CN102569019B - Shallow trench isolation forming method - Google Patents
Shallow trench isolation forming method Download PDFInfo
- Publication number
- CN102569019B CN102569019B CN201010593561.9A CN201010593561A CN102569019B CN 102569019 B CN102569019 B CN 102569019B CN 201010593561 A CN201010593561 A CN 201010593561A CN 102569019 B CN102569019 B CN 102569019B
- Authority
- CN
- China
- Prior art keywords
- etching
- etch
- phosphoric acid
- etch rate
- acid solution
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Element Separation (AREA)
Abstract
The embodiment of the invention discloses a dielectric film etching method and a shallow trench isolation forming method. The dielectric film etching method comprises the steps as follows: building a corresponding relationship between an activity period and an etching rate of an etching solution, namely a first corresponding relationship; determining the etching rate of the etching solution in the present activity period according to the first corresponding relationship, namely a first etching rate; calculating out a first etching time according to the thickness of a dielectric film to be removed by etching and the first etching rate; and etching the dielectric film by the etching solution which lasts for a first etching time. The technical scheme provided by the invention can enable dielectric film etched in different etching batches to have same etching degree, can improve the structure of a semiconductor device at the same time, and further improves the electric properties of the semiconductor device.
Description
Technical field:
The present invention relates to technical field of manufacturing semiconductors, relate in particular to a kind of shallow-trench isolation formation method.
Background technology:
Shallow-trench isolation (STI) is the optional technique of one of making isolated area between transistor active area in semiconductor wafer, because it has higher space utilization rate in semiconductor device structure, therefore this technology is particularly useful for making sub-0.25um device, be substituted traditional local oxidation of silicon technique (LOCOS), in large scale integrated circuit, be widely used.
Shallow grooved-isolation technique mainly comprises three steps: etching groove, oxide are filled and cmp.Before etching groove; isolating oxide layer and silicon nitride medium film on semiconductor wafer surface, are formed successively; wherein; silicon nitride medium film is the grinding-material that one deck is firm; for protecting active area at oxide filling process; and the barrier material that conduct is ground in cmp, isolating oxide layer is avoided chemistry for the protection of active area and is stain in removal silicon nitride medium film.Conventionally after cmp step, also can comprise etching removal silicon nitride medium film step, in this step, pass through phosphoric acid solution erosion removal silicon nitride medium film.The general silicon nitride medium film that adopts fixing etch period etching to remove different batches of industry at present,
But there is following defect in above-mentioned technique: the etch rate difference of the silicon nitride medium film of different batches semiconductor wafer, make its final etching degree difference, exist the silicon nitride medium film of part batch semiconductor wafer not by complete etching, and the silicon nitride medium film of another part batch semiconductor wafer is damaged to the structure of lower floor after by over etching.Need to do over again in order to solve this defect, therefore can cause the increase of etch period and cost.Above-mentioned defect is not only present in the silicon nitride medium film etch step of shallow grooved-isolation technique, and other adopts in the deielectric-coating etch step of same process, also has similar defect.This defect can further have influence on the structure of the semiconductor device of formation, finally has influence on the electric property of semiconductor device.
Summary of the invention
For solving the problems of the technologies described above, the object of the present invention is to provide a kind of deielectric-coating lithographic method, to solve the not identical problem of etching degree of deielectric-coating of different batches; Another object of the present invention is to provide a kind of shallow-trench isolation formation method, to solve the not identical problem of etching degree of silicon nitride medium film of different batches, improve the structure of the semiconductor device forming, and then improve the electric property of semiconductor device.
For addressing the above problem, the embodiment of the present invention provides following technical scheme:
The embodiment of the present invention provides a kind of shallow-trench isolation formation method, after cmp, comprising:
Set up the corresponding relation of phosphoric acid solution activity cycle and its etch rate to silicon nitride medium film, i.e. the first corresponding relation;
Determine the etch rate of the phosphoric acid solution in current activity cycle according to described the first corresponding relation, i.e. the first etch rate;
Thickness and first etch rate of the silicon nitride medium film of removing according to required etching calculate the first etch period;
Apply silicon nitride medium film described in described phosphoric acid solution etching, the duration is the first etch period.
After silicon nitride medium film etching, comprising:
Set up the corresponding relation of phosphoric acid solution activity cycle and its etch rate to isolating oxide layer, i.e. the second corresponding relation;
Determine the etch rate of the phosphoric acid solution in current activity cycle according to described the second corresponding relation, i.e. the second etch rate;
Thickness and second etch rate of the isolating oxide layer of removing according to required etching calculate the second etch period;
Apply isolating oxide layer described in described phosphoric acid solution etching, the duration is the second etch period.
Preferably,
When equaling isolating oxide layer and form, the thickness of the isolating oxide layer of required removal retains the difference of thickness after thickness and default etching.
Preferably, after isolating oxide layer etching, also comprise:
Apply described phosphoric acid solution and continue isolating oxide layer described in etching, the duration is the 3rd etch period;
Described the 3rd etch period is the excessive etch period of setting, to prevent etching residue.
Preferably,
Described the 3rd etch period is 5% of the first etch period and the second etch period sum.
Compared with prior art, technique scheme has the following advantages:
The technical scheme that the embodiment of the present invention provides, by the etching solution activity cycle of foundation and the corresponding relation of etch rate, the deielectric-coating that can be different batches semiconductor wafer according to etching solution activity cycle is selected the different etch period of coupling, and then make the etching degree of different etching batch deielectric-coating identical, can improve the structure of semiconductor device, and then improve the electric property of semiconductor device simultaneously.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
The deielectric-coating lithographic method schematic flow sheet that Fig. 1 provides for the embodiment of the present invention one;
The shallow-trench isolation formation method flow schematic diagram that Fig. 2 provides for the embodiment of the present invention two;
The phosphoric acid solution activity cycle that Fig. 3 provides for the embodiment of the present invention two and the corresponding relation schematic diagram of its etch rate to silicon nitride medium film;
Shallow groove isolation structure schematic diagram after the cmp that Fig. 4 provides for the embodiment of the present invention three;
Shallow groove isolation structure schematic diagram after the etching that Fig. 5 provides for the embodiment of the present invention three completes;
The part schematic flow sheet of the shallow-trench isolation formation method that Fig. 6 provides for the embodiment of the present invention three;
The phosphoric acid solution activity cycle that Fig. 7 provides for the embodiment of the present invention three and the corresponding relation schematic diagram of its etch rate to isolating oxide layer.
Embodiment
Just as described in the background section, the semiconductor wafer deielectric-coating that in prior art is different batches adopts identical etch period, there is the etch rate difference of the silicon nitride medium film of different batches semiconductor wafer, make the defect that its etching degree is different, this defect can further have influence on the structure of the semiconductor device of formation, finally has influence on the electric property of semiconductor device.
Study discovery through inventor, produce above-mentioned defect former because: there are multiple different activity cycles in etching solution, the etch rate difference of etching solution in the different etching cycles to dielectric layer, as use the phosphoric acid solution of hour the etch rate of silicon nitride medium film to be significantly greater than to the etch rate of the phosphoric acid solution that has used five hours, and in the scheme of prior art, while not considering different etching batch, etching solution is in different activity cycles, it is the etch rate difference of different etching batch, therefore the etch period of different etching batch should be adjusted according to the current etch rate of etching solution.
On basis based on above-mentioned research, the embodiment of the present invention provides a kind of deielectric-coating lithographic method, comprises the following steps:
Set up the corresponding relation of etching solution activity cycle and etch rate, i.e. the first corresponding relation;
Determine the etch rate of the etching solution in current activity cycle according to described the first corresponding relation, i.e. the first etch rate;
Deielectric-coating thickness and described the first etch rate removed according to required etching calculate the first etch period;
Apply deielectric-coating described in described etching solution etching, the duration is the first etch period.
While being specifically applied in shallow-trench isolation formation, the embodiment of the present invention also provides a kind of shallow-trench isolation formation method, after cmp, comprises the following steps:
Set up the corresponding relation of phosphoric acid solution activity cycle and its etch rate to silicon nitride medium film, i.e. the first corresponding relation;
Determine the etch rate of the phosphoric acid solution in current activity cycle according to described the first corresponding relation, i.e. the first etch rate;
Thickness and first etch rate of the silicon nitride medium film of removing according to required etching calculate the first etch period;
Apply silicon nitride medium film described in described phosphoric acid solution etching, the duration is the first etch period.
The technical scheme that the embodiment of the present invention provides, by the etching solution activity cycle of foundation and the corresponding relation of etch rate, the deielectric-coating that can be different batches semiconductor wafer according to etching solution activity cycle is selected the different etch period of coupling, and then make the etching degree of different etching batch deielectric-coating identical, can improve the structure of semiconductor device, and then improve the electric property of semiconductor device simultaneously.
It is more than the application's core concept, below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, rather than whole embodiment.Based on the embodiment in the present invention, those of ordinary skills, not making the every other embodiment obtaining under creative work prerequisite, belong to the scope of protection of the invention.
A lot of details are set forth in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here and implement, those skilled in the art can do similar popularization without prejudice to intension of the present invention in the situation that, and therefore the present invention is not subject to the restriction of following public specific embodiment.
Secondly, the present invention is described in detail in conjunction with schematic diagram, in the time that the embodiment of the present invention is described in detail in detail; for ease of explanation; represent that the profile of device architecture can disobey general ratio and do local amplification, and described schematic diagram is example, it should not limit the scope of protection of the invention at this.In addition in actual fabrication, should comprise, the three-dimensional space of length, width and the degree of depth.
Embodiment mono-:
The embodiment of the present invention provides a kind of deielectric-coating lithographic method, as shown in the deielectric-coating lithographic method schematic flow sheet that Fig. 1 provides, specifically can comprise the following steps:
Step S101, sets up the corresponding relation of etching solution activity cycle and etch rate, i.e. the first corresponding relation.
The etching solution in different etching cycle can be different to the etch rate of same deielectric-coating, and the etch rate of the deielectric-coating of the etching solution in same etching cycle to different materials also can be different.In this step, can be according to the corresponding relation of determining etching solution activity cycle and etch rate in actual production by a large amount of experimental datas of obtaining, described corresponding relation can pass through the form record of chart.
Step S102, according to the etch rate of the definite etching solution in current activity cycle of described the first corresponding relation, i.e. the first etch rate.
In this step, described etching solution current in activity cycle can collect from board equipment, activity cycle can be defined as the setting duration having used, and by inquiring about the chart of the first corresponding relation, can determine the etch rate of the etching solution in current activity cycle.
Step S103, deielectric-coating thickness and described the first etch rate removed according to required etching calculate the first etch period.
Deielectric-coating thickness can collect by the on-line measurement website of semiconductor wafer, thickness when the deielectric-coating thickness that required etching is removed can equal deielectric-coating formation, also the thickness can be less than deielectric-coating and form time, retains the deielectric-coating of setting thickness when can etching removing the deielectric-coating of segment thickness.The product of described the first etch period and described the first etch rate is the deielectric-coating thickness that required etching is removed.
Step S104, applies deielectric-coating described in described etching solution etching, and the duration is the first etch period.
In addition, because etching apparatus and technological parameter exist certain unsteadiness, can cause realizing default etching degree completely, therefore, after above-mentioned deielectric-coating etching, can also comprise:
Apply deielectric-coating described in described etching solution etching, the duration is the second etch period;
Described the second etch period is the excessive etch period of setting, to prevent deielectric-coating etching residue.
This scheme be equal to application described etching solution etching described in deielectric-coating, the duration is the first etch period and the second etch period sum.
Conventionally described excessive etch period (the second etch period) can be a fixing value, and in the present embodiment, described excessive etch period (the second etch period) can be 5% of described the first etch period.
The technical scheme that the embodiment of the present invention provides, by the etching solution activity cycle of foundation and the corresponding relation of etch rate, the deielectric-coating that can be different batches semiconductor wafer according to etching solution activity cycle is selected the different etch period of coupling, and then make the etching degree of different etching batch deielectric-coating identical, can improve the structure of semiconductor device, and then improve the electric property of semiconductor device simultaneously.
Embodiment bis-:
The technical scheme that the present embodiment provides embodiment mono-is applied to shallow-trench isolation and forms in technique, a kind of shallow-trench isolation formation method is provided, after cmp, the shallow-trench isolation providing as Fig. 2 forms as shown in method flow schematic diagram, specifically can comprise the following steps:
Step S201, sets up the corresponding relation of phosphoric acid solution activity cycle and its etch rate to silicon nitride medium film, i.e. the first corresponding relation.
The phosphoric acid solution in different etching cycle can be different to the etch rate of silicon nitride medium film.In this step, can be according to the corresponding relation of determining phosphoric acid solution activity cycle and its etch rate to silicon nitride medium film in actual production by a large amount of experimental datas of obtaining, described corresponding relation can pass through the form record of chart.As shown in Figure 3, be the corresponding relation schematic diagram of a kind of typical phosphoric acid solution activity cycle and its etch rate to silicon nitride medium film.
Step S202, according to the etch rate of the definite phosphoric acid solution in current activity cycle of described the first corresponding relation, i.e. the first etch rate.
In this step, described phosphoric acid solution current in activity cycle can collect from board equipment, activity cycle can be defined as the setting duration having used, by inquiring about the chart of the first corresponding relation, can determine phosphoric acid etching solution in the current activity cycle etch rate to silicon nitride medium film.
Step S203, thickness and first etch rate of the silicon nitride medium film of removing according to required etching calculate the first etch period.
The thickness of silicon nitride medium film can collect by the on-line measurement website of semiconductor wafer, and the product of described the first etch period and described the first etch rate is the thickness of the silicon nitride medium film of required etching removal.
Step S204, applies silicon nitride medium film described in described phosphoric acid solution etching, and the duration is the first etch period.
The technical scheme that the embodiment of the present invention provides, by the phosphoric acid solution activity cycle of foundation and the corresponding relation of etch rate, can be the different etch period of the silicon nitride medium film selection coupling in different batches shallow grooved-isolation technique according to etching solution activity cycle, and then make the etching degree of different etching batch silicon nitride medium film identical, can improve the structure of shallow-trench isolation, and then improve the electric property of semiconductor device simultaneously.
Embodiment tri-:
As shown in the shallow groove isolation structure schematic diagram after the cmp that Fig. 4 provides; form in technique in shallow-trench isolation; silicon nitride medium film also comprises one deck isolating oxide layer 402 401 times conventionally,, in the time that CMP technique is removed silicon nitride medium film, avoids chemistry and stains for the protection of active area.The thickness of described isolating oxide layer is about 150 dusts.Existing a kind of shallow-trench isolation forms in technique, in etch silicon nitride deielectric-coating, need etching to remove the isolating oxide layer of segment thickness, the isolating oxide layer retaining is used by subsequent technique, as shown in shallow groove isolation structure schematic diagram after the etching providing as Fig. 5 completes, because the isolating oxide layer 402a retaining has larger impact to the electrical properties of semiconductor device, therefore, need to control accurately the thickness of retained isolating oxide layer, so need to control accurately the duration of phosphoric acid solution etching.
In prior art, conventionally adopt the duration of fixing phosphoric acid solution etching, because of the etch rate difference to isolating oxide layer in phosphoric acid solution different activities period, therefore in prior art, different batches shallow-trench isolation forms the thickness difference of the final isolating oxide layer retaining in technique, make the structure difference of the semiconductor device forming, and then make the electric property difference of semiconductor device, cannot meet the demand of application.
For this reason, the present embodiment provides the another kind of way of realization of shallow-trench isolation formation method, and as shown in the schematic flow sheet that Fig. 6 provides, the difference of itself and embodiment bis-is, further comprising the steps of:
Step S601, sets up the corresponding relation of phosphoric acid solution activity cycle and its etch rate to isolating oxide layer, i.e. the second corresponding relation.
The phosphoric acid solution in different etching cycle can be different to the etch rate of isolating oxide layer.In this step, can be according to the corresponding relation of determining phosphoric acid solution activity cycle and its etch rate to isolating oxide layer in actual production by a large amount of experimental datas of obtaining, described corresponding relation can pass through the form record of chart.As shown in Figure 7, be the corresponding relation schematic diagram of a kind of typical phosphoric acid solution activity cycle and its etch rate to isolating oxide layer.
Step S602, according to the etch rate of the definite phosphoric acid solution in current activity cycle of described the second corresponding relation, i.e. the second etch rate.
In this step, described phosphoric acid solution current in activity cycle can collect from board equipment, activity cycle can be defined as the setting duration having used, by inquiring about the chart of the second corresponding relation, can determine phosphoric acid etching solution in the current activity cycle etch rate to isolating oxide layer.
Step S603, thickness and second etch rate of the isolating oxide layer of removing according to required etching calculate the second etch period.
In this step, when equaling isolating oxide layer and form, the thickness of the isolating oxide layer that required etching is removed retains the difference of thickness after thickness and default etching.When removing the isolating oxide layer of segment thickness by phosphoric acid solution etching, retain the isolating oxide layer of setting thickness.The product of described the second etch period and described the second etch rate is the isolation oxidation layer thickness that required etching is removed.
Step S604, applies isolating oxide layer described in described phosphoric acid solution etching, and the duration is the second etch period.
Two technical schemes that provide in conjunction with the embodiments, the technical scheme that the present embodiment provides is equal to simultaneously silicon nitride medium film and described isolating oxide layer described in etching of application phosphoric acid solution, and the duration is the second etch period sum described in the first etch period described in embodiment bis-and the present embodiment.
In addition, because etching apparatus and technological parameter exist certain unsteadiness, can cause realizing completely default etching degree and retain the isolation oxidation layer thickness of setting, therefore, on the basis of such scheme, can also comprise:
Apply described phosphoric acid solution and continue isolating oxide layer described in etching, the duration is the 3rd etch period;
Described the 3rd etch period is the excessive etch period of setting, to prevent etching residue.
This scheme be equal to application described phosphoric acid solution etching described in silicon nitride medium film and described isolating oxide layer, the duration is the first etch period, the second etch period and the 3rd etch period sum.
Conventionally described excessive etch period (the 3rd etch period) can be a fixing value, and in the present embodiment, described excessive etch period (the 3rd etch period) can be 5% of described the first etch period and the second etch period sum.
The technical scheme that the embodiment of the present invention provides, by the etching solution activity cycle of foundation and the corresponding relation of etch rate, the deielectric-coating that can be different batches semiconductor wafer according to etching solution activity cycle is selected the different etch period of coupling, and then make the etching degree of different etching batch deielectric-coating identical, can improve the structure of semiconductor device, and then improve the electric property of semiconductor device simultaneously.
In this specification, various piece adopts the mode of going forward one by one to describe, and what each part stressed is and the difference of other parts, between various piece identical similar part mutually referring to.To the above-mentioned explanation of the disclosed embodiments, make professional and technical personnel in the field can realize or use the present invention.To be apparent for those skilled in the art to the multiple modification of these embodiment, General Principle as defined herein can, in the situation that not departing from the spirit or scope of the present invention, realize in other embodiments.Therefore, the present invention will can not be restricted to embodiment illustrated herein, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
Claims (4)
1. a shallow-trench isolation formation method, is characterized in that, after cmp, comprising:
Set up the corresponding relation of phosphoric acid solution activity cycle and its etch rate to silicon nitride medium film, i.e. the first corresponding relation;
Determine the etch rate of the phosphoric acid solution in current activity cycle according to described the first corresponding relation, i.e. the first etch rate;
Thickness and first etch rate of the silicon nitride medium film of removing according to required etching calculate the first etch period;
Apply silicon nitride medium film described in described phosphoric acid solution etching, the duration is the first etch period;
Wherein, after silicon nitride medium film etching, comprising:
Set up the corresponding relation of phosphoric acid solution activity cycle and its etch rate to isolating oxide layer, i.e. the second corresponding relation;
Determine the etch rate of the phosphoric acid solution in current activity cycle according to described the second corresponding relation, i.e. the second etch rate;
Thickness and second etch rate of the isolating oxide layer of removing according to required etching calculate the second etch period;
Apply isolating oxide layer described in described phosphoric acid solution etching, the duration is the second etch period.
2. shallow-trench isolation formation method according to claim 1, is characterized in that:
When equaling isolating oxide layer and form, the thickness of the isolating oxide layer of required removal retains the difference of thickness after thickness and default etching.
3. shallow-trench isolation formation method according to claim 1, is characterized in that, after isolating oxide layer etching, also comprises:
Apply described phosphoric acid solution and continue isolating oxide layer described in etching, the duration is the 3rd etch period;
Described the 3rd etch period is the excessive etch period of setting, to prevent etching residue.
4. shallow-trench isolation formation method according to claim 3, is characterized in that:
Described the 3rd etch period is 5% of the first etch period and the second etch period sum.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010593561.9A CN102569019B (en) | 2010-12-17 | 2010-12-17 | Shallow trench isolation forming method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010593561.9A CN102569019B (en) | 2010-12-17 | 2010-12-17 | Shallow trench isolation forming method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102569019A CN102569019A (en) | 2012-07-11 |
| CN102569019B true CN102569019B (en) | 2014-06-04 |
Family
ID=46414140
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201010593561.9A Active CN102569019B (en) | 2010-12-17 | 2010-12-17 | Shallow trench isolation forming method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102569019B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107316821B (en) * | 2016-04-27 | 2021-03-12 | 中芯国际集成电路制造(上海)有限公司 | Depth stability detection method |
| CN107331613A (en) * | 2017-06-26 | 2017-11-07 | 上海华力微电子有限公司 | A kind of method of accurate control oxide thickness in phosphoric acid etching technics |
| CN115241058B (en) * | 2022-09-23 | 2023-03-10 | 广州粤芯半导体技术有限公司 | Semiconductor device etching method and semiconductor device manufacturing method |
| CN116230525B (en) * | 2023-05-08 | 2023-08-29 | 粤芯半导体技术股份有限公司 | Wafer Cleaning Method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1472361A (en) * | 2002-08-01 | 2004-02-04 | 台湾积体电路制造股份有限公司 | Etching agent and application for improving etching selectvie ratio |
| CN1914713A (en) * | 2004-03-22 | 2007-02-14 | 三益半导体工业株式会社 | Schedule control method in spin etching and spin etching system |
| CN101281374A (en) * | 2007-04-06 | 2008-10-08 | 中芯国际集成电路制造(上海)有限公司 | Method for testing whether etching solution is valid or not |
| CN101388323A (en) * | 2007-09-10 | 2009-03-18 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Semi-conductor processing process controlling method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100859490B1 (en) * | 2007-06-12 | 2008-09-23 | 주식회사 동부하이텍 | Method for fabricating semi-conductor transistor |
-
2010
- 2010-12-17 CN CN201010593561.9A patent/CN102569019B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1472361A (en) * | 2002-08-01 | 2004-02-04 | 台湾积体电路制造股份有限公司 | Etching agent and application for improving etching selectvie ratio |
| CN1914713A (en) * | 2004-03-22 | 2007-02-14 | 三益半导体工业株式会社 | Schedule control method in spin etching and spin etching system |
| CN101281374A (en) * | 2007-04-06 | 2008-10-08 | 中芯国际集成电路制造(上海)有限公司 | Method for testing whether etching solution is valid or not |
| CN101388323A (en) * | 2007-09-10 | 2009-03-18 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Semi-conductor processing process controlling method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102569019A (en) | 2012-07-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI415214B (en) | Integrated circuits and methods for forming shallow trench isolation structures | |
| CN102569019B (en) | Shallow trench isolation forming method | |
| CN104956482B (en) | Semiconductor substrate and manufacturing method for photon and electronic structure | |
| JP2004363595A (en) | Method for filling up separation structure having high aspect ratio with material based on polysilazane | |
| CN103011048B (en) | Isolation structure, have its semiconductor device and manufacture the method for this isolation structure | |
| CN105161412A (en) | Method for improving wafer edge product yield | |
| CN103227111B (en) | The manufacture method of semiconductor device | |
| KR100741876B1 (en) | Manufacturing method of semiconductor device having trench isolation prevented from divot | |
| CN103021926B (en) | Formation method of STI (shallow trench isolation) structure and formation method of memory | |
| CN102543667A (en) | Forming method of graph of aligned layer on silicon chip | |
| CN102339733A (en) | Method for controlling critical size of graph on uneven silicon slice surface | |
| CN103633140A (en) | Two-step shallow trench isolation (STI) process | |
| CN103545256B (en) | Form the method for cmos device | |
| CN102243995B (en) | The integrated approach of different thickness grid oxygen in high-pressure process | |
| CN101958268B (en) | Method for producing isolating structure | |
| CN101777513A (en) | Method for improving growth of gate oxide layer and manufacture method of shallow groove isolating process | |
| CN110391184B (en) | Method for manufacturing zero-layer interlayer film | |
| CN102148181A (en) | Method for forming shallow trench isolation structure | |
| JP2007242977A (en) | High breakdown voltage semiconductor integrated circuit device | |
| CN105633021A (en) | Method for manufacturing semiconductor element | |
| CN103165435A (en) | Silicon etching process | |
| CN102437020B (en) | Wafer control slice and forming method thereof | |
| CN102956535A (en) | Semiconductor device and manufacturing method thereof | |
| CN104867860A (en) | Manufacturing method of shallow trench isolating structure | |
| CN101834128B (en) | Method for manufacturing semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: 214028 Xinzhou Road, Wuxi national hi tech Industrial Development Zone, Jiangsu, China, No. 8 Patentee after: Wuxi Huarun Shanghua Technology Co., Ltd. Address before: 214028 Wuxi provincial high tech Industrial Development Zone, Hanjiang Road, No. 5, Jiangsu, China Co-patentee before: Wuxi Huarun Shanghua Technology Co., Ltd. Patentee before: Wuxi CSMC Semiconductor Co., Ltd. |