CN102566682B - Blade server motherboard - Google Patents
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- CN102566682B CN102566682B CN201110459110.0A CN201110459110A CN102566682B CN 102566682 B CN102566682 B CN 102566682B CN 201110459110 A CN201110459110 A CN 201110459110A CN 102566682 B CN102566682 B CN 102566682B
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Abstract
The invention provides a blade server motherboard which comprises multiple PCB (printed circuit board) layers, wherein the multiple PCB layers comprise digital electrical layers or digital ground layers, and signal layers. The blade server motherboard is characterized in that a digital electrical layer or digital ground layer is arranged between every two signal layers. Through the blade server motherboard provided by the invention, the EMI (electro-magnetic interference) is reduced, and the stability of the motherboard when the motherboard is electrified and running is enhanced.
Description
Technical field
The present invention relates to computer realm substantially, more specifically, relates to a kind of mainboard of blade server.
Background technology
AMD platform adopts HT bussing technique to realize the interconnected communication between CPU, and HT technology is bussing technique interconnected between a kind of CPU, has two-way, serial, high bandwidth, low delay, the characteristic such as point-to-point.Current HT 3.0 agreement regulation bus dominant frequency are up to 3.2GHz, and rising edge and negative edge 1 clock period carry out respectively a data transfer, so maximum transmission rate reaches 6.4GT/s.The G34 platform of main flow is supported MagnyCours series CPU at present, and every processor all has 2 nodes (Node), the HT bus of 4 16 bits (bit), and the interconnected needs of HT bus are followed certain principle.At present the whole world only has the exploitation of seldom several companies based on AMD platform Si road blade server product, and HT connected mode is different, some realizations annular connection, some realizations annular be connected with semidecussation.Different connected modes, has larger impact for function and the performance of blade server.
A kind of four road server master boards are provided in prior art, comprise four processors, memory module, peripheral input/output component, it is characterized in that, also comprise the peripheral component interconnect equipment that the peripheral component interconnect bridge chip, South Bridge chip of expansion, the peripheral component interconnect bus by expansion connect, wherein memory module is connected with processor, and peripheral input/output component is connected with South Bridge chip; Between processor, between the peripheral component interconnect bridge chip of processor, expansion and South Bridge chip by super transfer bus transmission of information.
Above-mentioned prior art has improved the performance of the extensibility, availability of blade server etc. aspect to a certain extent, yet for PCB (printed circuit board (PCB)) the layer structure of server master board, do not improve, make this server master board there is the defects such as EMI interference performance is poor, DDR3 allowance (Margin) is not enough.
Summary of the invention
The defects such as, DDR3 allowance (Margin) poor for server master board EMI interference performance of the prior art is not enough.The present invention proposes a kind of mainboard of blade server, solved the technical matters that how to improve mainboard of blade server EMI interference performance and how to increase DDR3 Margin.
According to an aspect of the present invention, a kind of mainboard of blade server is provided, comprise a plurality of PCB layers, described a plurality of PCB layer comprises numeral electricity layer or digital strata and signals layer, it is characterized in that, between every two described signals layers, all there is described digital strata or numeral electricity layer, wherein, described signals layer is used to the device on described mainboard of blade server to transmit signal, described numeral electricity layer or digital strata form closed-loop path for combining with described signals layer, thereby provide return path for described signal.
In this mainboard of blade server, described mainboard of blade server comprises 16 layers of PCB layer and a plurality of CPU, and wherein, ground floor is signals layer, for CPU Memory Controller Hub is connected with DIMMS groove; The second layer is numeral electricity layer or digital strata; The 3rd layer is signals layer, for CPU Memory Controller Hub is connected with DIMMS groove; The 4th layer of bit digital electricity layer or digital strata; Layer 5 is signals layer, for described CPU is interconnected; Layer 6 is numeral electricity layer or digital strata; Layer 7 is signals layer, for described CPU is interconnected; The 8th layer is numeral electricity layer or digital strata; The 9th layer is numeral electricity layer or digital strata; The tenth layer is signals layer, for described CPU is interconnected; Eleventh floor is numeral electricity layer or digital strata; Floor 12 is signals layer, for described CPU is interconnected; The 13 layer is numeral electricity layer or digital strata; The 14 layer is signals layer, for CPU Memory Controller Hub is connected with DIMMS groove, and for described CPU is interconnected; The 15 layer is numeral electricity layer or digital strata; And the 16 layer be signals layer, for CPU Memory Controller Hub is connected with DIMMS groove.
In this mainboard of blade server, described a plurality of CPU comprises a CPU, the 2nd CPU, the 3rd CPU and the 4th CPU, wherein, between a described CPU, described the 2nd CPU, described the 3rd CPU and described the 4th CPU, interconnect, a described CPU is connected with north bridge chips.
In this mainboard of blade server, described layer 5 is for being connected a described CPU by HT bus with described the 2nd CPU; Described layer 7 is used for by HT bus, a described CPU being connected with described the 2nd CPU, and for described the 3rd CPU and described the 4th CPU being interconnected by HT bus; The described ten layer for being connected described the 2nd CPU by HT bus with described the 3rd CPU; And described the 14 layer for CPU Memory Controller Hub is connected with DIMMS groove, and for a described CPU and described the 3rd CPU being interconnected by HT bus.
In this mainboard of blade server, described CPU is AMD Opteron 6000 series processors.
In this mainboard of blade server, described HT bus is 16 bit HT 3.0 buses.
In this mainboard of blade server, further comprise: infinite bandwidth subcard, is connected with infinite bandwidth switch with the PCI-E slot of described mainboard of blade server.
In this mainboard of blade server, described infinite bandwidth subcard is connected with PCI-E slot by the first connector, and is connected with described infinite bandwidth switch by the second connector.
In this mainboard of blade server, described infinite bandwidth subcard is positioned at described mainboard of blade server top.
The described mainboard of blade server of the application of the invention, can reduce EMI and disturb, and improve DDR3 Margin, makes system move stability and safety more.
Other features and advantages of the present invention will be set forth in the following description, and, partly from instructions, become apparent, or understand by implementing the present invention.Object of the present invention and other advantages can be realized and be obtained by specifically noted structure in the instructions write, claims and accompanying drawing.
Accompanying drawing explanation
Accompanying drawing is used to provide a further understanding of the present invention, and forms a part for instructions, for explaining the present invention, is not construed as limiting the invention together with embodiments of the present invention.In the accompanying drawings:
Fig. 1 shows the PCB rhythmo structure that arrives according to an embodiment of the invention mainboard of blade server.
Fig. 2 shows the interconnected relationship between four CPU according to an embodiment of the invention.
Fig. 3 shows the layout of four road mainboard of blade servers according to an embodiment of the invention.
Embodiment
Below in conjunction with accompanying drawing, the preferred embodiments of the present invention are described, should be appreciated that preferred embodiment described herein, only for description and interpretation the present invention, is not intended to limit the present invention.
The invention discloses a kind of mainboard of blade server, this mainboard of blade server comprises a plurality of PCB layers, the plurality of PCB layer comprises numeral electricity layer, digital strata and signals layer, wherein, between every two signals layers, all there is digital strata or numeral electricity layer, that is to say, not having adjacent two layers is all the situation of signals layer.Wherein, numeral electricity layer or digital strata form closed-loop path for combining with signals layer, thereby provide return path for signal.
By above-mentioned mainboard of blade server disclosed in this invention, reduced EMI interference, strengthened stability when mainboard powers on operation.
In addition, by above-mentioned arrangement, sufficient DDR3 Margin is provided, make the upgrading of AMD CPU of future generation can not change motherboard layout and can smoothly support Interlagos CPU, sufficient Margin makes supported internal memory work maximum frequency reach 1600MHz, has surpassed current main-stream internal memory frequency of operation 1066MHz and 1333MHz.Have benefited from the lifting of internal memory dominant frequency, internal memory theoretical bandwidth performance is promoted to 12.8GB/s by the 10.664GB/s of main flow, has promoted ratio and has reached 20%.
In a preferred embodiment, mainboard of blade server can comprise 16 layers of PCB layer and four CPU (CPU0, CPU1, CPU2, CPU3), and plate thickness is 90 Mills.Preferably, Fig. 1 shows the PCB rhythmo structure that arrives according to an embodiment of the invention mainboard of blade server, and concrete rhythmo structure is as follows:
| Flaggy | Wiring rule |
| Layer 100 | Interconnected (for transmitting DDR3 signal) of CPU Memory Controller Hub and DIMMS groove |
| Layer 102 | Numeral electricity layer or digital strata |
| Layer 104 | CPU Memory Controller Hub and DIMMS groove interconnected |
| Layer 106 | Numeral electricity layer or digital strata |
| Layer 108 | CPU0 and CPU3 HT bus are cross interconnected |
| Layer 110 | Numeral electricity layer or digital strata |
| Layer 112 | The HT bus of CPU0 and CPU1 is interconnected, and the HT bus of CPU2 and CPU3 is interconnected |
| Layer 114 | Numeral electricity layer or digital strata |
| Layer 116 | Numeral electricity layer or digital strata |
| Layer 118 | CPU1 and CPU2 HT bus are cross interconnected |
| Layer 120 | Numeral electricity layer or digital strata |
| Layer 122 | The HT bus of CPU0 and CPU1 is interconnected, and the HT bus of CPU1 and CPU3 is interconnected |
| Layer 124 | Numeral electricity layer or |
| Layer | |
| 126 | CPU Memory Controller Hub and DIMMS groove interconnected; The HT bus of CPU0 and CPU3 is interconnected |
| |
Numeral electricity layer or digital strata |
| Layer 130 | CPU Memory Controller Hub and DIMMS groove interconnected; |
In the PCB of this example stacked, layer 100, layer 104, layer 108, layer 112, layer 118, layer 122, layer 126 and layer 130 are signals layer, for transmitting signal.And between above-mentioned signals layer, all at least there is layer digital electricity layer or a digital strata, and this numeral electricity layer or digital strata form closed-loop path for combining with signals layer, thus the signal transmitting for signals layer provides return path.Wherein, signals layer can interconnected for forming between CPU Memory Controller Hub and DIMMS groove (that is, for transmitting DDR3 signal), and/or between a plurality of CPU, forming interconnected (that is, between a plurality of CPU, transmitting signal).
In the present embodiment, the CPU on mainboard of blade server can realize entirely interconnected by high speed HT bus.Fig. 2 shows the interconnected relationship between four CPU according to an embodiment of the invention.
By above-mentioned arrangement, make every layer signal layer to form closure signal loop with nearest digital strata, reduce EMI interference, thereby strengthened the stability that mainboard powers on and moves.
In addition, by above-mentioned arrangement, sufficient DDR3 Margin is provided, make the upgrading of AMD CPU of future generation can not change motherboard layout (layout) and can smoothly support Interlagos CPU, sufficient Margin makes supported internal memory work maximum frequency reach 1600MHz, has surpassed current main-stream internal memory frequency of operation 1066MHz and 1333MHz.Have benefited from the lifting of internal memory dominant frequency, internal memory theoretical bandwidth performance is promoted to 12.8GB/s by the 10.664GB/s of main flow, has promoted ratio and has reached 20%.
In yet another embodiment of the present invention, provide a kind of mainboard of blade server of supporting infinite bandwidth (Infiniband).
In blade server application, the application of Infiniband network is more and more extensive, and its transfer rate can arrive 40Gbps, postpones only 100ns, irreplaceable in the effect of high-performance computing sector.But the limitations in density of Shou Si road mainboard of blade server, mainboard cannot integrated quadruple according to rate infinite bandwidth (QDR Infiniband) exchange chip.Thus, the present embodiment is realized the support for QDR Infiniband network by detain the form of a subcard on mainboard.At mainboard end, a connector is installed, this connector PIN pin connects the signal of 1 group of PCI-E 2.0x16, and the two-way transfer rate limit of checking the mark is 5Gbps*8, i.e. 40Gbps meets the transmission bandwidth of QDR Infiniband just.At a subcard of mainboard of blade server top button, be connected with this connector, can realize the integrated Infiniband function of high density blade, that is to say, this subcard for transmitting data between mainboard and Infiniband switch.Wherein, this subcard is installed in the top of mainboard of blade server, highlights, thereby occupy the surface area of mainboard of blade server seldom from the surface of blade server.All mainboard of blade servers are all detained a subcard, and are connected to middle plate by connector, more therefrom plate is connected to Infiniband switch, can realize the interconnected Infiniband network of blade server.Wherein, above-mentioned Infiniband subcard also can directly be connected with Infiniband switch with PCI-E slot.
In addition, Fig. 3 shows the layout of four road mainboard of blade servers according to an embodiment of the invention.
By the described mainboard of blade server of the present embodiment, take full advantage of the space configuration Infiniband subcard of mainboard top, thereby saved the wiring area on mainboard.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any modification of doing, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (8)
1. a mainboard of blade server, comprise a plurality of PCB layers, described a plurality of PCB layer comprises numeral electricity layer or digital strata and signals layer, it is characterized in that between every two described signals layers, all thering is described digital strata or numeral electricity layer, wherein, described signals layer is used to the device on described mainboard of blade server to transmit signal, described numeral electricity layer or digital strata form closed-loop path for combining with described signals layer, thereby provide return path for described signal
Wherein, described mainboard of blade server comprises 16 layers of PCB layer and a plurality of CPU, and wherein,
Ground floor is signals layer, for CPU Memory Controller Hub is connected with DIMMS groove;
The second layer is numeral electricity layer or digital strata;
The 3rd layer is signals layer, for CPU Memory Controller Hub is connected with DIMMS groove;
The 4th layer of bit digital electricity layer or digital strata;
Layer 5 is signals layer, for described CPU is interconnected;
Layer 6 is numeral electricity layer or digital strata;
Layer 7 is signals layer, for described CPU is interconnected;
The 8th layer is numeral electricity layer or digital strata;
The 9th layer is numeral electricity layer or digital strata;
The tenth layer is signals layer, for described CPU is interconnected;
Eleventh floor is numeral electricity layer or digital strata;
Floor 12 is signals layer, for described CPU is interconnected;
The 13 layer is numeral electricity layer or digital strata;
The 14 layer is signals layer, for CPU Memory Controller Hub is connected with DIMMS groove, and for described CPU is interconnected;
The 15 layer is numeral electricity layer or digital strata; And
The 16 layer is signals layer, for CPU Memory Controller Hub is connected with DIMMS groove.
2. mainboard of blade server according to claim 1, it is characterized in that, described a plurality of CPU comprises a CPU, the 2nd CPU, the 3rd CPU and the 4th CPU, wherein, between a described CPU, described the 2nd CPU, described the 3rd CPU and described the 4th CPU, interconnect, a described CPU is connected with north bridge chips.
3. mainboard of blade server according to claim 2, is characterized in that,
Described layer 5 is for being connected a described CPU by HT bus with described the 2nd CPU;
Described layer 7 is used for by HT bus, a described CPU being connected with described the 2nd CPU, and for described the 3rd CPU and described the 4th CPU being interconnected by HT bus;
The described ten layer for being connected described the 2nd CPU by HT bus with described the 3rd CPU; And
Described the 14 layer for CPU Memory Controller Hub is connected with DIMMS groove, and for a described CPU and described the 3rd CPU being interconnected by HT bus.
4. mainboard of blade server according to claim 3, is characterized in that, described CPU is AMD Opteron6000 series processors.
5. mainboard of blade server according to claim 4, is characterized in that, described HT bus is 16 bit HT3.0 buses.
6. mainboard of blade server according to claim 5, is characterized in that, further comprises:
Infinite bandwidth subcard, is connected with infinite bandwidth switch with the PCI-E slot of described mainboard of blade server.
7. mainboard of blade server according to claim 6, is characterized in that, described infinite bandwidth subcard is connected with PCI-E slot by the first connector, and is connected with described infinite bandwidth switch by the second connector.
8. mainboard of blade server according to claim 6, is characterized in that, described infinite bandwidth subcard is positioned at described mainboard of blade server top.
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| CN201110459110.0A CN102566682B (en) | 2011-12-31 | 2011-12-31 | Blade server motherboard |
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| CN201110459110.0A CN102566682B (en) | 2011-12-31 | 2011-12-31 | Blade server motherboard |
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| CN102566682B true CN102566682B (en) | 2014-04-09 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1747620A (en) * | 2004-09-08 | 2006-03-15 | 华为技术有限公司 | Laminated structure of printing circuit board and multi-laminate laminated structure |
| CN101378618A (en) * | 2007-08-31 | 2009-03-04 | 鸿富锦精密工业（深圳）有限公司 | Printed circuit board |
| CN201781688U (en) * | 2009-06-16 | 2011-03-30 | 联想(北京)有限公司 | Printed circuit board and computer using same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1747620A (en) * | 2004-09-08 | 2006-03-15 | 华为技术有限公司 | Laminated structure of printing circuit board and multi-laminate laminated structure |
| CN101378618A (en) * | 2007-08-31 | 2009-03-04 | 鸿富锦精密工业（深圳）有限公司 | Printed circuit board |
| CN201781688U (en) * | 2009-06-16 | 2011-03-30 | 联想(北京)有限公司 | Printed circuit board and computer using same |
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Effective date of registration: 20170213 Address after: 124000 Panjin, Liaoning Province, coastal economic zone in the coastal area of the crown building, building 3018, room 3, Liaoning Patentee after: Dawning Information Systems (Liaoning) Co., Ltd. Address before: 300384 Tianjin city Xiqing District Huayuan Industrial Zone (outer ring) Haitai Huake Street No. 15 1-3 Patentee before: Sugon Information Industry Co., Ltd. |