CN102566175A - 一种阵列基板、液晶显示装置及阵列基板制作方法 - Google Patents

一种阵列基板、液晶显示装置及阵列基板制作方法 Download PDF

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CN102566175A
CN102566175A CN2011103822733A CN201110382273A CN102566175A CN 102566175 A CN102566175 A CN 102566175A CN 2011103822733 A CN2011103822733 A CN 2011103822733A CN 201110382273 A CN201110382273 A CN 201110382273A CN 102566175 A CN102566175 A CN 102566175A
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陈政鸿
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TCL China Star Optoelectronics Technology Co Ltd
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Abstract

本发明公开一种阵列基板、液晶显示装置及阵列基板制作方法。一种阵列基板，包括多个薄膜晶体管、与所述薄膜晶体管的漏极连接的第一画素电极，所述阵列基板还包括设在第一画素电极底层的相互绝缘的第二画素电极。本发明可以增加画素的穿透率、改善面板的视角色偏特性，并减轻因为电极线宽局部变异所形成的亮度不均(mura)现象。

Description

一种阵列基板、液晶显示装置及阵列基板制作方法
技术领域
本发明涉及液晶显示领域，更具体的说，涉及一种阵列基板、液晶显示装置及阵列基板制作方法。
背景技术
液晶显示装置包括液晶面板，液晶面板包括相互对置的阵列基板和彩色滤光板(CF)，中间注满了液晶。阵列基板上设有多个画素电极4，彩色滤光板上设有公共电极，调整画素电极4和公共电极之间的电压就能控制液晶分子的倾角，从而形成不同的灰阶。一般液晶显示器的视角比较小，采用PVA，PSVA等液晶显示模式可以具有较宽泛的视角，以PSVA(Polymer stability vertical alignment)为例，如图1所述，为一传统的聚合物稳定垂直对齐模式的画素设计，其画素电极4可以大致地分成四个区域且其电极狭缝分别朝向图示的A、B、C、D四个不同的方向，当上下板电极存在有电位差时，其画素设计所造成的电力线的形貌可将液晶分子大略地形成四个方向的倾倒，再通过液晶或是配向层中所存在的光或热反应材料，照光或是加热使得配向层表面的液晶分子固化并往四个方向形成预倾角，这就是一般所熟知的PSVA原理。
本发明文件所述的PSVA技术泛指广义的PSVA技术，可参考下面四篇介绍：
1.SID′04 Digest，p.1200；PSA
2.SID′09Digest，p.666；SC-PVA
3.IDW′09，p.747；SC-PVA
4.SID′10 Digest，p.595  FPA
一般PSVA之画素电极4呈现羽毛形状，在PSVA制程之加电压的过程中，画素电极4必须要存在着电极狭缝才可以利用电力线之分布使得液晶分子大致地往所设计的方向倾倒而后加热或照光固化配向层表面的液晶而形成预倾角。但实际在亮态驱动下，由于电极狭缝上方之电场垂直方向的分量较小，液晶分子在此并无法做最有效的倾倒，因此电极狭缝区的亮度会较电极区稍暗。
另外，面板的亮度或穿透度与画素电极4狭缝之宽度尺寸强烈相关，所以当制程产生局部狭缝宽度变异时，画面会有局部亮度不均匀的现象产生网点(Mura)。
发明内容
本发明所要解决的技术问题是提供一种改善液晶显示装置的亮度、视角特性和网点问题的阵列基板、液晶显示装置及阵列基板制作方法。
本发明的目的是通过以下技术方案来实现的：
一种阵列基板，包括多个薄膜晶体管、与所述薄膜晶体管的漏极连接的第一画素电极，所述阵列基板还包括设在第一画素电极底层的相互绝缘的第二画素电极。
优选的，所述阵列基板包括共通线，所述第二画素电极位于所述第一画素电极和共通线之间，所述第一画素电极、第二画素电极、共通线之间相互绝缘。此为一种包括共通线的阵列基板的实施例。
优选的，所述第二画素电极在所述第一画素电极和所述共通线的叠交区域设有缺口，这样第一画素电极和共通线之间只有绝缘材质，没有金属材质的阻隔，两者之间形成的存储电容比较大，以保障在两个扫描周期的间隔内，存储电容的电量足够维持液晶偏转。
优选的，所述阵列基板设有多个向内凹陷的接触窗口，所述第一画素电极延伸入所述接触窗口内跟所述薄膜晶体管的漏极电气连接。此为一种第一画素电极跟薄膜晶体管的漏极连接的具体实施方式。
一种液晶显示装置，包括上述的一种阵列基板。
一种阵列基板的制造方法，包括以下步骤：
A：在玻璃基板上形成第一钝化层；
B：在所述阵列基板的第一钝化层上面依次形成第二画素电极、第二钝化层、第一画素电极。
优选的，在所述步骤A之前，先在玻璃基板上形成共通线。此为一种包括共通线的阵列基板的实施例。
优选的，所述步骤B中，形成所述第二画素电极的时候，在所述第一画素电极和共通线的叠交区域形成缺口，这样第一画素电极和共通线之间只有绝缘材质，没有金属材质的阻隔，两者之间形成的存储电容比较大，以保障在两个扫描周期的间隔内，存储电容的电量足够维持液晶偏转。
优选的，所述步骤B中，形成所述第二钝化层的时候，在所述第一画素电极和所述薄膜晶体管的漏极叠交区域留有缺口，在形成第一画素电极的时候同步形成接触窗口。此为一种第一画素电极跟薄膜晶体管的漏极连接的具体实施方式，不需要额外增加工序，有利于提升工作效率，降低成本。
本发明采用在第一画素电极和共通线之间加设第二画素电极，所述第二画素电极为浮接(floating)电极，不与其他部分产生电气连接。假设第一画素电极跟彩色滤光板(CF)的公共电极之间的电压差为V1，由于第二画素电极电容分压的缘故会与公共电极之间存在有V2的电位差，因此会存在有V1≠V2之关系，所以其电力线之分布仍会使得液晶分子大致地往所设计的方向倾倒。而在实际的阵列基板驱动时，由于V1和V2的差距不大，因此施加一适当大之电压可使第一与第一画素电极均达到亮度饱和点，两画素电极所对应的亮度差异很小，因此可以得到较传统方式为高的穿透率；而在驱动中间灰阶时，第二画素电极与第一画素电极上方因为有不同的电位(V1、V2)对应不同的液晶倾倒程度，此对视角色偏也具有改善的功效。另外，本发明中液晶倾倒主要取决于第一画素电极和第二画素电极之间的压差，降低了电极狭缝的尺寸差异的影响，因此也就改善了网点(mura)问题。综上所述，本发明可以增加画素的穿透率、改善面板的视角色偏特性，并减轻因为电极线宽局部变异所形成的亮度不均(mura)现象。
附图说明
图1是现有的一种PSVA模式的画素结构示意图；
图2是本发明画素结构的剖面示意图；
图3是本发明画素结构的示意图；
图4是本发明画素结构的局部放大示意图；
图5是图4沿A-A’方向的剖面示意图；
图6是本发明画素结构共通线区域的局部放大示意图；
图7是图6沿B-B’方向的剖面示意图；
图8是本发明的原理示意图；
图9是本发明的压差折线图；
图10是本发明的亮度曲线图；
其中：1、资料线；2、扫描线；3、薄膜晶体管(TFT)；31、第一金属层；32、绝缘层；33、有效层；34、欧姆接触层；35、第二金属层；36、第一钝化层；37、第二钝化层；4、画素电极；41、共通线；42、接触窗口；43、第一画素电极；44、第二画素电极；45、缺口。
具体实施方式
下面结合附图和较佳的实施例对本发明作进一步说明。
如图1～7所示，一种液晶显示装置，包括一种阵列基板，该阵列基板包括多个薄膜晶体管，以及分别与所述薄膜晶体管(薄膜晶体管(TFT)3)的闸极、源极、漏极连接的扫描线2、资料线1、画素结构。
薄膜晶体管(TFT)3和画素结构如图2所示，图左侧为薄膜晶体管(TFT)3，右侧为画素结构，两者都位于同一玻璃基板上。薄膜晶体管(TFT)3从玻璃基板算起，上面依次为第一金属层31、绝缘层32、有效层33、欧姆接触层34、第二金属层35、第一钝化层36和第二钝化层37，第二金属层35靠近画素结构的一侧为薄膜晶体管(TFT)3的漏极，另外一侧为跟资料线1连接的源极。画素结构从玻璃基板算起，上面依次包括共通线41、绝缘层32、第一钝化层36、第二画素电极44、第二钝化层37和第一画素电极43。第一画素电极43穿透通第一钝化层36和第二钝化层37跟薄膜晶体管(TFT)3的漏极连接，形成所述接触窗口42。所述第二画素电极44在所述第一画素电极43和所述共通线41的叠交区域设有缺口45，以增大第一画素电极43和共通线41之间的储存电容(Cst2)。
上述阵列基板可采用目前常用的光罩制程制作，即在玻璃基板上采用沉积、曝光、显影、蚀刻等工序依次形成上述结构，具体步骤包括：
1.在玻璃基板上采用沉积、曝光、显影、蚀刻工序制成第一金属层31和共通线41；
2.在第一金属层31上沉积形成绝缘层32(Isolator)；
3.在绝缘层32上采用沉积、曝光、显影、蚀刻依次制成有效层33(activelayer)与欧姆接触层34(ohmic contact layer)；
4.在绝缘层32和欧姆接触层34上采用沉积、曝光、显影、蚀刻制成第二金属层35(此步骤同时需蚀刻欧姆接触层34)；
5.在整个阵列基板表面沉积形成第一钝化层36；
6.在第一钝化层36上采用沉积、曝光、显影、蚀刻制成第一透明导电层，即第二画素电极44，并在第一画素电极43和共通线41的叠交区域设缺口45。
7.在整个阵列基板表面沉积形成第二钝化层37；
8.在需要连接第二金属层35和第一画素电极43的位置采用沉积、曝光、显影、蚀刻制成接触窗口42(VIA)；
9.在第二钝化层37上采用沉积、曝光、显影、蚀刻制成第二透明导电层；
图8为上面所述画素结构的等效电路图，相较于传统电路结构由于此设计具有额外的透明导电层作为第二画素电极44因此会与之第一画素电极43之间形成CA电容且会与共通线41(Com Line)间会形成第一储存电容(Cst1)。
上述设计在PSVA液晶显示装置加电压过程中，第一画素电极43若与彩色滤光板(CF)上的公共电极间存在有V1之电位差，两者之间的电容为CLC2；而第二画素电极44为共通线41与第一画素电极43间的浮接(floating)电极，其跟公共电极间的电容为CLC1，由于电容分压的缘故会与公共电极间存在有V2之电位差，因此会存在有V1≠V2之关系，所以其电力线之分布仍会使得液晶分子大致地往所设计的方向倾倒，此时加热或照光固化配向层表面的液晶会形成预倾角。而在实际面板驱动时，若由资料线1输入一适当电压，其与公共电极间具有Vin之电位差，由于第二画素电极44之电位为第一画素电极43之分压的关系，两画素电极与公共电极间的电位差(Velectrode)与Vin的关系如下图9所示，所以Vin对应两画素电极区域的亮度如下图10所示，故施加一适当大之电压可使第一与第一画素电极均达到亮度饱和点，两画素电极所对应的亮度差异很小，因此可以得到较传统方式为高的穿透率；此外在驱动中间灰阶时，第一与第一画素电极上方因为不同的电位所以会对应不同的液晶倾倒程度，此对视角色偏也具有改善的功效。
以上内容是结合具体的优选实施方式对本发明所作的进一步详细说明，不能认定本发明的具体实施只局限于这些说明。对于本发明所属技术领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本发明的保护范围。

Claims (9)

1.一种阵列基板，包括多个薄膜晶体管、与所述薄膜晶体管的漏极连接的第一画素电极，其特征在于，所述阵列基板还包括设在第一画素电极底层的相互绝缘的第二画素电极。
2.权利要求1所述的一种阵列基板，其特征在于，所述阵列基板包括共通线，所述第二画素电极位于所述第一画素电极和共通线之间，所述第一画素电极、第二画素电极、共通线之间相互绝缘。
3.如权利要求1所述的一种阵列基板，其特征在于，所述第二画素电极在所述第一画素电极和所述共通线的叠交区域设有缺口。
4.如权利要求1所述的一种阵列基板，其特征在于，所述阵列基板设有多个向内凹陷的接触窗口，所述第一画素电极延伸入所述接触窗口内跟所述薄膜晶体管的漏极电气连接。
5.一种液晶显示装置，包括如权利要求1～4任一所述的一种阵列基板。
6.一种阵列基板的制造方法，包括以下步骤：
A：在玻璃基板上形成第一钝化层；
B：在所述阵列基板的第一钝化层上面依次形成第二画素电极、第二钝化层、第一画素电极。
7.如权利要求6所述的一种阵列基板的制造方法，其特征在于，在所述步骤A之前，先在玻璃基板上形成共通线。
8.如权利要求7所述的一种阵列基板的制造方法，其特征在于，所述步骤B中，形成所述第二画素电极的时候，在所述第一画素电极和共通线的叠交区域形成缺口。
9.如权利要求7所述的一种阵列基板的制造方法，其特征在于，所述步骤B中，形成所述第二钝化层的时候，在所述第一画素电极和所述薄膜晶体管的漏极叠交区域留有缺口，在形成第一画素电极的时候同步形成接触窗口。
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