CN102543893B - Preparation method of semiconductor device - Google Patents

Preparation method of semiconductor device Download PDF

Info

Publication number
CN102543893B
CN102543893B CN201010625100.5A CN201010625100A CN102543893B CN 102543893 B CN102543893 B CN 102543893B CN 201010625100 A CN201010625100 A CN 201010625100A CN 102543893 B CN102543893 B CN 102543893B
Authority
CN
China
Prior art keywords
solder bump
stove
carboxylic acid
acid gas
temperature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201010625100.5A
Other languages
Chinese (zh)
Other versions
CN102543893A (en
Inventor
泽田佳奈子
青木秀夫
小牟田直幸
小木曾浩二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Japanese Businessman Panjaya Co ltd
Kioxia Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to CN201010625100.5A priority Critical patent/CN102543893B/en
Publication of CN102543893A publication Critical patent/CN102543893A/en
Application granted granted Critical
Publication of CN102543893B publication Critical patent/CN102543893B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector

Abstract

The invention provides a preparation method of a semiconductor device. In one enforcement manner, a first base plate provided with a first welding material convex point and a second base plate provided with a second welding material convex point are overlapped and then arranged in a furnace by mutually and temporarily fixing the welding material convex points. After the furnace is exhausted to form a decompression atmosphere, carboxylic acid gas is introduced. After the carboxylic acid is introduced, the temperature in the furnace is raised; and by exhausting gas in the furnace, the decompression atmosphere is formed in a temperature range which is higher than a reduction temperature of the carboxylic acid gas to an oxidization film and is lower than a fusion temperature of the welding material convex points. The temperature in the furnace is raised to the temperature range which is higher than the fusion temperature of the welding material convex points, and the first welding material convex point and the second welding material convex point are jointed by fusing.

Description

The manufacture method of semiconductor device
The cross reference of related application
The application is based on the Japanese patent application 2009-146153 applied on June 19th, 2009 and require its priority, and its all content is incorporated by reference herein at this.
Technical field
The present invention relates to the manufacture method of semiconductor device.
Background technology
In recent years, in order to multi-pipe pin, the pitch adapting to semiconductor chip become more meticulous, the high speed of signal speed, as the mounting means that distribution/connecting length is short, use the semiconductor device applying flip-chip and connect.When flip-chip being connected the connection between connection or semiconductor chip and silicon insert (Silicon Interposer) be applied between semiconductor chip, solder bump is formed respectively on the electronic pads of upper and lower chip (semiconductor chip, silicon insert), stacked to carry out after the mode contraposition making these solder bumps relative, afterwards, heat, fusion welding salient point and connecting.
Usually, in order to remove the oxide-film on solder bump surface, after on surface scaling powder being coated on solder bump, make upper and lower chip contraposition and stacked.Next, to heat in reflow ovens, fusion welding salient point and make it connect, afterwards, clean scaling powder and removed.But, along with the microminiaturization of solder bump itself, the granular of formation chip, be difficult to clean scaling powder completely.Therefore, there is the problem of welding assisted agent residuals.
Therefore, to removed by the carboxylic acid such as formic acid solder bump surface oxide-film, heat on one side, fusion welding salient point and make it connect to be studied.In Japanese Unexamined Patent Publication 2001-244618 publication and Japanese Unexamined Patent Publication 2001-244283 publication, describe by the semiconductor chip with solder bump to be mounted in the reduced atmosphere being configured under the state on wiring substrate and comprising carboxylic acid gas and heat in such atmosphere, the scheme of fusion welding salient point.By heating in the reduced atmosphere comprising carboxylic acid gas, while the oxide-film removing solder bump surface, eliminate the space in the solder bump (solder layer) caused by gas of generation when being heated by solder.
When connecting each other the solder bump be arranged on upper and lower chip, make solder bump temporarily fixing after be configured in reflow ovens.In this case, due to the engaging-in solder bump of surface film oxide temporary transient immobile interface (contact interface) each other, so be difficult to realize the connectivity improved between solder bump to produce getting both of both spaces with the solder bump suppressed after melting is interior.
Summary of the invention
The present invention proposes in view of the above problems, and object is that providing a kind of can improve the connectivity between solder bump and suppress the interior manufacture method producing the semiconductor device in space of solder bump after melting.
In one embodiment, a kind of manufacture method of semiconductor device is provided, it is characterized in that, comprise following operation: on the first substrate with the first solder bump, the second substrate with the second solder bump is carried out stacked operation by temporarily fixing the first solder bump and the second solder bump; By temporarily secure the first solder bump and the second solder bump, the duplexer of both first substrate and second substrate is configured to operation in stove; Exhaust in the stove making to be configured with duplexer and form the operation of reduced atmosphere; The operation of carboxylic acid gas is imported in the stove of reduced atmosphere; Temperature in stove after carboxylic acid gas is imported rises, and, being more than or equal in the temperature province of carboxylic acid gas to the reduction temperature of the oxide-film of the first solder bump and the second solder bump and less than the melt temperature of the first solder bump and the second solder bump, making exhaust in stove and form the operation of reduced atmosphere; And make the in-furnace temperature of reduced atmosphere rise to the temperature province of the melt temperature being more than or equal to the first solder bump and the second solder bump, and make the first solder bump and the second solder bump melting and the operation engaged.
In other embodiments, a kind of manufacture method of semiconductor device is provided, it is characterized in that, comprise following operation: on the first substrate with the first solder bump, the second substrate with the second solder bump is carried out stacked operation by temporarily fixing the first solder bump and the second solder bump; The duplexer temporarily securing both the first substrate of the first solder bump and the second solder bump and second substrate is configured to the operation in stove; Exhaust in the stove making to be configured with duplexer and form the operation of reduced atmosphere; And make the temperature in the stove of reduced atmosphere rise to the temperature province of the melt temperature being more than or equal to the first solder bump and the second solder bump, and make the first solder bump and the second solder bump melting and the operation engaged.To be more than or equal to less the first solder bump and the second solder bump melt temperature temperature province stove in import carboxylic acid gas, maintain 5 × 10 to make the pressure in stove 3~ 3 × 10 4the scope of Pa and carboxylic acid concentration are in the scope of 0.1 ~ 2.8 volume %.
Invention effect
According to the present invention, the connectivity between solder bump can be improved, and suppress to produce space in solder bump after melting.
Accompanying drawing explanation
Figure 1A to Fig. 1 C is the cutaway view of the manufacturing process of the semiconductor device illustrated according to the first execution mode.
Fig. 2 is the cutaway view of the state of amplifying the solder bump illustrated in the manufacturing process of semiconductor device shown in Figure 1.
Fig. 3 amplifies the cutaway view that the state that the solder bump in the manufacturing process of semiconductor device shown in Figure 1 is temporarily fixed is shown.
Fig. 4 is the figure of the pressure and temperature curve of the removing step of the oxide-film on the solder bump surface illustrated in the first embodiment and the melting operation of solder bump.
Fig. 5 is the figure of the variation that pressure and temperature curve shown in Figure 4 is shown.
Fig. 6 is the figure of another variation that pressure and temperature curve shown in Figure 4 is shown.
Fig. 7 is the figure of the pressure and temperature curve of the removing step of the oxide-film on the solder bump surface illustrated in this second embodiment and the melting operation of solder bump.
Fig. 8 is the figure of the variation that pressure and temperature curve shown in Figure 7 is shown.
Embodiment
(the first execution mode)
Figure 1A ~ 1C is the cutaway view of the manufacturing process of the semiconductor device illustrated according to the first execution mode.As shown in Figure 1A, prepare that there is the first substrate 2 of the first solder bump 1 and the second substrate 4 with the second solder bump 3.First and second substrates 2,4 are such as semiconductor chip (silicon (Si) chip etc.) or silicon (Si) insert.The combination of the first and second substrates 2,4 is such as the combination of the first semiconductor chip (2) and the second semiconductor chip (4), the combination of Si insert (2) and semiconductor chip (4), the combination etc. of semiconductor chip (2) and Si insert (4), is not particularly limited.
First and second solder bumps 1,3 are respectively by the rectangular regulation region being arranged in substrate 2,4.Solder bump 1,3 respectively as shown in Figure 2, the electronic pads 5,7 being arranged at substrate 2,4 face side is formed across barrier metal layer 6,8.As the constituent material of solder bump 1,3, such as, adopt leadless welding alloy or the Sn-Pb class solder alloys such as Sn-Ag class solder alloy, Sn-Cu class solder alloy, Sn-Ag-Cu class solder alloy, Sn-Bi class solder alloy, Sn-In class solder alloy.Solder bump 1,3 can be any one in substantially lead-free lead-free solder and kupper solder.
Solder bump 1,3 is such as formed by galvanoplastic, or adopts the small ball containing solder alloy and formed.Although after being just formed on electronic pads 5,7, the surface of solder bump 1,3 not existing oxide-film, is through certain hour, as shown in Figure 2, the surface of solder bump 1,3 is oxidized.Be formed in oxide-film 9 on solder bump 1,3 surface solder bump 1,3 each other melting and connect time, the resistance between solder bump 1,3 is increased, or becomes the reason that bad connection occurs between solder bump 1,3.Therefore, before heating, fusion welding salient point 1,3, need the oxide-film 9 removing solder bump 1,3 surface.
When carrying out flip-chip to first substrate 2 and second substrate 4 and being connected, first, contraposition is carried out to the first solder bump 1 and the second solder bump 3, and stacked second substrate 4 on the first substrate 2.Now, as shown in Figure 1B and Fig. 3, temporarily fix the first solder bump 1 and the second solder bump 3.As long as the temporarily fixing intensity with the degree that upper and lower base plate 2,4 does not depart from when proceeding to next operation (removing step of oxide-film 9).Solder bump 1,3 temporarily fixing in, be suitable for based on the ultrasonic wave under the room temperature of ultrasonic flip chip jointing machine (Flip Chip Bonder) and the applying of load, the applying etc. based on the temperature near the solder melt point of pulse heater (pulse heater) hot type flip-chip bond machine and load.
Due to the first solder bump 1 and the second solder bump 3 is fixedly temporarily implement, so oxide-film 9 becomes the state of the contact interface between engaging-in first solder bump 1 and the second solder bump 3 under the state that there is oxide-film 9 over their surface.But, because the first solder bump 1 and the second solder bump 3 are temporarily fixing states, so contact interface between the first solder bump 1 and the second solder bump 3 exists clearance G as shown in Figure 3.Utilize the clearance G of such contact interface, after the oxide-film 9 being removed the oxide-film 9 and engaging-in contact interface be present on the surface of solder bump 1,3 by carboxylic acid gas, heating, fusion welding salient point 1,3.
With reference to the pressure and temperature curve in heating furnace shown in Figure 4, the heating of removing step and the solder bump 1,3 being present in oxide-film 9 on solder bump 1,3 surface, melting operation are described.First, after being configured to by the duplexer temporarily securing both solder bump 1,3 first substrate 2 each other and second substrate 4 in heating furnace (reflow ovens), reduced atmosphere is formed by vacuumizing in heating furnace.Because the oxygen remained in heating furnace makes solder bump 1,3 be oxidized, so preferably, by heating furnace from atmospheric pressure state (1.01 × 10 5pa) 1 × 10 is vented to 3the decompression state of below Pa, particularly about 5Pa.Carboxylic acid gas is imported in the heating furnace of such reduced atmosphere.
Carboxylic acid gas be the oxide-film 9 be present on solder bump 1,3 surface is reduced remove gas.There is no particular limitation for the carboxylic acid used as the reducing agent of oxide-film 9, such as, can be the low-grade carboxylic acid of the aliphat monovalencies such as formic acid, acetic acid, acrylic acid, propionic acid, oxalic acid, butanedioic acid, malonic acid or divalence.Wherein, because the cost of self cost and gasification is low and excellent and preferably use formic acid to the reduction of oxide-film 9.In addition, although stressed the situation of use formic acid as the typical example of carboxylic acid below, the carboxylic acid as the reducing agent of oxide-film 9 has been not limited thereto.
Import the carboxylic acid gases such as formic acid in heating furnace after or roughly while importing carboxylic acid gas, make to heat up in heating furnace with the programming rate specified (such as 40 ~ 50 DEG C/min).When using formic acid as carboxylic acid gas, under finding the temperature more than 150 DEG C, there is reduction to oxide-film 9.That is, the reduction temperature T1 of formic acid to oxide-film 9 is about 150 DEG C, if reach more than this temperature, oxide-film 9 is reduced removal.In the temperature province of more than the reduction temperature T1 of such oxide-film 9, by making solder bump 1,3 such as expose a few minutes in formic acid gas, thus reduce and remove the oxide-film 9 be present on solder bump 1,3 surface.
Preferably, be the state forced down than air by the pressure setting imported after carboxylic acid gas in heating furnace.Although concrete furnace pressure also depends on the import volume of carboxylic acid gas, preference is as 8 × 10 4below Pa.But, under such state (only importing the state of carboxylic acid gas), during temperature more than the fusing point being warmed up to solder bump 1,3, invade the carboxylic acid gas in above-mentioned clearance G and the gas that produces when oxide-film 9 reduces may enter the inside of the solder bump 1,3 of melting and form space.
In the first embodiment, in the temperature province of the reduction temperature T1 more than of carboxylic acid gas to oxide-film 9, melt temperature (fusing point T2) less than solder bump 1,3, remove carboxylic acid gas by vacuumizing in heating furnace.That is, the vacuum pump action being connected to heating furnace is made to be formed decompression state to be exhausted the atmosphere in heating furnace.Like this, before the fusing point T2 reaching solder bump 1,3 (before making solder bump 1,3 melting), by carrying out vacuum exhaust to the atmosphere in heating furnace, the gas that can produce when the carboxylic acid gas of solder bump 1,3 contact interface each other removal intrusion clearance G and oxide-film 9 reduce.
And, solder bump 1,3 melting is made by after the gas that produces when removing the carboxylic acid gas that invades clearance G from solder bump 1,3 contact interface (clearance G) each other and oxide-film 9 reduces, the space caused by gas invading clearance G or generation can be suppressed, i.e. the space that produces, solder bump 1,3 inside after melting.In addition, even if removed carboxylic acid gas before the fusing point T2 reaching solder bump 1,3, owing to solder bump 1,3 being exposed in carboxylic acid gas in the stage before, therefore also can removing and be present in the oxide-film 9 on solder bump 1,3 surface and the oxide-film 9 of engaging-in contact interface.Therefore, in the melting operation of solder bump 1,3, the increase of the resistance of the bad connection between solder bump 1,3 and the solder bump after melting 1,3 can be suppressed.
For the vacuumizing of atmosphere gas exhaust in heating furnace is preferably implemented in more than the reduction temperature T1 of oxide-film 9, temperature province less than the fusing point T2 of solder bump 1,3.But also due to the programming rate of heating furnace, when making to vacuumize too early in heating furnace, the time be exposed in carboxylic acid gas by solder bump 1,3 may be inadequate.On the other hand, when in heating furnace, evening vacuumizes excessively, can not from contact interface Exhaust Gas fully.Preferably, the enforcement temperature vacuumized is more than the temperature (T2-10 [DEG C]) of low 10 DEG C of the fusing point T2 than solder bump 1,3 and than fusing point T2 in the temperature (T2-5 [DEG C]) of low 5 DEG C scope below.Further, being exposed to by solder bump 1,3 in the time insufficient situation in carboxylic acid gas, official hour can be kept at the temperature of more than the reduction temperature T1 of oxide-film 9, or the programming rate during this that slows down.
Preferably, implement vacuumizing in the temperature province of the fusing point T2 less than solder bump 1,3, to make the pressure in heating furnace identical with the pressure imported before carboxylic acid gas.Particularly, preferably, in more than the reduction temperature T1 of oxide-film 9, temperature province less than the fusing point T2 of solder bump 1,3, vacuumize in heating furnace, until the pressure in heating furnace is 1 × 10 3~ 1 × 10 4the decompression state of about Pa.Thus, the gas produced when the carboxylic acid gas of intrusive contact interfacial gap G and oxide-film 9 can be made to reduce diffuses to around.
At this, because the clearance G of solder bump 1,3 contact interface is each other narrow and small, so only import carboxylic acid gas can there is the situation of oxide-film 9 of engaging-in contact interface of can not reducing completely in heating furnace.Further, also consider the diameter according to solder bump 1,3 and temporarily fixing state, the gas invading clearance G or generation can not be removed fully.To this, preferably, as shown in Figure 5, in the temperature province of carboxylic acid gas to more than the reduction temperature T1 of oxide-film 9, repeatedly repeatedly implement to import in heating furnace carboxylic acid gas operation and to the operation vacuumized in heating furnace (deairing step of carboxylic acid gas).
Like this, by repeatedly implementing to import carboxylic acid gas to reduce the process of removing oxide-film 9 and the process be discharged to by the gas produced when the carboxylic acid gas after reduction-oxidation film 9 and reduction-oxidation film 9 outside heating furnace in heating furnace, the oxide-film 9 of engaging-in contact interface can be removed better.Further, the clearance G at intrusive contact interface or the gas of generation are discharged more reliably.Therefore, engage by making solder bump 1,3 melting afterwards, inhibit the increase of the resistance value of the bad connection between solder bump 1,3 and the solder bump after melting 1,3 more reliably, and the space of generation in solder bump 1,3 after melting can be suppressed.
When repeatedly repeatedly implement to import carboxylic acid gas operation and to the operation vacuumized in heating furnace, preferably, in the temperature province of carboxylic acid gas to more than the reduction temperature T1 of oxide-film 9 and less than the fusing point T2 of solder bump 1,3, the stipulated time is kept.Thus, before the fusing point T2 arriving solder bump 1,3, the reduction treatment of oxide-film 9 and the discharge process of gas can repeatedly be implemented.Although to importing the operation of carboxylic acid gas and there is no particular limitation by the number of occurrence of operation that vacuumizes in heating furnace, but consider and repeatedly implement the effect of these operations generation and the increase of activity time, in the scope of 3 ~ 5 times, preferably repeat gas import and vacuumize.
Afterwards, by by the temperature province of the temperature in heating furnace to more than the fusing point T2 of solder bump 1,3, solder bump 1,3 melting is made.Such as, when being made up of solder bump 1,3 lead-free solder, although the fusing point of lead-free solder is different due to the composition of solder alloy, at about 220 ~ 230 DEG C, so the temperature being heated to more than such temperature is to make solder bump 1,3 melting.When being made up of solder bump 1,3 kupper solder, be heated to the temperature of more than 183 DEG C of kupper solder fusing point to make solder bump 1,3 melting.
The solder bump 1,3 of melting is ground integrated as shown in Figure 1 C and form connecting portion 10.In the first embodiment, remove the oxide-film 9 of engaging-in solder bump 1,3 contact interface each other, and promote that the clearance G at intrusive contact interface or the gas of generation are dispersed towards periphery.Therefore, form good connecting portion (connecting portion that shape and conduction etc. are excellent) 10 by solder bump 1,3, and the generation in the space in connecting portion 10 can be suppressed.That is, can realize being connected between substrate 2,4 by connecting portion 10 that is electric and good mechanical performance.
Then, cool to easily from the temperature of fech connection structure in heating furnace, the temperature of such as about 100 DEG C, and in heating furnace, import the inert gases such as nitrogen to return to atmospheric pressure, afterwards, take out from heating furnace and connect first substrate 2 and second substrate 4 by the connecting portion 10 be made up of solder bump 1,3 and the structure that forms.Like this, although can implement after the temperature cooling to easy fech connection structure to atmospheric recovery in heating furnace, but such as shown in Figure 6, temperature in heating furnace, under the state of the temperature province of more than the fusing point T2 of solder bump 1,3, does not import the inert gases such as nitrogen off and on until it is also effective for recovering atmospheric pressure in heating furnace.
Like this, by making the pressure in heating furnace not return to atmospheric pressure off and on during solder bump 1,3 melting, the fine gas bubbles remained in the solder bump 1,3 (connecting portion 10 of molten condition) of melting can be crushed.That is, although by removing vacuumizing in heating furnace in the temperature province of the fusing point T2 less than solder bump 1,3, the situation that microscopic spaces remains near interface can be there is in the large space caused by the gas of the contact interface of solder bump 1,3.Such microscopic spaces can by during solder bump 1,3 melting from around apply pressure and crush, thus obtain more intact connecting portion 10.
The structure connector of both second substrates 4 (first substrate 2 with) taken out from heating furnace is the same with general semiconductor device is sent to assembling procedure.Assembling procedure is selected according to semiconductor device, and there is no particular limitation.If describe one of them example, that is, first, in the gap between first substrate 2 and second substrate 4, fill thermosetting underfill resin (underfill resin), and process is cured to it and makes it harden.Further, after the connector of both first substrate 2 and second substrate 4 such as being carried on the 3rd substrate be made up of wiring substrate, connected between connector and the 3rd substrate by terminal conjunction method etc.After resin molded such structure, configuration outer conductor ball (ア ウ タ mono-リ mono-De ボ mono-Le) and form the external connection terminals of semiconductor device (semiconductor package part).
(the second execution mode)
In the manufacturing process of the semiconductor device according to the second execution mode, with the first execution mode (with reference to Figure 1A ~ 1C, Fig. 2, Fig. 3) in the same manner, make the first solder bump 1 and the second solder bump 3 contraposition, and stacked second substrate 4 on the first substrate 2.First solder bump 1 and the second solder bump 3 are temporarily fixed.The method for temporary fixing of the concrete example of substrate 2,4, the constituent material of solder bump 1,3, solder bump 1,3 etc. are identical with the first execution mode.
Next, identically with the first execution mode, after being configured in heating furnace (reflow ovens) by the duplexer temporarily securing both solder bump 1,3 first substrate 2 each other and second substrate 4, form reduced atmosphere by vacuumizing in heating furnace.Because the oxygen remained in heating furnace makes solder bump 1,3 be oxidized, so preferably, by heating furnace from atmospheric pressure state (1.01 × 10 5pa) 1 × 10 is vented to 3the decompression state of below Pa, particularly about 5Pa.In the heating furnace of such reduced atmosphere, import carboxylic acid gas, and make the temperature that is warmed up in heating furnace more than the melt temperature (fusing point T) of solder bump 1,3.As the reducing agent of oxide-film 9, the carboxylic acid gas identical with the first execution mode can be used, especially, consider the aspect of cost and reduction, preferably use formic acid gas.
Import carboxylic acid gas and make the pressure in heating furnace (atmosphere pressure) maintain 5 × 10 3~ 3 × 10 4in the scope of Pa.That is, suitable decompression state will be maintained in heating furnace, and import carboxylic acid gas in heating furnace.Particularly, after vacuumizing to remove the oxygen in heating furnace, continue to vacuumize (exhaust), on one side the carboxylic acid gas of debita spissitudo without interruption and flow.Thereby, it is possible to implement the melting operation of solder bump 1,3 under making the concentration of the carboxylic acid gas in heating furnace maintain the reduced atmosphere of suitable state.
When in the melting operation at solder bump 1,3, during the excessive concentration of the carboxylic acid gas in heating furnace, in the solder bump 1,3 that unnecessary carboxylic acid gas enters melting, form space.The generation in the space caused to suppress such carboxylic acid gas, makes pressure in the heating furnace in the melting operation of solder bump 1,33 × 10 in this second embodiment 4below Pa.When the pressure in heating furnace is more than 3 × 10 4during Pa, the gas flow entered in the solder bump 1,3 of melting increases, in solder bump 1,3, easily produce space.
Under the concentration of the carboxylic acid gas under such reduced atmosphere, the oxide-film 9 on solder bump 1,3 surface is reduced and removes.That is, even when the carboxylic acid gas concentration in heating furnace is lower, when connecting in solder bump 1,3 melting be arranged on upper and lower base plate 2,4, also can reduces and remove the oxide-film 9 be present on solder bump 1,3 surface.But, when the pressure in heating furnace is less than 5 × 10 3during Pa, because the concentration of carboxylic acid gas is too low, remove oxide-film 9 so can not reduce fully.Therefore, in the melting operation of solder bump 1,3, make pressure in heating furnace 5 × 10 3more than Pa.
Under above-mentioned reduced atmosphere, implement the importing operation of carboxylic acid gas, with make carboxylic acid concentration by volume ratio be the scope of 0.1 ~ 2.8%.When this carboxylic acid concentration is such as scaled the molar concentration of formic acid, be 4.1 × 10 -4~ 3.1 × 10 -2the scope of mol/L.When the concentration of carboxylic acid gas is more than 2.8 volume %, the gas concentration in heating furnace increases, in solder bump 1,3, easily produce space.On the other hand, when the concentration of carboxylic acid gas is less than 0.1 volume %, the reduction of carboxylic acid gas to oxide-film 9 can not be obtained fully, the increase of bad connection between solder bump 1,3 and resistance value can be caused.
Preferably, the pressure in the heating furnace in the melting operation of solder bump 1,3 is 1.3 ~ 2.7 × 10 4the scope of Pa.The concentration of carboxylic acid gas now in the scope of 0.1 ~ 2.8 volume %, further more preferably in the scope of 0.1 ~ 1 volume %.By the concentration of the carboxylic acid gas under above-mentioned reduced atmosphere is set in lower concentration, more reproducibility the space in the solder bump 1,3 of melting can be suppressed well.Therefore, preferably, the concentration of carboxylic acid gas is in the scope of 0.1 ~ 1 volume %.
By making to be set as the temperature province of the temperature in the heating furnace of furnace pressure as above (atmosphere pressure) and carboxylic acid concentration to more than the fusing point T of solder bump 1,3, make solder bump 1,3 melting.When being made up of solder bump 1,3 lead-free solder, although the fusing point of lead-free solder is different due to the composition of solder alloy, at about 220 ~ 230 DEG C, so the temperature being heated to more than this temperature is to make solder bump 1,3 melting.When being made up of solder bump 1,3 kupper solder, be heated to the temperature of more than 183 DEG C of kupper solder fusing point to make solder bump 1,3 melting.The solder bump 1,3 of melting is ground integrated as shown in Figure 1 C and form connecting portion 10.
When solder bump 1,3 melting, remove oxide-film 9 by the carboxylic acid gas reduction be present in heating furnace.Now, due in the scope of reduction that can obtain oxide-film 9, the atmosphere pressure of heating furnace and gas concentration are reduced to can reduce the value of the gas flow entered in the solder bump 1,3 of melting, so inhibit carboxylic acid gas enter in connecting portion 10 and form space.That is, oxide-film 9 can be removed and connect solder bump 1,3 well each other, and the few good connecting portion 10 of pore volume can be obtained.Therefore, can be connected between substrate 2,4 by connecting portion 10 that is electric and good mechanical performance.
Due to when using formic acid as carboxylic acid gas, there is reduction to oxide-film 9 under finding the temperature more than 150 DEG C, so certain hour can be kept in the temperature province more than such temperature, less than the fusing point T of solder bump 1,3.Thus, the removal effect of oxide-film 9 can be improved.But, because carboxylic acid gas at least exists when solder bump 1,3 melting, so as shown in Figure 8, only when solder bump 1,3 melting (temperature province of more than fusing point T), carboxylic acid gas can be imported in heating furnace.Carboxylic acid gas at least imports when solder bump 1,3 melting.Atmosphere pressure now, gas concentration are same as described above.
Cool to normal temperature by heating furnace, and in heating furnace, import the inert gases such as nitrogen to return to atmospheric pressure, afterwards, take out from heating furnace and connect first substrate 2 and second substrate 4 by the connecting portion 10 be made up of solder bump 1,3 and the structure that forms.The structure connector of both second substrates 4 (first substrate 2 with) taken out from heating furnace is the same with general semiconductor device is sent to assembling procedure.Assembling procedure is selected according to semiconductor device, and there is no particular limitation.The concrete example of assembling procedure with describe in the first embodiment identical.
Next, the concrete example of the manufacturing process of the semiconductor device according to the second execution mode is described.First, prepare the Si chip that two have the solder bump (diameter: 25 μm) be made up of lead-free solder, adopt pulse heater hot type flip-chip bond machine (heating-up temperature: 250 DEG C), the solder bump of these two Si chips is temporarily fixed.After being configured in heating furnace by this temporary transient fixed body, be evacuated down to below 5Pa by heating furnace.Atmosphere pressure in heating furnace afterwards and be fed to the concentration of the formic acid gas in heating furnace and flow adjusts as described below.
In embodiment 1, furnace pressure is being set as 1.3 × 10 4in the heating furnace of Pa (100Torr), make the formic acid gas of normal concentration with the traffic flow of 15L/ minute.Formic acid concn now in stove is 1.4 volume % (6.2 × 10 -3mol/L).In example 2, furnace pressure is being set as 1.3 × 10 4in the heating furnace of Pa (100Torr), make the formic acid gas of normal concentration with the traffic flow of 1L/ minute, and make nitrogen as diluent gas with the traffic flow of 14L/ minute.Formic acid concn now in stove is 0.1 volume % (4.1 × 10 -4mol/L).
As comparative example 1, furnace pressure is being set as 8 × 10 4in the heating furnace of Pa (600Torr), make the formic acid gas of normal concentration with the traffic flow of 15L/ minute.Formic acid concn now in stove is 8.2 volume % (3.7 × 10 -2mol/L).In comparative example 2, furnace pressure is being set as 8 × 10 4in the heating furnace of Pa (600Torr), make the formic acid gas of normal concentration with the traffic flow of 1L/ minute, and make nitrogen as diluent gas with the traffic flow of 14L/ minute.Formic acid concn now in stove is 0.6 volume % (2.5 × 10 -3mol/L).
Make the heating furnace in each example be warmed up to 265 DEG C, after keeping 3 minutes at such a temperature, cool to normal temperature.Like this, the melting and engaging each other of the solder bump of two Si chips is made respectively.By the chip join body of each example (connect two Si chips by the melting and solidification body of solder bump and form structure) each making five respectively, check in the solder bump in the same position of each chip (each 162/amount to 810) and have tight.About the space in solder bump, check respectively the presence or absence in large space of diameter more than 10 μm and diameter less than 10 μm areolate with or without.Their measurement result is shown in Table 1.
Table 1
As known from Table 1, the pressure in heating furnace is 5 × 10 3~ 3 × 10 4the scope of Pa, simultaneously formic acid concn are in the embodiment 1,2 of the scope of 0.1 ~ 2.8 volume %, and compared with comparative example 1,2, the salient point quantity that space occurs greatly reduces.Further, according to the result of comparative example 2, even if formic acid concn is in the scope of 0.1 ~ 2.8 volume %, when the pressure in heating furnace is more than 3 × 10 4during Pa, the effect in space can not be suppressed fully.
The result when condition changing above-described embodiment is shown in table 2.In table 2, sample 1 is the sample of fusion welding salient point under the same conditions as in practical example 2.Wherein, temperature conditions is 220 DEG C × 3 minutes (maintenance) → 265 DEG C × 3 minutes (maintenance).In sample 2, flowing formic acid gas (1L/ minute) and nitrogen (14L/ minute), to make to be set as 2.7 × 10 at furnace pressure 4the heating furnace of Pa (200Torr) is interior, formic acid concn is 0.2 volume %.In sample 3, flowing formic acid gas (5L/ minute) and nitrogen (10L/ minute), to make to be set as 2.7 × 10 at furnace pressure 4the heating furnace of Pa is interior, formic acid concn is 0.9 volume %.
In sample 4, flowing formic acid gas (5L/ minute) and nitrogen (10L/ minute), to make to be set as 1.3 × 10 at furnace pressure 4the heating furnace of Pa (100Torr) is interior, formic acid concn is 0.5 volume %.In sample 5, flowing formic acid gas (15L/ minute), to make to be set as 1.3 × 10 at furnace pressure 4the heating furnace of Pa is interior, formic acid concn is 1.4 volume %.In sample 6, flowing formic acid gas (15L/ minute), to make to be set as 2.7 × 10 at furnace pressure 4the heating furnace of Pa is interior, formic acid concn is 2.8 volume %.
Table 2
From the salient point quantity in the generation space shown in table 2, by atmosphere pressure during solder bump melting is set as 1.3 ~ 2.7 × 10 4the scope of Pa and formic acid concn are set in the scope of 0.1 ~ 1 volume %, improve the reproducibility of space inhibition.Further, the conduction test result that the chip join body of each sample is shown is merged in table 2.From the result of conduction test, in any one example, solder bump melting all well, joint, the oxide-film of bump surface does not hinder solder bump connection each other.
Although described some execution modes, these execution modes have been only present by way of example, are not used for limiting the scope of the invention.In fact, new method and system described here can be implemented in other mode various; Further, the form of method and system described here can carry out various omission, substitutes and change, and does not depart from spirit of the present invention.Claims and equivalents thereof are for containing the form in scope and spirit of the present invention of falling into or distortion.

Claims (17)

1. a manufacture method for semiconductor device, is characterized in that,
Comprise following operation:
On the first substrate with the first solder bump, the second substrate with the second solder bump is carried out stacked operation by temporary transient fixing described first solder bump and described second solder bump;
By temporarily secure described first solder bump and described second solder bump, the duplexer of described first substrate and described both second substrates is configured to operation in stove;
Exhaust in the described stove making to be configured with described duplexer and go into the operation of reduced atmosphere;
In the stove of described reduced atmosphere, import carboxylic acid gas, make the pressure increase in described stove to operation that is higher than described reduced atmosphere and the pressure forced down than air;
The temperature in the described stove of importing described carboxylic acid gas is made to increase, and, being more than or equal in the temperature province of described carboxylic acid gas to the reduction temperature of the oxide-film of described first solder bump and described second solder bump and less than the melt temperature of described first solder bump and described second solder bump, making again to be vented in described stove and form the operation of reduced atmosphere; And
Make the described in-furnace temperature being formed as reduced atmosphere in described deairing step again rise to the temperature province of the melt temperature being more than or equal to described first solder bump and described second solder bump, make described first solder bump and described second solder bump melting and the operation engaged.
2. the manufacture method of semiconductor device according to claim 1, is characterized in that,
Reduce the oxide-film removing and be formed on described first solder bump and described second solder bump surface and the oxide-film between engaging-in described temporarily fixing described first solder bump and described second solder bump by the described carboxylic acid gas imported in described stove, and by the exhaust in described stove, described carboxylic acid gas and the gas that produced by the reduction of described oxide-film are discharged to outside described stove.
3. the manufacture method of semiconductor device according to claim 1, is characterized in that,
Make the interior exhaust of described stove being configured with described duplexer until be less than or equal to 1 × 10 3the reduced atmosphere of Pa.
4. the manufacture method of semiconductor device according to claim 1, is characterized in that,
The pressure forced down than air will be maintained in described stove, in described stove, import described carboxylic acid gas.
5. the manufacture method of semiconductor device according to claim 1, is characterized in that,
Pressure in described stove is maintained and is less than or equal to 8 × 10 4the reduced atmosphere of Pa, imports described carboxylic acid gas in described stove.
6. the manufacture method of semiconductor device according to claim 1, is characterized in that,
Formic acid gas is imported in described stove as described carboxylic acid gas.
7. the manufacture method of semiconductor device according to claim 6, is characterized in that,
Be more than or equal to 150 DEG C, temperature province less than the melt temperature of described first solder bump and described second solder bump, be exhausted in the described stove importing described formic acid gas.
8. the manufacture method of semiconductor device according to claim 6, is characterized in that,
Be less than or equal to the temperature province of lower than described fusing point 5 DEG C in the temperature be more than or equal to than low 10 DEG C of the fusing point of described first solder bump and described second solder bump, be exhausted in the described stove importing described carboxylic acid gas.
9. the manufacture method of semiconductor device according to claim 1, is characterized in that,
In described stove, repeatedly repeatedly import described carboxylic acid gas and to exhaust in described stove after, make described first solder bump and described second solder bump melting and engage.
10. the manufacture method of semiconductor device according to claim 1, is characterized in that,
Under the state that temperature in the stove of described reduced atmosphere is the temperature province of the melt temperature being more than or equal to described first solder bump and described second solder bump, make pressure recover in described stove to atmospheric pressure.
The manufacture method of 11. semiconductor devices according to claim 10, is characterized in that,
In described stove, import inert gas and make pressure recover in described stove to atmospheric pressure.
The manufacture method of 12. semiconductor devices according to claim 1, is characterized in that,
Described first substrate possesses semiconductor chip or silicon insert, and described second substrate possesses semiconductor chip or silicon insert.
The manufacture method of 13. semiconductor devices according to claim 1, is characterized in that,
In the importing of described carboxylic acid gas, the pressure in described stove is made to maintain 5 × 10 3~ 3 × 10 4the scope of Pa and carboxylic acid concentration are in the scope of 0.1 ~ 2.8 volume %.
The manufacture method of 14. semiconductor devices according to claim 1, is characterized in that,
Formic acid gas is imported in described stove as described carboxylic acid gas.
The manufacture method of 15. semiconductor devices according to claim 14, is characterized in that,
Described formic acid gas is imported in described stove, to make formic acid concn 4.1 × 10 -4~ 3.1 × 10 -2the scope of mol/L.
The manufacture method of 16. semiconductor devices according to claim 1, is characterized in that,
Described carboxylic acid gas is imported in described stove, to make the pressure in described stove maintain 1.3 ~ 2.7 × 10 4the scope of Pa and described carboxylic acid concentration are in the scope of 0.1 ~ 1 volume %.
The manufacture method of 17. semiconductor devices according to claim 1, is characterized in that,
Make to be vented until be less than or equal to 1 × 10 in described stove 3the reduced atmosphere of Pa.
CN201010625100.5A 2010-12-17 2010-12-17 Preparation method of semiconductor device Active CN102543893B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201010625100.5A CN102543893B (en) 2010-12-17 2010-12-17 Preparation method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201010625100.5A CN102543893B (en) 2010-12-17 2010-12-17 Preparation method of semiconductor device

Publications (2)

Publication Number Publication Date
CN102543893A CN102543893A (en) 2012-07-04
CN102543893B true CN102543893B (en) 2014-12-17

Family

ID=46350430

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201010625100.5A Active CN102543893B (en) 2010-12-17 2010-12-17 Preparation method of semiconductor device

Country Status (1)

Country Link
CN (1) CN102543893B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3547809A4 (en) * 2016-11-22 2020-07-08 Senju Metal Industry Co., Ltd Soldering method

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105458433B (en) * 2016-01-20 2017-08-29 福建中科晶创光电科技有限公司 A kind of packaging system and method for packing of the welding of miniature solid state laser multistage temperature
CN109877411A (en) * 2019-04-10 2019-06-14 中国电子科技集团公司第十三研究所 The microcircuit welding assembly method of flux-free
CN113036573B (en) * 2021-02-25 2023-04-18 福建富鑫达电子有限公司 Method and device for crimping wire connector

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5992729A (en) * 1996-10-02 1999-11-30 Mcnc Tacking processes and systems for soldering
US6344407B1 (en) * 1999-12-20 2002-02-05 Fujitsu Limited Method of manufacturing solder bumps and solder joints using formic acid

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6858941B2 (en) * 2000-12-07 2005-02-22 International Business Machines Corporation Multi-chip stack and method of fabrication utilizing self-aligning electrical contact array

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5992729A (en) * 1996-10-02 1999-11-30 Mcnc Tacking processes and systems for soldering
US6344407B1 (en) * 1999-12-20 2002-02-05 Fujitsu Limited Method of manufacturing solder bumps and solder joints using formic acid

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3547809A4 (en) * 2016-11-22 2020-07-08 Senju Metal Industry Co., Ltd Soldering method

Also Published As

Publication number Publication date
CN102543893A (en) 2012-07-04

Similar Documents

Publication Publication Date Title
JP4901933B2 (en) Manufacturing method of semiconductor device
US8191758B2 (en) Method for manufacturing semiconductor device
US9468136B2 (en) Low void solder joint for multiple reflow applications
KR102121176B1 (en) Method for producing semiconductor package
JP2014199852A (en) Bonding method, and method of manufacturing semiconductor module
US8616433B2 (en) Forming low stress joints using thermal compress bonding
JP2007287712A (en) Semiconductor device, packaging structure thereof, and manufacturing method of semiconductor device and packaging structure
CN102543893B (en) Preparation method of semiconductor device
JP5035134B2 (en) Electronic component mounting apparatus and manufacturing method thereof
JPWO2019054509A1 (en) Mounting structure of semiconductor element and combination of semiconductor element and substrate
JP2002190497A (en) Sealing resin for flip-chip mounting
CN102593012B (en) Manufacturing method of semiconductor device
JP4577130B2 (en) Manufacturing method of semiconductor device
CN103050465A (en) Wafer-thinning single-chip encapsulation piece with copper pillars and manufacturing technology thereof
US7727805B2 (en) Reducing stress in a flip chip assembly
KR102181706B1 (en) Method for producing semiconductor chip
US20160005710A1 (en) Methods of attaching electronic components
TWI440110B (en) Method of manufacturing semiconductor device
JP2012129482A (en) Method for manufacturing semiconductor device
WO2022195757A1 (en) Semiconductor device and method for producing semiconductor device
KR101214683B1 (en) Method for manufacturing semiconductor device
JP5055625B2 (en) Lead-free vacuum soldering method for wide gap semiconductor chips
KR101192925B1 (en) Method of manufacturing semiconductor device
CN117457532A (en) Airborne microelectronic device eutectic integration and multi-gradient phase diagram analysis and calculation method thereof
JP6186884B2 (en) Electrode, electronic component, electronic apparatus, and electrode joining method

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20170801

Address after: Tokyo, Japan

Patentee after: TOSHIBA MEMORY Corp.

Address before: Tokyo, Japan

Patentee before: Toshiba Corp.

CP01 Change in the name or title of a patent holder
CP01 Change in the name or title of a patent holder

Address after: Tokyo, Japan

Patentee after: TOSHIBA MEMORY Corp.

Address before: Tokyo, Japan

Patentee before: Japanese businessman Panjaya Co.,Ltd.

Address after: Tokyo, Japan

Patentee after: Kaixia Co.,Ltd.

Address before: Tokyo, Japan

Patentee before: TOSHIBA MEMORY Corp.

TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20211231

Address after: Tokyo, Japan

Patentee after: Japanese businessman Panjaya Co.,Ltd.

Address before: Tokyo

Patentee before: TOSHIBA MEMORY Corp.