JP4577130B2 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- JP4577130B2 JP4577130B2 JP2005206398A JP2005206398A JP4577130B2 JP 4577130 B2 JP4577130 B2 JP 4577130B2 JP 2005206398 A JP2005206398 A JP 2005206398A JP 2005206398 A JP2005206398 A JP 2005206398A JP 4577130 B2 JP4577130 B2 JP 4577130B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
- H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/26175—Flow barriers
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- H—ELECTRICITY
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81009—Pre-treatment of the bump connector or the bonding area
- H01L2224/8101—Cleaning the bump connector, e.g. oxide removal step, desmearing
- H01L2224/81013—Plasma cleaning
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Abstract
Description
本発明は、半導体チップがフリップチップ実装されてなる半導体装置の製造方法に関するものである。 The present invention relates to a method of manufacturing a semiconductor device in which a semiconductor chip is formed by flip chip mounting.
半導体装置の中には、その実装の省スペース化を図るべく、半導体チップの下面に設けられた複数の入出力端子の各々が、配線基板の上面に設けられた複数のパッド端子の各々に接合されてなる、いわゆるフリップチップ実装構造のものがある。このようなフリップチップ実装の半導体装置は、半導体チップ側または配線基板側の少なくとも一方に半田バンプを形成しておき、その半田バンプを加熱溶融して半導体チップと配線基板とを接合することで、製造されるのが一般的である。
ただし、近年では環境保護の観点から無鉛半田が広く用いられつつあるが、例えば錫（Ｓｎ）−銀（Ａｇ）等の無鉛半田では、半田バンプの表面に強固な酸化膜が形成され、これにより接合不良や導通不良等が発生してしまい、結果としてフリップチップ実装の信頼性が低下してしまうおそれがある。
このことから、フリップチップ実装の半導体装置を製造するにあたっては、例えば、半田バンプにフラックスを付着させておき、その半田バンプの加熱溶融時にフラックスの還元作用を利用して酸化膜を除去することや（例えば、特許文献１参照）、不活性ガス雰囲気中で発生させたプラズマを用いて金属接合部表面を洗浄して酸化を防ぎ、その処理雰囲気中で加熱により接合を行うことが提案されている（例えば、特許文献２参照）。また、その他にも、半田バンプではなく、金（Ａｕ）バンプを用い、その金バンプをプラズマ溶融して、フリップチップ実装することも提案されている。
In some semiconductor devices, each of a plurality of input / output terminals provided on the lower surface of the semiconductor chip is bonded to each of a plurality of pad terminals provided on the upper surface of the wiring board in order to save the mounting space. There is a so-called flip chip mounting structure. In such a flip-chip mounted semiconductor device, solder bumps are formed on at least one of the semiconductor chip side or the wiring board side, the solder bumps are heated and melted, and the semiconductor chip and the wiring board are joined, It is common to be manufactured.
However, in recent years, lead-free solder has been widely used from the viewpoint of environmental protection. However, in lead-free solder such as tin (Sn) -silver (Ag), a strong oxide film is formed on the surface of the solder bump. There is a possibility that bonding failure, conduction failure, or the like occurs, and as a result, the reliability of flip chip mounting is lowered.
For this reason, when manufacturing a flip-chip mounted semiconductor device, for example, a flux is attached to a solder bump, and the oxide film is removed by utilizing the reducing action of the flux when the solder bump is heated and melted. (For example, refer to Patent Document 1), it has been proposed that the surface of a metal joint is cleaned by using plasma generated in an inert gas atmosphere to prevent oxidation, and bonding is performed by heating in the processing atmosphere. (For example, refer to Patent Document 2). In addition, it has also been proposed to use gold (Au) bumps instead of solder bumps, and to melt the gold bumps by plasma to perform flip chip mounting.
しかしながら、上述した従来技術によるフリップチップ実装では、以下に述べるような難点がある。
例えば、上記特許文献１に開示された手法によるフリップチップ実装では、フラックスを用いているため、接合部分のアンダーフィルによる封止時に、そのフラックスの洗浄残渣等によりボイドが発生する可能性がある。このようなボイドは、ショート発生等を招き、半導体装置の信頼性低下に繋がるおそれがある。
また、上記特許文献２に開示された手法によるフリップチップ実装では、不活性ガス雰囲気中でのプラズマ処理後にその処理雰囲気中で半導体チップを基板上に接合する必要があり、そのために用いる製造装置の構成が複雑化してしまう。この点については、プラズマを用いた洗浄後に、半導体チップと基板との接合を大気中で行うことも考えられる。ところが、不活性ガス雰囲気中でプラズマ処理を行うと、そのプラズマ照射によって半田バンプの表面粗さが荒れる傾向にある。したがって、表面粗さが荒れたまま大気中に曝したのでは、その表面粗さに起因して酸化膜が形成され易くなる可能性があり、結果として接合不良や導通不良等によるフリップチップ実装の信頼性低下を招くおそれがある。
また、上記特許文献３に開示された手法によるフリップチップ実装では、金バンプを用いるため、半田バンプの場合に比べて接続の柔軟性に劣り、例えばＤＲＡＭ（Dynamic Random Access Memory）のセル上への適用が困難である。
However, the above-described conventional flip chip mounting has the following problems.
For example, in the flip chip mounting by the method disclosed in Patent Document 1, since flux is used, voids may be generated due to the cleaning residue of the flux at the time of sealing the joint portion with underfill. Such voids may cause a short circuit and the like, leading to a decrease in reliability of the semiconductor device.
Further, in flip chip mounting by the technique disclosed in Patent Document 2, it is necessary to join a semiconductor chip on a substrate in a processing atmosphere after plasma processing in an inert gas atmosphere. The configuration becomes complicated. With respect to this point, it is also conceivable to perform bonding between the semiconductor chip and the substrate in the air after cleaning using plasma. However, when plasma treatment is performed in an inert gas atmosphere, the surface roughness of the solder bumps tends to become rough due to the plasma irradiation. Therefore, if the surface roughness is exposed to the atmosphere, the oxide film is likely to be formed due to the surface roughness, and as a result, the flip chip mounting due to poor bonding or poor conduction may occur. There is a risk of lowering reliability.
Further, in flip chip mounting by the technique disclosed in Patent Document 3, since gold bumps are used, connection flexibility is inferior to that of solder bumps. For example, DRAM (Dynamic Random Access Memory) cells are placed on cells. It is difficult to apply.
そこで、本発明は、フリップチップ実装の半導体装置であっても、そのフリップチップ実装による接続の信頼性を十分に確保でき、しかも製造装置構成の複雑化等を招くことがなく、さらには様々な製品用途への適用に対応可能な汎用性を得ることのできる、半導体装置の製造方法を提供することを目的とする。 Therefore, the present invention can sufficiently ensure the reliability of the connection by flip chip mounting even in a flip chip mounted semiconductor device, and does not incur the complexity of the manufacturing apparatus configuration. It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of obtaining versatility that can be applied to product applications.
本発明は、上記目的を達成するために案出された半導体装置の製造方法である。すなわち、半導体チップがフリップチップ実装されてなる半導体装置の製造方法であって、前記フリップチップ実装による接続端子間の少なくとも一方に形成された半田バンプに対してプラズマを用いた洗浄を行う洗浄工程と、前記洗浄工程による洗浄後の半田バンプを加熱溶融して前記接続端子間の接合を行う接合工程とを含み、前記洗浄工程では、前記プラズマを用いた洗浄を、不活性ガスと還元性ガスとの混合ガス雰囲気中で行うことを特徴とする。また、半田バンプを加熱して、該半田バンプの表面における酸化膜を一定量成長させる加熱工程を含み得る。 The present invention is a semiconductor device manufacturing method devised to achieve the above object. That is, a method of manufacturing a semiconductor device in which a semiconductor chip is flip-chip mounted, wherein a cleaning step is performed for cleaning a solder bump formed on at least one of the connection terminals by the flip chip mounting using plasma. And a bonding step of bonding the connecting terminals by heating and melting the solder bumps that have been cleaned in the cleaning step, and in the cleaning step, cleaning using the plasma is performed with an inert gas and a reducing gas. It is characterized by being performed in a mixed gas atmosphere. Moreover, the heating process which heats a solder bump and grows a fixed quantity of oxide films on the surface of the solder bump may be included.
上記手順の半導体装置の製造方法では、不活性ガスと還元性ガスとの混合ガス雰囲気中で、半田バンプに対してプラズマを用いた洗浄を行う。「不活性ガス」は、プラズマ発生を励起させるためのもので、代表的なものとして例えばアルゴン（Ａｒ）ガスが挙げられる。また、「還元性ガス」は、酸素と反応する特性を有したものであり、代表的なものとして例えば水素（Ｈ2）ガスが挙げられる。このような不活性ガスと還元性ガスとの混合ガス雰囲気中にて洗浄を行うと、半田バンプの表面では、プラズマによって酸化膜が除去されるとともに、還元性ガスの還元作用によっても酸化膜が除去される。しかも、プラズマのみの場合に比べると、還元性ガスの還元作用により半田バンプの表面粗さが平滑化するため、例えば洗浄後に半田バンプを大気中に曝した場合であっても酸化膜が形成され難くなる。
したがって、洗浄工程による洗浄後の半田バンプについて、接合工程にて加熱溶融を行えば、その半田バンプ表面の酸化膜に起因する接合不良や導通不良等の発生を抑制し得るようになる。また、大気中でも半田バンプ表面に酸化膜が形成され難いことから、接合工程を大気中にて行うことも可能となる。
In the semiconductor device manufacturing method according to the above procedure, the solder bumps are cleaned using plasma in a mixed gas atmosphere of an inert gas and a reducing gas. The “inert gas” is for exciting plasma generation, and a typical example is argon (Ar) gas. The “reducing gas” has a characteristic of reacting with oxygen, and a representative example thereof is hydrogen (H 2 ) gas. When cleaning is performed in a mixed gas atmosphere of such an inert gas and a reducing gas, the oxide film is removed by the plasma on the surface of the solder bump, and the oxide film is also formed by the reducing action of the reducing gas. Removed. In addition, the surface roughness of the solder bumps is smoothed by the reducing action of the reducing gas as compared with the case of plasma alone, so that an oxide film is formed even when, for example, the solder bumps are exposed to the air after cleaning. It becomes difficult.
Therefore, if the solder bumps cleaned by the cleaning process are heated and melted in the bonding process, it is possible to suppress the occurrence of defective bonding or poor conduction due to the oxide film on the surface of the solder bump. In addition, since it is difficult to form an oxide film on the solder bump surface even in the air, the bonding process can be performed in the air.
以上のように、本発明によれば、フリップチップ実装の場合であっても、フラックスを要することなく接続端子間の接合不良や導通不良等の発生を抑制し得ることでき、そのフリップチップ実装の信頼性を十分に確保することができる。しかも、大気中での接合も可能であることから、フリップチップ実装のために用いる製造装置の構成が複雑化するのを回避し得る。さらには、半田バンプを用いることで、例えばＤＲＡＭのセル上への適用が容易であるといったように、様々な製品用途への適用に対応可能な汎用性を得ることができる。 As described above, according to the present invention, even in the case of flip-chip mounting, it is possible to suppress the occurrence of bonding failure between the connection terminals or poor conduction without requiring flux, and the flip-chip mounting Reliability can be sufficiently secured. In addition, since bonding in the atmosphere is possible, it is possible to avoid complication of the configuration of the manufacturing apparatus used for flip chip mounting. Furthermore, by using solder bumps, it is possible to obtain versatility that can be applied to various product applications, such as easy application to DRAM cells.
以下、図面に基づき、本発明に係る半導体装置の製造方法について説明する。 Hereinafter, with reference to the accompanying drawings, a description will be given on a method of manufacturing a semiconductor device according to the present invention.
〔半導体装置についての説明〕
先ず、はじめに、本発明を用いて製造される半導体装置の構成について簡単に説明する。図１は、半導体装置の概略構成例を示す説明図である。
[Description of semiconductor device]
First, the configuration of a semiconductor device manufactured using the present invention will be briefly described. FIG. 1 is an explanatory diagram illustrating a schematic configuration example of a semiconductor device.
ここで説明する半導体装置は、半導体チップがフリップチップ実装されてなるものである。詳しくは、図１（ａ）に示すように、半導体チップ１の下面に設けられた複数の入出力端子１ａの各々が、配線基板２の上面に設けられた複数のパッド端子２ａの各々と、半田バンプ３を介して接合されてなる、いわゆるフリップチップ実装構造のものである。なお、半導体チップ１と配線基板２との間の接合部分は、アンダーフィル４によって封止されている。 The semiconductor device described here is formed by flip-chip mounting a semiconductor chip. Specifically, as shown in FIG. 1A, each of the plurality of input / output terminals 1a provided on the lower surface of the semiconductor chip 1 is connected to each of the plurality of pad terminals 2a provided on the upper surface of the wiring board 2. This is a so-called flip-chip mounting structure that is joined via solder bumps 3. Note that the joint between the semiconductor chip 1 and the wiring substrate 2 is sealed with an underfill 4.
また、半導体装置は、図１（ｂ）に示すように構成されたものであってもよい。すなわち、上側半導体チップ５の下面に設けられた複数の入出力端子５ａの各々が、下側半導体チップ６の上面に設けられた複数の入出力端子６ａの各々と、半田バンプ３を介して接合されてなるものであってもよい。このようなフリップチップ実装構造のものでは、下側半導体チップ６の下面が配線基板７上に固着され、その下側半導体チップ６または上側半導体チップ５の外部端子と配線基板７上の接続端子とがボンディングワイヤを介して電気的に接続されることになる。なお、このようなフリップチップ実装構造においても、上側半導体チップ５と下側半導体チップ６との間の接合部分は、アンダーフィル４によって封止されている。 Further, the semiconductor device may be configured as shown in FIG. That is, each of the plurality of input / output terminals 5 a provided on the lower surface of the upper semiconductor chip 5 is joined to each of the plurality of input / output terminals 6 a provided on the upper surface of the lower semiconductor chip 6 via the solder bumps 3. It may be made. In such a flip-chip mounting structure, the lower surface of the lower semiconductor chip 6 is fixed on the wiring board 7, and external terminals of the lower semiconductor chip 6 or the upper semiconductor chip 5 and connection terminals on the wiring board 7 are provided. Are electrically connected via a bonding wire. Even in such a flip chip mounting structure, the joint between the upper semiconductor chip 5 and the lower semiconductor chip 6 is sealed with the underfill 4.
つまり、半導体装置は、半導体チップ１，５，６がフリップチップ実装されてなる構造のものであればよい。 That is, the semiconductor device only needs to have a structure in which the semiconductor chips 1, 5, and 6 are flip-chip mounted.
〔半導体装置の製造装置についての説明〕
次に、以上のような半導体装置を製造する製造装置の構成について簡単に説明する。図２は、本発明に係る半導体装置の製造装置の概略構成例を示す説明図である。
[Description of Semiconductor Device Manufacturing Equipment]
Next, the configuration of a manufacturing apparatus for manufacturing the semiconductor device as described above will be briefly described. FIG. 2 is an explanatory diagram showing a schematic configuration example of a semiconductor device manufacturing apparatus according to the present invention.
図例のように、ここで説明する半導体装置の製造装置は、洗浄装置１０と、接合装置２０とを含んで構成されている。これらを含んでいれば、さらに他装置を備えていてもよい。 As illustrated, the semiconductor device manufacturing apparatus described here includes a cleaning device 10 and a bonding device 20. If these are included, another device may be further provided.
洗浄装置１０は、プラズマを用いた洗浄処理を行うもので、所定雰囲気を実現するチャンバ室１１と、そのチャンバ室１１内でプラズマを発生させるための電極１２とを備えており、チャンバ室１１内に被洗浄物をセットし得るように構成されている。
また、この洗浄装置１０では、チャンバ室１１内に、不活性ガス（希ガス）に加えて、還元性ガスを供給し得るようになっている。すなわち、プラズマを用いた洗浄処理を、不活性ガスと還元性ガスとの混合ガス雰囲気中で行い得るようになっている。
不活性ガスは、プラズマ発生を励起させるためのもので、代表的なものとして例えばアルゴン（Ａｒ）ガスが挙げられる。また、還元性ガスは、酸素と反応する特性を有したものであり、代表的なものとして例えば水素（Ｈ2）ガスが挙げられる。ただし、Ｈ2ガス以外にも、メタン（ＣＨ4）ガス、アンモニア（ＮＨ3）ガス、アセチレン（Ｃ2Ｈ2）ガス等を用いることも考えられる。
なお、プラズマを発生させるための機構の詳細については、公知技術を利用して実現すればよいため、ここではその説明を省略する。
The cleaning device 10 performs a cleaning process using plasma, and includes a
In the cleaning apparatus 10, a reducing gas can be supplied into the
The inert gas is for exciting plasma generation, and a typical example is argon (Ar) gas. Also, the reducing gas is one which has the property of reacting with oxygen, typical as for example, hydrogen (H 2) include gas. However, in addition to H 2 gas, methane (CH 4 ) gas, ammonia (NH 3 ) gas, acetylene (C 2 H 2 ) gas, or the like may be used.
Note that the details of the mechanism for generating plasma may be realized using a known technique, and thus the description thereof is omitted here.
一方、接合装置２０は、半導体チップ１，５，６のフリップチップ実装を行うべく、半田バンプ３に対する加熱溶融を行って、そのフリップチップ実装構造における接合部分を接合するものである。なお、この接合装置２０における機構の詳細についても、公知技術を利用して実現すればよいため、ここではその説明を省略する。 On the other hand, in order to perform flip chip mounting of the semiconductor chips 1, 5, and 6, the bonding apparatus 20 heats and melts the solder bumps 3 to bond the bonding portions in the flip chip mounting structure. The details of the mechanism in the joining apparatus 20 may be realized by using a known technique, and thus the description thereof is omitted here.
〔半導体装置の製造方法についての説明〕
次に、以上のような製造装置を用いて半導体装置を製造する場合の手順、すなわち半導体装置の製造方法について説明する。図３は、本発明に係る半導体装置の製造方法の一具体例を示す説明図である。図中では、図１（ｂ）に示した構成の半導体装置を製造する場合を例に挙げている。
[Description of Semiconductor Device Manufacturing Method]
Next, a procedure for manufacturing a semiconductor device using the manufacturing apparatus as described above, that is, a method for manufacturing a semiconductor device will be described. FIG. 3 is an explanatory view showing a specific example of a method for manufacturing a semiconductor device according to the present invention. In the drawing, the case where the semiconductor device having the configuration shown in FIG. 1B is manufactured is taken as an example.
半導体装置の製造にあたっては、上側半導体チップ５の基になるウエハ基板と、下側半導体チップ６の基になるウエハ基板とのそれぞれに対し、いわゆる前工程によるチップ形成を行った後、それぞれにおける入出力端子５ａ，６ａ上に半田バンプ３を形成する（ステップ１０１、以下ステップを「Ｓ」と略す）。半田バンプ３は、環境保護の観点からＳｎ−Ａｇ等の無鉛半田を用いることが考えられる。ただし、半田バンプ３の形成は、必ずしも上側半導体チップ５と下側半導体チップ６との両方に対して行う必要はなく、いずれか一方のみに対して行ってもよい。すなわち、互いに接合される入出力端子５ａ，６ａ同士の少なくとも一方の側に形成されていればよい。そして、半田バンプ３を形成したら、続いて、研磨による板厚調整（Ｓ１０２）およびダイシングによるチップ切断分離（Ｓ１０３）を行う。
In manufacturing the semiconductor device, after forming a chip by a so-called pre-process on each of the wafer substrate on which the upper semiconductor chip 5 is based and the wafer substrate on which the lower semiconductor chip 6 is based, Solder bumps 3 are formed on the output terminals 5a and 6a (
その後は、ダイシングにより得られた上側半導体チップ５と下側半導体チップ６とを互いに接合するボンディング、すなわち接合装置２０を用いた接合工程を行う（Ｓ１０５）。ただし、ここで説明する半導体装置の製造方法では、接合工程に先立って、加熱工程および洗浄工程（Ｓ１０４）を行う点に大きな特徴がある。 After that, bonding for bonding the upper semiconductor chip 5 and the lower semiconductor chip 6 obtained by dicing to each other, that is, a bonding process using the bonding apparatus 20 is performed (S105). However, the semiconductor device manufacturing method described here has a great feature in that a heating step and a cleaning step (S104) are performed prior to the bonding step.
加熱工程は、半田バンプ３を形成後から洗浄工程の実施前までのいずれかの時点で行えばよい。加熱工程では、洗浄工程での洗浄対象となる半田バンプ３に対する加熱を行う。この加熱により、半田バンプ３の表面における酸化膜が成長することになる。ただし、加熱による酸化膜の成長には限度があり、ある一定量で収束する。したがって、加熱温度を半田バンプ３の表面における酸化膜を成長させるのに必要十分な温度とし、また加熱時間を酸化膜の成長量が収束するのに十分な時間とすれば、加熱を行うことによって、半田バンプ３の表面における酸化膜の厚さが一定となるようにコントロールし得るとともに、複数の半田バンプ３が存在する場合であっても、それぞれにおける酸化膜の厚さの均一化が図れるようになる。具体的には、例えば大気中にて２００℃で２時間の加熱を行うことが考えられる。なお、加熱は、加熱ヒータ等の公知技術を利用して行えばよい。 The heating process may be performed at any time after the solder bump 3 is formed and before the cleaning process is performed. In the heating process, the solder bumps 3 to be cleaned in the cleaning process are heated. By this heating, an oxide film on the surface of the solder bump 3 grows. However, there is a limit to the growth of the oxide film by heating, and it converges with a certain amount. Therefore, if the heating temperature is set to a temperature necessary and sufficient for growing the oxide film on the surface of the solder bump 3 and the heating time is set to a time sufficient for the growth amount of the oxide film to converge, heating is performed. The thickness of the oxide film on the surface of the solder bump 3 can be controlled to be constant, and even if there are a plurality of solder bumps 3, the thickness of the oxide film can be made uniform in each of them. become. Specifically, for example, heating in the atmosphere at 200 ° C. for 2 hours can be considered. Heating may be performed using a known technique such as a heater.
洗浄工程は、加熱工程の後から、接合工程の実施前までのいずれかの時点で行えばよい。ただし、接合工程の直前に行うことが最も望ましい。洗浄工程は、半田バンプ３の表面における酸化膜を除去するための行うものであるが、その洗浄工程から接合工程までの間に他工程を挟むと、その他工程の内容によっては、酸化膜が形成されるおそれがあるためである。すなわち、酸化膜を除去する上では、接合工程の直前に行うのが最も有効だからである。 The cleaning process may be performed at any time after the heating process and before the bonding process. However, it is most desirable to carry out immediately before the joining step. The cleaning process is performed to remove the oxide film on the surface of the solder bump 3. If another process is sandwiched between the cleaning process and the bonding process, an oxide film may be formed depending on the contents of the other process. It is because there is a risk of being. That is, it is most effective to remove the oxide film immediately before the bonding step.
洗浄工程では、洗浄対象となる半田バンプ３が形成されている半導体チップ５，６を、洗浄装置１０のチャンバ室１１内にセットし、その状態でプラズマを用いた洗浄処理を行う。このとき、チャンバ室１１内には、不活性ガスと還元性ガスとを供給し、そのチャンバ室１１内をこれらの混合ガス雰囲気とする。不活性ガスとしては、Ａｒガスを用いることが考えられる。また、還元性ガスとしては、Ｈ2ガスを用いることが考えられる。
In the cleaning process, the semiconductor chips 5 and 6 on which the solder bumps 3 to be cleaned are formed are set in the
ＡｒガスおよびＨ2ガスの混合ガス雰囲気中で、プラズマを用いた洗浄処理を行うと、Ａｒガスの存在によってプラズマ発生が励起される。そして、そのプラズマが半田バンプ３の表面と衝突する作用によって、その半田バンプ３の表面における酸化膜が除去されることになる。また、これと合わせて、Ｈ2ガスも存在しているので、そのＨ2ガスの還元作用によって、酸化膜中の酸素（Ｏ）がＨ2と反応し、水蒸気（Ｈ2Ｏ）となって抽出されることになる。つまり、Ｈ2ガスの還元作用によっても、半田バンプ３の表面における酸化膜が除去されることになる。 In a mixed gas atmosphere of Ar gas and H 2 gas, when a cleaning process using a plasma, the plasma generated by the presence of Ar gas is excited. The oxide film on the surface of the solder bump 3 is removed by the action of the plasma colliding with the surface of the solder bump 3. In addition, since H 2 gas is also present, oxygen (O) in the oxide film reacts with H 2 due to the reducing action of the H 2 gas to form water vapor (H 2 O). Will be extracted. That is, the oxide film on the surface of the solder bump 3 is also removed by the reducing action of the H 2 gas.
このようなＡｒガスとＨ2ガスとの混合ガス雰囲気中にて洗浄処理を行うと、半田バンプ３の表面では、プラズマの作用によって酸化膜が除去されるとともに、Ｈ2の還元作用によっても酸化膜が除去されるので、プラズマのみの場合に比べると、半田バンプ３の表面粗さが平滑化する。これは、プラズマが半田バンプ３の表面と衝突する作用によって酸化膜除去を行うと、その除去後の表面に凹凸が生じてしまい、これにより表面粗さが荒れる傾向にあるが、プラズマによる除去に合わせてＨ2の還元作用による除去を併用すると、その還元作用による除去が主に凸部分に働くことになり、これにより凹凸が均される傾向が強くなるからである。 When cleaning is performed in such a mixed gas atmosphere of Ar gas and H 2 gas, the oxide film is removed on the surface of the solder bump 3 by the action of plasma and also oxidized by the action of H 2 reduction. Since the film is removed, the surface roughness of the solder bump 3 is smoothed as compared with the case of only plasma. This is because when the oxide film is removed by the action of the plasma colliding with the surface of the solder bump 3, irregularities are generated on the surface after the removal, and the surface roughness tends to be roughened. In addition, if the removal by the reducing action of H 2 is used in combination, the removal by the reducing action mainly acts on the convex part, and thereby the tendency for the unevenness to be leveled becomes strong.
このときの混合ガス雰囲気中におけるＨ2ガスの濃度は、低過ぎても高過ぎてもいけない。その上限および下限は、実験等を通じて得られた経験則から、２％〜６０％が適用可能範囲であると考えられる。２％未満の場合のように、濃度が低過ぎると、還元作用による除去効果が十分に得られず、また６０％を超える場合のように、濃度が高過ぎると、凹凸の凹部分にまで還元作用が働いてしまい、却って表面の凹凸が顕著になってしまうからである。
最も好適なＨ2ガスの濃度は、２０％程度である。すなわち、Ａｒガス８０％、Ｈ2ガス２０％の混合ガス雰囲気中にて、プラズマを用いた洗浄処理を行うと、半田バンプ３の表面における酸化膜を適切に除去しつつ、その除去後においても平滑な表面粗さが得られることが、実験等を通じて得られた経験則から分かっている。
At this time, the concentration of H 2 gas in the mixed gas atmosphere should not be too low or too high. The upper limit and the lower limit are considered to be applicable ranges of 2% to 60% from empirical rules obtained through experiments and the like. If the concentration is too low as in the case of less than 2%, the removal effect due to the reducing action cannot be sufficiently obtained, and if the concentration is too high as in the case of exceeding 60%, it is reduced to the concave and convex portions. This is because the action works and the surface irregularities become conspicuous.
The most preferred concentration of H 2 gas is about 20%. That is, when a cleaning process using plasma is performed in a mixed gas atmosphere of Ar gas 80% and H 2 gas 20%, the oxide film on the surface of the solder bump 3 is appropriately removed and even after the removal. It is known from empirical rules obtained through experiments and the like that a smooth surface roughness can be obtained.
プラズマを用いた洗浄処理を行う際の処理時間についても、短過ぎても長過ぎてもいけない。あまりに時間が短いと酸化膜を十分に除去することができず、また除去すべき酸化膜の厚さは加熱工程を経て一定量とされているから処理時間が長過ぎても生産効率の点で不利だからである。具体的には、Ｈ2ガスの濃度が２％〜６０％の範囲であれば、３分〜６分程度の処理時間とすれば、酸化膜を十分に除去することができ、かつ、生産効率が極端に悪化してしまうことも回避し得ることが、実験等を通じて得られた経験則から分かっている。 The processing time for performing the cleaning process using plasma should not be too short or too long. If the time is too short, the oxide film cannot be removed sufficiently, and the thickness of the oxide film to be removed is set to a constant amount through the heating process, so that even if the processing time is too long, it is in terms of production efficiency. Because it is disadvantageous. More specifically, if the range the concentration of H 2 gas is 2% to 60%, if 3 minutes to 6 minutes to the processing time, it is possible to sufficiently remove the oxide film, and the production efficiency It is known from the empirical rule obtained through experiments and the like that it is possible to avoid that the deterioration of the temperature is extremely worse.
また、処理時間が長くなると、プラズマ照射時間も増え、これに伴い半田バンプ３の表面温度も上昇する。したがって、余りに処理時間が長くなると、例えば半田バンプ３がＳｎ−Ａｇ等の無鉛半田である場合には、Ａｇ3Ｓｎの表面への析出等が発生してしまうことが考えられる。このようなＡｇ3Ｓｎの表面への析出は、半田バンプ３の表面凹凸を顕著にするのみならず、半田バンプ３の融点高温化を招いてしまうおそれがある。
具体的には、Ｓｎ−Ａｇを例に挙げると、通常、半田として使う組成域では、標準的な溶融温度が２２０℃〜２３２℃程度であるが、Ａｇ3Ｓｎが析出した後の組成では、最低溶融温度が４８０℃程度となってしまう。このような融点高温化は、洗浄処理の後の行う接合工程に悪影響を及ぼすため、回避すべきである。
これらのことからも、洗浄処理の処理時間が余りに長くなってしまうのを抑制して６分程度に抑えることは有効であると言える。
Further, as the processing time becomes longer, the plasma irradiation time also increases, and the surface temperature of the solder bump 3 also increases accordingly. Therefore, when too a longer processing time, for example, when the solder bump 3 is a lead-free solder such as Sn-Ag is deposited like on the surface of the Ag 3 Sn is conceivable that occur. Such precipitation of Ag 3 Sn on the surface may not only make the surface irregularities of the solder bumps 3 noticeable, but also increase the melting point of the solder bumps 3.
Specifically, taking Sn-Ag as an example, in a composition range usually used as solder, the standard melting temperature is about 220 ° C to 232 ° C, but in the composition after Ag 3 Sn is precipitated, The minimum melting temperature is about 480 ° C. Such a high melting point temperature should be avoided because it adversely affects the bonding process performed after the cleaning process.
From these facts, it can be said that it is effective to suppress the cleaning processing time from becoming too long and to suppress it to about 6 minutes.
以上のような洗浄工程を行った後は、続いて、上側半導体チップ５と下側半導体チップ６とを互いに接合する接合工程を行う（Ｓ１０５）。
このとき、半田バンプ３は、上述した洗浄処理を経た後のものであり、Ｈ2ガスの還元作用により表面粗さが平滑化されたものである。すなわち、その半田バンプ３を大気中に曝した場合であっても、従来のようなプラズマのみの場合に比べると、酸化膜が形成され難い。
したがって、接合工程については、半田バンプ３の加熱溶融、すなわち上側半導体チップ５と下側半導体チップ６との接合を、洗浄装置１０のチャンバ室１１内から取り出して、大気中にて行うことが可能である。つまり、大気中で行っても、洗浄後の半田バンプ３の表面に酸化膜が形成されてしまうのを抑制できることから、接合不良や導通不良等の発生を未然に回避し得るのである。
After performing the cleaning process as described above, a bonding process for bonding the upper semiconductor chip 5 and the lower semiconductor chip 6 to each other is subsequently performed (S105).
At this time, the solder bump 3 has been subjected to the above-described cleaning process, and the surface roughness has been smoothed by the reducing action of H 2 gas. That is, even when the solder bumps 3 are exposed to the atmosphere, it is difficult to form an oxide film as compared with the conventional plasma alone.
Accordingly, in the bonding process, the solder bump 3 can be heated and melted, that is, the upper semiconductor chip 5 and the lower semiconductor chip 6 can be bonded from the
このことは、接合装置２０を、洗浄装置１０におけるチャンバ室１１内と同等の環境ではなく、大気中で用いることが可能であることを意味する。つまり、洗浄装置１０および接合装置２０を含む装置構成が複雑化してしまうのを回避し得るようになる。
This means that the joining device 20 can be used in the atmosphere, not in the same environment as the
ところで、接合工程では、上側半導体チップ５と下側半導体チップ６との接合にあたり、半田バンプ３に対する加熱溶融を行う必要がある。その一方で、半田バンプ３を加熱すると、既に説明したように、その半田バンプ３の表面における酸化膜の形成および成長が促進されることになる。
これらのことから、接合工程における半田バンプ３に対する加熱温度は、例えば半田バンプ３がＳｎ−Ａｇ等の無鉛半田である場合には、２２０℃〜３６０℃程度とすることが考えられる。２２０℃未満であると標準的な半田溶融温度に達しないからであり、３６０℃を超えると表面の顕著な酸化が起こり接合性が極端に悪化するからである。
By the way, in the joining process, it is necessary to heat and melt the solder bumps 3 when joining the upper semiconductor chip 5 and the lower semiconductor chip 6. On the other hand, when the solder bump 3 is heated, the formation and growth of the oxide film on the surface of the solder bump 3 is promoted as described above.
From these facts, it is conceivable that the heating temperature for the solder bump 3 in the joining process is about 220 ° C. to 360 ° C. when the solder bump 3 is a lead-free solder such as Sn—Ag. This is because if the temperature is less than 220 ° C., the standard solder melting temperature is not reached, and if it exceeds 360 ° C., remarkable oxidation of the surface occurs and the bonding property is extremely deteriorated.
また、接合工程に際しては、その接合工程に先立ち、あるいはその接合工程に付随して、律動工程を行うことも考えられる。
律動工程では、接合工程での半導体チップ５，６の各入出力端子５ａ，６ａ間の接合にあたり、その入出力端子５ａ，６ａの律動を行う。律動は、例えば接合装置２０に付設された超音波ヘッドを用いて、規則正しい繰り返し動作（振動や揺動等）を半導体チップ５，６に与えることで実現すればよい。なお、必ずしも半導体チップ５，６の両方が律動する必要はなく、いずれか一方のみであってもよい。
In addition, in the joining process, it is conceivable to perform a rhythmic process prior to or in connection with the joining process.
In the rhythm process, when the input / output terminals 5a and 6a of the semiconductor chips 5 and 6 are joined in the joining process, the input / output terminals 5a and 6a are rhythmized. The rhythm may be realized by applying regular repeated operations (vibration, oscillation, etc.) to the semiconductor chips 5 and 6 using, for example, an ultrasonic head attached to the bonding apparatus 20. Note that both of the semiconductor chips 5 and 6 do not necessarily have to rhythm, and only one of them may be used.
このような律動工程を行えば、半導体チップ５，６の各入出力端子５ａ，６ａの間にて、半田バンプ３同士または半田バンプ３と各入出力端子５ａ，６ａとが互いに接触するときに、その律動工程による律動によってそれぞれが互いに擦れ合い、これにより半田バンプ３への酸化膜の形成防止およびその除去が図れるようになる。したがって、接合工程を大気中で行う場合、洗浄工程から接合工程までにタイムラグがあり、その間半田バンプ３が大気中に曝されたままとなることも考えられるが、その場合であっても律動工程による酸化膜の形成防止およびその除去を経ることで、接合不良や導通不良等の発生防止を確実なものとすることができる。 If such a rhythmic process is performed, when the solder bumps 3 or the solder bumps 3 and the input / output terminals 5a and 6a come into contact with each other between the input / output terminals 5a and 6a of the semiconductor chips 5 and 6, respectively. By the rhythm of the rhythm process, they rub against each other, whereby the formation of an oxide film on the solder bump 3 can be prevented and removed. Therefore, when the joining process is performed in the atmosphere, there is a time lag between the cleaning process and the joining process, and during that time, the solder bumps 3 may be left exposed to the atmosphere. By preventing the formation of the oxide film and removing the oxide film, it is possible to reliably prevent the occurrence of defective bonding or poor conduction.
その後は、上側半導体チップ５と下側半導体チップ６との間の接合部分をアンダーフィル４によって封止する封止工程を行うとともに（Ｓ１０６）、その下側半導体チップ６の下面を配線基板７上に固着して、ボンディングワイヤを介して電気的な接続を確保するパッケージング工程を行って（Ｓ１０７）、パッケージングされることになる。このようにして、フリップチップ実装構造の半導体装置を完成させる。 Thereafter, the joint portion between the upper semiconductor chip 5 and the lower semiconductor chip 6 by underfill 4 performs a sealing to Rufutome step (S106), the wiring board 7 its lower surface of the lower semiconductor chip 6 A packaging process for securing the electrical connection via the bonding wire is performed (S107) , and the packaging is performed. As this, to complete the semiconductor device of the flip-chip mounting structure.
以上のように、本実施形態で説明した半導体装置の製造方法によれば、フリップチップ実装の場合であっても、フラックスを要することなく、半田バンプ３を介した各入出力端子５ａ，６ａ間の接合不良や導通不良等の発生を抑制し得ることできる。したがって、ボイドによるショート発生等を招くことなく、各入出力端子５ａ，６ａ間を良好に接合し得るので、フリップチップ実装の信頼性を十分に確保することができる。しかも、大気中での接合も可能であることから、フリップチップ実装のために用いる製造装置の構成が複雑化するのを回避し得るようになる。さらには、半田バンプ３を用いることで、例えばＤＲＡＭのセル上への適用が容易であるといったように、様々な製品用途への適用に対応可能な汎用性を得ることができる。また、半田バンプ３の表面の酸化膜除去を通じてアンダーフィル４の濡れ性が向上し、その充填性が良好になることが期待される。 As described above , according to the method of manufacturing a semiconductor device described in the present embodiment, even in the case of flip chip mounting, the flux is not required and the input / output terminals 5a and 6a are connected via the solder bumps 3. It is possible to suppress the occurrence of poor bonding and poor conduction. Accordingly, the input / output terminals 5a and 6a can be satisfactorily joined without causing a short-circuit due to voids, and the reliability of flip chip mounting can be sufficiently ensured. Moreover, since bonding in the atmosphere is possible, it is possible to avoid complication of the configuration of the manufacturing apparatus used for flip chip mounting. Furthermore, by using the solder bumps 3, it is possible to obtain versatility that can be applied to various product applications, such as easy application to DRAM cells. Further, it is expected that the wettability of the underfill 4 is improved through the removal of the oxide film on the surface of the solder bump 3 and the filling property is improved.
なお、本実施形態では、上側半導体チップ５と下側半導体チップ６とがフリップチップ実装されてなる構造の場合を主に説明したが、半導体チップ１が配線基板２上にフリップチップ実装されたもの等、他のフリップチップ実装構造のものであっても、全く同様に本発明を適用可能であることは勿論である。 In this embodiment, the case where the upper semiconductor chip 5 and the lower semiconductor chip 6 are flip-chip mounted has been mainly described. However, the semiconductor chip 1 is flip-chip mounted on the wiring substrate 2. Of course, the present invention can be applied to other flip chip mounting structures in exactly the same manner.
１…半導体チップ、１ａ…入出力端子、２…配線基板、２ａ…パッド端子、３…半田バンプ、４…アンダーフィル、５…上側半導体チップ、５ａ…入出力端子、６…下側半導体チップ、６ａ…入出力端子、７…配線基板、１０…洗浄装置、１１…チャンバ室、１２…電極、２０…接合装置 DESCRIPTION OF SYMBOLS 1 ... Semiconductor chip, 1a ... Input / output terminal, 2 ... Wiring board, 2a ... Pad terminal, 3 ... Solder bump, 4 ... Underfill, 5 ... Upper semiconductor chip, 5a ... Input / output terminal, 6 ... Lower semiconductor chip, 6a ... input / output terminal, 7 ... wiring board, 10 ... cleaning device, 11 ... chamber chamber, 12 ... electrode, 20 ... joining device
Claims (2)
前記フリップチップ実装による接続端子間の少なくとも一方に形成された半田バンプを加熱して、該半田バンプの表面における酸化膜を一定量成長させる加熱工程と、
前記加熱工程の後、前記半田バンプに対してプラズマを用いた洗浄を行う洗浄工程と、
前記洗浄工程による洗浄後の前記半田バンプを加熱溶融して前記接続端子間の接合を行う接合工程とを含み、
前記洗浄工程では、前記プラズマを用いた洗浄を、不活性ガスと還元性ガスとの混合ガス雰囲気中で行う、
半導体装置の製造方法。 A method of manufacturing a semiconductor device in which a semiconductor chip is flip-chip mounted,
Heating a solder bump formed on at least one of the connection terminals by the flip chip mounting to grow a certain amount of an oxide film on the surface of the solder bump; and
After the heating step, a cleaning step of cleaning the solder bumps using plasma,
A bonding step in which the solder bumps after cleaning by the cleaning step are heated and melted to bond between the connection terminals,
In the cleaning step, cleaning using the plasma is performed in a mixed gas atmosphere of an inert gas and a reducing gas.
A method for manufacturing a semiconductor device.
請求項１記載の半導体装置の製造方法。 In joining between the connection terminals in the joining step, joining the connection terminals according to the rhythm between the connection terminals,
A method according to claim 1 Symbol placement.
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| US8844793B2 (en) | 2010-11-05 | 2014-09-30 | Raytheon Company | Reducing formation of oxide on solder |
| WO2014115702A1 (en) * | 2013-01-24 | 2014-07-31 | 株式会社日立国際電気 | Method for manufacturing semiconductor device, substrate treatment apparatus and recording medium |
| CN111727494B (en) * | 2018-02-14 | 2023-09-08 | 库利克和索夫工业公司 | Method for soldering a semiconductor element to a substrate comprising the use of a reducing gas and associated soldering machine |
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| JPH04107921A (en) * | 1990-08-28 | 1992-04-09 | Matsushita Electric Ind Co Ltd | Plasma cleaning device |
| JPH10224029A (en) * | 1997-02-05 | 1998-08-21 | Sony Corp | Production of bump |
| JP2000117213A (en) * | 1998-10-13 | 2000-04-25 | Matsushita Electric Ind Co Ltd | Plasma washing method and device |
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