CN102543725A - Method for manufacturing high-speed silicon-germanium heterojunction bipolar transistor (SiGe HBT) - Google Patents
Method for manufacturing high-speed silicon-germanium heterojunction bipolar transistor (SiGe HBT) Download PDFInfo
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- CN102543725A CN102543725A CN201010596088XA CN201010596088A CN102543725A CN 102543725 A CN102543725 A CN 102543725A CN 201010596088X A CN201010596088X A CN 201010596088XA CN 201010596088 A CN201010596088 A CN 201010596088A CN 102543725 A CN102543725 A CN 102543725A
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Abstract
The invention discloses a method for manufacturing a high-speed silicon-germanium heterojunction bipolar transistor (SiGe HBT). A method for forming a collector region comprises the following steps of: repeatedly implanting local collector region N-type impurities in a gradually-changed depth mode after a local active region of the transistor is opened; and performing rapid thermal annealing to ensure that the repeatedly-implanted N-type impurities are integrally connected so as to form uniform N-type local collector region impurity distribution. By the method, the total resistance of the collector region can be effectively reduced, and the cut-off frequency of the high-speed transistor is effectively improved; and the high-speed SiGe HBT manufactured by the method is low in cost and high in performance.
Description
Technical field
The invention belongs to the semiconductor integrated circuit manufacturing process, especially a kind of manufacturing approach of high speed Ge-Si heterojunction bipolar transistor.
Background technology
In radio frequency applications; Need increasingly high device feature frequency; RFCMOS (RF CMOS) is though can realize upper frequency in advanced person's technology; But be difficult to satisfy fully radio frequency requirement, realize the characteristic frequency more than the 40GHz as being difficult to, and the R&D costs of advanced technologies also are very high; Compound semiconductor can be realized very high characteristic frequency device, but because the shortcoming that material cost is high, size is little adds that the most compounds semiconductor is poisonous, has limited its application.Si/SiGe HBT (germanium or Ge-Si heterojunction bipolar transistor) then is the fine selection of hyperfrequency device.
Conventional high speed triode collector region manufacture craft adopts expensive collector region outer layer growth; And adopt once or the local collector region of secondary injects; And adopt highly doped collector region buried regions; Adopt high concentration high-energy N type to inject, connect the collector region buried regions, form collector terminal (collector pick-up).The low-doped collector region in outer Yanzhong on the collector region buried regions, the SiGe extension that P type on the throne mixes forms the base, and heavy then N type DOPOS doped polycrystalline silicon constitutes emitter, finally accomplishes the making of HBT.This device technology mature and reliable, but major defect has: and 1, collector region extension cost is high; 2, the formation inhomogeneous 3, collectorpick-up of the CONCENTRATION DISTRIBUTION of local collector region leans on the ion of high dose, macro-energy to inject, and could the collector region buried regions be drawn, and therefore shared device area is very big.
Summary of the invention
The technical problem that the present invention will solve provides the manufacturing approach of a kind of low cost, high performance high speed Ge-Si heterojunction bipolar transistor; Make and do not have expensive collector region epitaxial loayer in the device; Adopt repeatedly gradual change degree of depth collector region to inject; Form uniform local collector region N type Impurity Distribution, effectively reduced the overall resistance of collector region, effectively raise the cut-off frequency of high speed triode.
For solving the problems of the technologies described above, the present invention provides a kind of manufacturing approach of high speed Ge-Si heterojunction bipolar transistor, comprises forming collector region, base and emitter region; The formation method of its collector region is: the local collector region N of the repeatedly injection type impurity of opening the gradual change degree of depth in back at the local active area of triode; Through rapid thermal annealing the N type impurity that repeatedly injects is joined together then, form the local collector region Impurity Distribution of uniform N type.
This method specifically comprises the steps:
Step 1, on P type silicon substrate, form oxygen district's groove and active area;
Step 2, carry out N type ion in the bottom, oxygen district, field of said active area both sides and inject and form counterfeit buried regions;
Step 3, in said oxygen district groove, insert silica and form an oxygen district;
Step 4, open the local collector region N of the repeatedly injection type impurity of the back gradual change degree of depth at local active area; And then carry out rapid thermal anneal process, and the N type impurity that repeatedly injects is joined together, form the local collector region Impurity Distribution of uniform N type;
Step 5, formation base;
Step 6, formation emitter region;
Step 7, in the oxygen district, field at said counterfeit buried regions top, form the deep hole contact and draw said collector region electrode.
Step 2 is specially: at first; Define counterfeit buried regions zone with photoresist, protect window to carry out N type ion through the counterfeit buried regions of photoresist formation and inject, through the horizontal proliferation of injection ion in the bottom, oxygen district, field of active area both sides; Be intersected in active area, form counterfeit buried regions; The N type ion implantation technology condition of said counterfeit buried regions is: when implanted dopant was phosphorus, implantation dosage was 3e14/cm2～5e15/cm2, and the injection energy is 3KeV～20keV; When implanted dopant was arsenic, implantation dosage was 3e14/cm2～5e15/cm2, and the injection energy is 5KeV～40keV.
In the step 4, the injection number of times that repeatedly injects local collector region N type impurity of the said gradual change degree of depth is 3～5 times, injects the energy trend that tapers off at every turn; When implanted dopant was phosphorus, inject energy was 50～500kev at every turn; When implanted dopant was arsenic, inject energy was 100～1000kev at every turn; The dosage that the surface is once injected is 5e12～1e14/cm2, and the dosage that the middle part is injected several times is 1e13～2e14/cm2, and a darkest implantation dosage is 1e14～1e15/cm2.
In the step 4, the process conditions of said rapid thermal anneal process are: temperature is 990～1060 ℃; Time is 5 seconds to 30 seconds.
In the step 7, the contact of said deep hole through in the oxygen district, field at said counterfeit buried regions top, open a deep hole and in said deep hole behind deposit titanium/titanium nitride barrier metal layer, insert tungsten again and form.
Compare with prior art; The present invention has following beneficial effect: the present invention proposes high speed Ge-Si heterojunction bipolar transistor manufacture craft a kind of economy, high performance; Adopt the local collector region of the repeatedly gradual change degree of depth to inject; Form uniform local collector region N type Impurity Distribution, effectively reduced the overall resistance of collector region, effectively raise the cut-off frequency of high speed triode.
Description of drawings
Fig. 1 is the sketch map that adopts the local collector region of the repeatedly gradual change degree of depth to inject among the present invention;
Fig. 2 is the sketch map that adopts the high speed Ge-Si heterojunction bipolar transistor of the inventive method formation.
Embodiment
Below in conjunction with accompanying drawing and embodiment the present invention is done further detailed explanation.
As depicted in figs. 1 and 2, there are not collector region buried regions and collector region epitaxial loayer in the high speed Ge-Si heterojunction bipolar transistor device of employing the inventive method manufacturing, the substitute is and make N type breast buried regions (PseudoBuried Layer) and doping collector region.At the shallow-trench isolation high dose of HBT both sides, low-yield inject phosphonium ion or arsenic ion, the horizontal proliferation through phosphorus or arsenic is intersected in active area, forms buried regions.Through the hard mask layer (Hard Mask) on the local active area of erosion removal, phosphonium ion or arsenic ion at local triode region injection low dosage form collector region then.
As shown in Figure 1, the present invention adopts the local collector region of the repeatedly gradual change degree of depth to inject, the high speed triode collector region technology of low-cost and high-performance, the repeatedly injection collector region N type impurity of the gradual change degree of depth after the local active area of high speed triode is opened; Injecting number of times is 3～5 times, injects the energy trend that tapers off at every turn; When implanted dopant was phosphorus, inject energy was 50～500kev at every turn; When implanted dopant was arsenic, inject energy was 100～1000kev at every turn; The dosage that the surface is once injected is 5e12～1e14/cm2, and the dosage that the middle part is injected several times is 1e13～2e14/cm2, and a darkest implantation dosage is 1e14～1e15/cm2; Form uniform local collector region N type Impurity Distribution, and connect, effectively reduced the overall resistance of collector region, effectively raise the cut-off frequency of high speed triode with the counterfeit buried regions of N+.
The present invention no longer injects through high concentration high-energy N type and makes collector terminal, but through carving the deep trap contact hole in the oxygen on the scene, inserts Ti/TiN transition metal layer and metal W, and buried regions is born in contact, realizes drawing of collector electrode.This contact hole is very near apart from the device base, has avoided excessive collector resistance, has also reduced the parasitic capacitance of collector electrode.
Lift the manufacturing approach that an embodiment specifies high speed Ge-Si heterojunction bipolar transistor of the present invention below, this method mainly comprises the steps:
Step 1, on P type silicon substrate, form oxygen district's groove and active area.
Step 2, the counterfeit buried regions of formation N+.At first, with the counterfeit buried regions of lithographic definition zone, counterfeit buried regions protection window when promptly forming said counterfeit buried regions ion with photoresist and injecting.The said counterfeit buried regions protection window that forms through said photoresist carries out the injection of N type ion in the bottom, oxygen district, field of said active area both sides, through injecting the horizontal proliferation of ion, is intersected in active area, forms the counterfeit buried regions of said N+.The N type ion implantation technology condition of said counterfeit buried regions is: high dose, low-yield phosphonium ion or the arsenic ion of injecting.When implanted dopant was phosphorus, implantation dosage was 3e14/cm2～5e15/cm2, and the injection energy is 3KeV～20keV; When implanted dopant was arsenic, implantation dosage was 3e14/cm2～5e15/cm2, and the injection energy is 5KeV～40keV.
Step 3, in said oxygen district groove, insert silica and form an oxygen district.
Step 4, formation collector region.At first; Through the hard mask layer (HardMask) on the local active area of erosion removal; Promptly open the local active area of triode and form collector region protection window; As shown in Figure 1 then, (injecting number of times is 3～5 times, injects the energy trend that tapers off at every turn to open the local collector region N of the repeatedly injection type impurity that adopts the gradual change degree of depth in the back at the local active area of triode; When implanted dopant was phosphorus, inject energy was 50～500kev at every turn; When implanted dopant was arsenic, inject energy was 100～1000kev at every turn; The dosage that the surface is once injected is 5e12～1e14/cm2, and the dosage that the middle part is injected several times is 1e13～2e14/cm2, and a darkest implantation dosage is 1e14～1e15/cm2), form collector region.The said collector region degree of depth forms good the contact greater than the degree of depth and the said collector region of bottom, said oxygen district with said counterfeit buried regions.And then carry out rapid thermal anneal process and (adopt temperature: 990～1060 ℃; Time: 5 seconds to 30 seconds), the N type impurity that repeatedly injects is joined together, form the local collector region Impurity Distribution of uniform N type, and connect (see figure 2), form collector region, effectively raise the cut-off frequency of high speed triode than low resistance with the counterfeit buried regions of N+.
Step 5, form the base by this area conventional method.At first, form base window dielectric layer; Secondly, form the base window; Then, form the silica-based district of germanium.
Step 6, form the emitter region by this area conventional method.At first, form the emitter window dielectric layer; Secondly, form emitter window; Carry out N type polycrystalline silicon growth and etching again and form the N+ polysilicon emissioning area.Make the monox lateral wall of said emitter region then, said monox lateral wall can be avoided the short circuit of silicide on emitter region silicide and the outer base area.
Step 7, etching forms the deep hole contact and draws said collector region electrode in the oxygen district, field at said counterfeit buried regions top.The contact of said deep hole be through in the oxygen district, field at said counterfeit buried regions top, open a deep hole and in said deep hole behind deposit titanium/titanium nitride barrier metal layer, insert tungsten again and form, buried regions is born in this deep hole contact contact, realizes drawing of collector electrode.This deep hole contact is very near apart from the device base, has avoided excessive collector resistance, has also reduced the parasitic capacitance of collector electrode.This method also comprises the technology of the contact hole that forms said outer base area, emitter region, and other postchannel process, forms final high speed Ge-Si heterojunction bipolar transistor, sees Fig. 2.
Claims (6)
1. the manufacturing approach of a high speed Ge-Si heterojunction bipolar transistor comprises forming collector region, base and emitter region; It is characterized in that; The formation method of its collector region is: the local collector region N of the repeatedly injection type impurity of opening the gradual change degree of depth in back at the local active area of triode; Through rapid thermal annealing the N type impurity that repeatedly injects is joined together then, form the local collector region Impurity Distribution of uniform N type.
2. the manufacturing approach of high speed Ge-Si heterojunction bipolar transistor as claimed in claim 1 is characterized in that, comprises the steps:
Step 1, on P type silicon substrate, form oxygen district's groove and active area;
Step 2, carry out N type ion in the bottom, oxygen district, field of said active area both sides and inject and form counterfeit buried regions;
Step 3, in said oxygen district groove, insert silica and form an oxygen district;
Step 4, open the local collector region N of the repeatedly injection type impurity of the back gradual change degree of depth at local active area; And then carry out rapid thermal anneal process, and the N type impurity that repeatedly injects is joined together, form the local collector region Impurity Distribution of uniform N type;
Step 5, formation base;
Step 6, formation emitter region;
Step 7, in the oxygen district, field at said counterfeit buried regions top, form the deep hole contact and draw said collector region electrode.
3. the manufacturing approach of high speed Ge-Si heterojunction bipolar transistor as claimed in claim 2; It is characterized in that step 2 is specially: at first, define counterfeit buried regions zone with photoresist; The counterfeit buried regions protection window that forms through photoresist carries out the injection of N type ion in the bottom, oxygen district, field of active area both sides; Through injecting the horizontal proliferation of ion, be intersected in active area, form counterfeit buried regions; The N type ion implantation technology condition of said counterfeit buried regions is: when implanted dopant was phosphorus, implantation dosage was 3e14/cm2～5e15/cm2, and the injection energy is 3KeV～20keV; When implanted dopant was arsenic, implantation dosage was 3e14/cm2～5e15/cm2, and the injection energy is 5KeV～40keV.
4. the manufacturing approach of high speed Ge-Si heterojunction bipolar transistor as claimed in claim 2 is characterized in that, in the step 4, the injection number of times that repeatedly injects local collector region N type impurity of the said gradual change degree of depth is 3～5 times, injects the energy trend that tapers off at every turn; When implanted dopant was phosphorus, inject energy was 50～500kev at every turn; When implanted dopant was arsenic, inject energy was 100～1000kev at every turn; The dosage that the surface is once injected is 5e12～1e14/cm2, and the dosage that the middle part is injected several times is 1e13～2e14/cm2, and a darkest implantation dosage is 1e14～1e15/cm2.
5. the manufacturing approach of high speed Ge-Si heterojunction bipolar transistor as claimed in claim 2 is characterized in that, in the step 4, the process conditions of said rapid thermal anneal process are: temperature is 990～1060 ℃; Time is 5 seconds to 30 seconds.
6. the manufacturing approach of high speed Ge-Si heterojunction bipolar transistor as claimed in claim 2; It is characterized in that: in the step 7, the contact of said deep hole through in the oxygen district, field at said counterfeit buried regions top, open a deep hole and in said deep hole behind deposit titanium/titanium nitride barrier metal layer, insert tungsten again and form.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103730354A (en) * | 2012-10-10 | 2014-04-16 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing germanium-silicon heterojunction bipolar transistor |
| CN106298517A (en) * | 2015-05-13 | 2017-01-04 | 北大方正集团有限公司 | The manufacture method of plane VDMOS device |
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| CN1231506A (en) * | 1998-04-07 | 1999-10-13 | 日本电气株式会社 | High-speed and low parasitic capacitance semiconductor device and making method thereof |
| US6001701A (en) * | 1997-06-09 | 1999-12-14 | Lucent Technologies Inc. | Process for making bipolar having graded or modulated collector |
| US6352901B1 (en) * | 2000-03-24 | 2002-03-05 | Industrial Technology Research Institute | Method of fabricating a bipolar junction transistor using multiple selectively implanted collector regions |
| US20020177253A1 (en) * | 2001-05-25 | 2002-11-28 | International Business Machines Corporation | Process for making a high voltage NPN Bipolar device with improved AC performance |
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2010
- 2010-12-20 CN CN201010596088XA patent/CN102543725A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6001701A (en) * | 1997-06-09 | 1999-12-14 | Lucent Technologies Inc. | Process for making bipolar having graded or modulated collector |
| CN1231506A (en) * | 1998-04-07 | 1999-10-13 | 日本电气株式会社 | High-speed and low parasitic capacitance semiconductor device and making method thereof |
| US6352901B1 (en) * | 2000-03-24 | 2002-03-05 | Industrial Technology Research Institute | Method of fabricating a bipolar junction transistor using multiple selectively implanted collector regions |
| US20020177253A1 (en) * | 2001-05-25 | 2002-11-28 | International Business Machines Corporation | Process for making a high voltage NPN Bipolar device with improved AC performance |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103730354A (en) * | 2012-10-10 | 2014-04-16 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing germanium-silicon heterojunction bipolar transistor |
| CN106298517A (en) * | 2015-05-13 | 2017-01-04 | 北大方正集团有限公司 | The manufacture method of plane VDMOS device |
| CN106298517B (en) * | 2015-05-13 | 2019-04-02 | 北大方正集团有限公司 | The production method of plane VDMOS device |
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