CN102543171B - Phase change memory with redundant circuit and redundancy method for phase change memory - Google Patents
Phase change memory with redundant circuit and redundancy method for phase change memory Download PDFInfo
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- CN102543171B CN102543171B CN201210036652.1A CN201210036652A CN102543171B CN 102543171 B CN102543171 B CN 102543171B CN 201210036652 A CN201210036652 A CN 201210036652A CN 102543171 B CN102543171 B CN 102543171B
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Abstract
The invention discloses a phase change memory with a redundant circuit. The phase change memory comprises P redundancy lines or Q redundancy columns, information storage circuits and a line or column switch selection circuit, wherein each line control line is connected with P+1 line switches or each column control line is connected with Q+1 column switches; a zeroth line switch or a first column switch is connected in series to the corresponding line control line or the corresponding column control line; one end of each of a second line switch to a P-th line switch or a seond column switch to a Q-th column switch is connected to the corresponding line control line or the corresponding column control line, and the other end of each of the first line switch to the P-th line switch or the first column switch to the Q-th column switch is sequentially connected to the next line control line to a P-th line control line or the next column control line to a Q-th column control line; each line switch or each column switch corresponds to one information storage circuit; the line or column switch selection circuit is connected with all information storage circuits; all information storage circuits are connected with a write circuit; and when a certain line or a certain column of a storage array is determined to be defective, switch turn-on or turn-off information is stored in each information storage circuit, and the corresponding line switch or the corresponding column switch is controlled, so the defective line or the defective column can be quickly replaced by a non-defective line or a non-defective column. Meanwhile, the invention discloses a redundancy method for the phase change memory.
Description
Technical field
The present invention relates to phase transition storage, particularly a kind of have the phase transition storage of redundant circuit and realize the method for redundancy.
Background technology
Phase transition storage is a kind of storer based on phase-change material, and by applying a long period on top of the phase change material and the medium electric pulse of intensity, phase-change material can be made to be converted to crystalline state by amorphous state, and this process is referred to as set process.Because crystalline state has low-resistance value, be usually defined as data " 1 ".By applying the high but electric pulse that action time is very brief of intensity on top of the phase change material, phase-change material can be made to be converted to amorphous state by crystalline state, and this process is referred to as reset process.Amorphous state has high resistance, is usually defined as data " 0 ".
Consider the data retention characteristics of phase transition storage, the process that namely can activate this spontaneous crystallization of crystallization by Long Time Thermal due to amorphous state is converted to crystalline state, therefore the normality of phase-change material is crystalline state (i.e. data " 1 "), and what the data " 0 " namely stored may be spontaneous after the longer time is converted to data " 1 ".Therefore should be noted that the authenticity of data " 1 ".
Existing phase transition storage comprises write circuit and storage array, is the row or column of part in storage array is used as redundant row or redundant columns when realizing redundancy, and redundancy row or column is used to replace defective row or column in storage array; The redundant row being wherein used for storing concrete ranks replacement information is called information row.General, method is by write circuit memory address in information row, when phase transition storage will carry out read-write operation time, first the address stored in the memory unit address of read-write and information row to be compared, to determine that this storage unit is the need of being replaced.Cause access time elongated like this, have impact on the storage speed of storer.
Summary of the invention
In view of this, fundamental purpose of the present invention is that providing a kind of has the phase transition storage of redundant circuit and realize the method for redundancy, to improve the read or write speed of phase transition storage.
According to first aspect of above-mentioned purpose, the invention provides a kind of phase transition storage with redundant circuit, comprise write circuit and storage array, also comprise P redundant row or Q redundant columns, multiple information storage circuit, row or column switch selection circuit.
The row or column continuous arrangement of a described P redundant row or Q redundant columns and storage array.
Every a line control line of described storage array is connected with P+1 row switch or each row control line is connected with Q+1 row switch; 1st row switch or row switch series are associated on the row or column control line of place; One end of 2 to the P+1 row switch or the 2 to the Q+1 row switch is connected to place row or column control line, and the other end is connected on lower 1 to P capable or 1 to the Q row control line of place row or column successively.
Each row switch described or each row Switch Controller should connect an information storage circuit; Described row or column switch selection circuit is connected with all information storage circuits; Described all information storage circuits are connected with write circuit.
When testing out a certain row or column defectiveness of storage array, first by row or column switch selection circuit, for all row or column after defectiveness row or column and defectiveness row or column, select the information storage circuit that current closed row switch or row Switch Controller are answered, in the information storage circuit selected, row or column switch OFF information is stored by write circuit, and described information storage circuit output switch control signal, turn off corresponding row switch or row switch; Again by row or column switch selection circuit, for all row or column after defectiveness row or column and defectiveness row or column, select the information storage circuit that a row switch that be connected with zero defect row or column, same sequence number or row Switch Controller are answered, in the information storage circuit selected, row or column switch conduction information is stored by write circuit, and described information storage circuit output switch control signal, the row switch that conducting is corresponding or row switch.
According to second aspect of above-mentioned purpose, the invention provides a kind of method that phase transition storage realizes redundancy, adopt the phase transition storage of preceding claim; When testing out a certain row or column defectiveness of storage array, perform following steps:
A, by row or column switch selection circuit, for all row or column after defectiveness row or column and defectiveness row or column, select the information storage circuit that current closed row switch or row Switch Controller are answered, in the information storage circuit selected, row or column switch OFF information is stored by write circuit, and described information storage circuit output switch control signal, turn off corresponding row switch or row switch;
B, by row or column switch selection circuit, for all row or column after defectiveness row or column and defectiveness row or column, select the information storage circuit that a row switch that be connected with zero defect row or column, same sequence number or row Switch Controller are answered, in the information storage circuit selected, row or column switch conduction information is stored by write circuit, and described information storage circuit output switch control signal, the row switch that conducting is corresponding or row switch.
As seen from the above technical solutions, of the present invention thisly have the phase transition storage of redundant circuit and realize the method for redundancy, when finding defective row or column when testing, the information of these row or column being directly stored in phase-change material, these information can also being preserved when power-off like this.Controlled the break-make of respective switch when normal work by the information read in phase-change material, in circuit, directly replace defective row or column by corresponding redundancy row or column.Compare with regard to not needing all to carry out address at every turn when read-write like this, improve read or write speed, and eliminate comparator circuit.
Accompanying drawing explanation
Fig. 1 is the default conditions (row is replaced) of phase transition storage in a preferred embodiment of the present invention;
Fig. 2 for phase transition storage shown in Fig. 1 have certain a line need replace time state;
The structure that Fig. 3 is an information storage circuit in phase transition storage shown in Fig. 1 and the connection layout with logical circuit and write circuit thereof;
A kind of duty (phase-change material 35 is write " 0 ") that Fig. 4 a is circuit shown in Fig. 3;
Another duty (to phase-change material 36 one writing) that Fig. 4 b is circuit shown in Fig. 3;
Fig. 5 is the default conditions (row are replaced) of the phase transition storage of another preferred embodiment of the present invention;
Fig. 6 for phase transition storage shown in Fig. 5 have a certain row need replace time state.
Embodiment
Referring to the accompanying drawing specific embodiment that develops simultaneously, this phase transition storage with redundant circuit of the present invention and the method realizing redundancy thereof are described in detail.
Of the present invention thisly have the phase transition storage of redundant circuit and realize the method for redundancy, both can be realized by the mode increasing redundant row, also can be realized by the mode of increase redundant columns.Below be described in detail for embodiment respectively.
First preferred embodiment
The present embodiment is that the mode by increasing redundant row realizes, the phase transition storage of the present embodiment and the phase change memory something in common of prior art are all to have write circuit and storage array and P redundant row, and difference is also to comprise multiple information storage circuit and a row switch selection circuit.
P redundant row in the present embodiment and the storage line continuous arrangement of storage array.Every a line control line of storage array is connected with P+1 row switch.Wherein, the 1st row switch series is associated on be expert at control line, and one end of the 2 to the P+1 row switch is connected to be expert at control line, and the other end is connected on be expert at lower 1 to P capable control line successively.Wherein, each row Switch Controller should connect an information storage circuit.Row switch selection circuit is connected with all information storage circuits, and all information storage circuits are connected with write circuit again.
When testing out storage array a line defectiveness, first by row switch selection circuit, for defectiveness capable and defectiveness capable after all row, select the information storage circuit that current closed row Switch Controller is answered, by write circuit storage line switch OFF information in the information storage circuit selected, and described information storage circuit output switch control signal, turn off corresponding row switch; Again by row switch selection circuit, for defectiveness capable and defectiveness capable after all row or column, select an information storage circuit of answering with the capable row Switch Controller that be connected, same sequence number of zero defect, by write circuit storage line switch conduction information in the information storage circuit selected, and described information storage circuit output switch control signal, the row switch that conducting is corresponding.
Fig. 1 shows the annexation of row switch and storage array and redundant row in the phase transition storage of the present embodiment, and the row switch in Fig. 1 is in default conditions.
As shown in Figure 1, the storage array of the present embodiment phase transition storage has m storage line 11, a n memory row, altogether m*n phase-change memory cell 10.This phase transition storage has 3 redundant rows 12, and continuous arrangement is after m storage line 11.
In Fig. 1, the row control line WL<i> of each storage line is all connected with 4 row interrupteur SW
i<j>, wherein i is from 0 to 3 from 0 to m-1, j.As: the row control line WL<0> of the 0th storage line is connected to SW
0<0>-SW
0<3> is totally 4 row switches; , the control line WL<m-1> that m-1 is capable is connected to SW
m-1<0>-SW
m-1<3>.Wherein, 3 row of below this row and this row received respectively by 4 row switches of each storage line, namely the 0th row switch series is associated on be expert at control line, and one end of the 1 to the 3 row switch is connected to be expert at control line, and the other end is connected on be expert at lower 1 to 3 row control lines successively.Redundant row, as the spare row of storage line, is connected with corresponding row switch in an identical manner, e.g., and interrupteur SW
m-2<0>-SW
m-2<3> is capable and two redundant rows (being designated as the redundant row of 0 and 1 in figure) by the m-1 that receives below capable and this row of m-2 respectively; Interrupteur SW
m-1<0>-SW
m-1<3> will receive 3 redundant rows of below capable and this row of m-1 respectively.
Fig. 1 shows the default conditions of row switch, is specially the SW<0> of each storage line ... SW
m-1<0> conducting, SW
0<1>-SW
0<3> ..., SW
m-1<1>-SW
m-1<3> turns off.Now each row control signal WL<0> ... WL<m-1> removes the corresponding row that draws oneself up.More than that if hypothesis has h redundant row (h≤m), each row control signal is connected to g switch, then g need meet g=h+1 with 3 redundancy behavior examples.
Find that there is certain a line when tested when makeing mistakes, the 1st row being assumed to be in storage line 11 (make mistakes, and needs to replace by the storage line (in the application's text, the counting of row is from the 0th row) for digital 1 place in Fig. 1.
As shown in Figure 2, now the SW of the 1st row
1<0> disconnects, SW
1<1> closes.And the SW of following all row
2<0> ... SW
m-1<0> disconnects, SW
2<1> ... SW
m-1<1> closes.That is, replace the 1st row by the 2nd row, the 3rd row replaces the 2nd row, by that analogy, finally replaces m-1 by the 0th row of redundant row 12 capable.
Can be seen by Fig. 2, the 1st row that storage line 11 li is made mistakes disconnects with all row control signals, does not re-use.For ease of understanding, in Fig. 2, the line number of no 1st row is deleted, using the 2nd row before replacement as the 1st present row, the rest may be inferred.That is, redundant row has been reduced to 2 row by 3 row.
If when also having row to make mistakes in ensuing test, be assumed to be xth row and make mistakes, the SW of this row
x<1>, and the SW of all row below this row
x+1<1>, SW
x+2<1> ... SW
m-1<1> disconnects, by the SW of this row
x<2>, and the SW of all row below this row
x+1<2>, SW
x+2<2> ... SW
m-1<2> closes.Finally replace m-1 by the 1st row of redundant row capable.By that analogy, until all provisional capitals are completed.
If find that there is the 3rd defect row, suppose that this defect behavior f is capable, then the SW of this row
f<2>, and the SW of all row below this row
f+1<2>, SW
f+2<2> ... SW
m-1<2> disconnects, by the SW of this row
f<3>, and the SW of all row below this row
f+1<3>, SW
f+2<3> ... SW
m-1<3> closes.Finally replace m-1 by the 2nd row of redundant row capable.
Like this, after being completed, all provisional capitals of makeing mistakes have been replaced complete, compare, improve read or write speed when reading and writing storer afterwards with regard to not needing all to carry out address at every turn.
In the present embodiment, be replaced in order by row switch, in practical application, also can not replace in order, behavior zero defects all after replacing only need be made capable.
Each row switch in Fig. 1 is the switch with control end, and the control end of each row switch is connected on a corresponding information storage circuit, and the switch controlling signal exported by information storage circuit is to control conducting or shutoff.
Information storage circuit in the present embodiment can be realized by nonvolatile memory, and it is using the row switch conduction of storage or turn off the row switch exporting to correspondence as control signal, with the conducting of control lines switch or shutoff.This information storage circuit also can realize with the circuit of phase-change material composition.Row switch selection circuit in the present embodiment is realized by logical circuit, and the concrete decoding scheme that can adopt realizes.
Fig. 3 shows one by the structure of the information storage circuit of phase-change material composition and the annexation with logical circuit and write circuit thereof.As shown in Figure 3, this information storage circuit comprises: three switch S 31-S33, two phase-change materials 35 and 36, PMOS 39, NMOS tube 40 and phase inverters 41.
Wherein the first end of the first switch S 31 is connected with write circuit 31, and the second end is connected with the first end of the first phase-change material 35.The first end of the first phase-change material 35 is also connected with the drain electrode of PMOS 39, and its second end is connected with the first end of the second phase-change material 36, and connecting valve control signal wire.The source electrode of PMOS 39 is connected with power supply.Second end of the second phase-change material 36 is connected with the drain electrode of NMOS tube 40.The source ground of NMOS tube 40.Described second switch S32 is in parallel with the first phase-change material 35, and described 3rd switch S 33 is in parallel with the second phase-change material 36.
Logical circuit 34 switch selection circuit at once in Fig. 3, the row control signal 32 that its reception testing software sends and switch selection signal 33, export the information storage circuit that row switch selection signal is answered to the row Switch Controller selected.
The row switch selection signal that in Fig. 3, logical circuit 34 exports outputs to the first end of phase inverter 41, and the second end of phase inverter 41 is connected to the grid of PMOS 39.This row switch selection signal also outputs to the grid of NMOS tube 40 simultaneously.
Row switch in the present embodiment is the switch of band control end, and the switch controlling signal line of each information storage circuit is connected on the control end of the row switch corresponding with it, to control conducting or the shutoff of corresponding row switch.
In circuit shown in Fig. 3, the object of the first switch S 31, second switch S32 and the 3rd switch S 33 will realize writing 0 or write 1 to phase-change storage material exactly, thus the information of respective switch conducting or shutoff is stored in phase-change material 35 and phase-change material 36 li.Non-volatile due to phase-change material, when the complete power down of storage array defect test, information also can not be lost.When system normally works on power afterwards, automatically complete opening of switch according to phase-change material 35 and 36 li of information stored or turn off, finally realizing by the replacement of redundancy row (column) to row (column) of makeing mistakes.
When carrying out defect test to storage array, the default conditions of the first switch S 31, second switch S32 and the 3rd switch S 33 turn off, as shown in Figure 3.Row control signal 32 and switch gating signal 33 come from the output of test procedure, specifically can determine current certain switch (SW that will connect certain row control signal (WL<x>) according to the two output after logical circuit 34
x<0>-SW
xwhich in <3>) carry out the operation of conducting or shutoff.
When test procedure finds that certain row is wrong and will turn off certain row switch of certain row, perform following steps:
Step 1, row control signal 32 and switch gating signal 33 exported after logical circuit 34 information storage circuit 38 that row switch selection signal (gating signal) answers to the row Switch Controller selected, remove selected first phase-change material 35 and second phase-change material 36 that wherein will write data.
That is, the row control signal 32 that logical circuit 34 inputs when receiving test and switch selection signal 33, to every a line, select the information storage circuit 38 that current closed row Switch Controller is answered, export row switch selection signal to the information storage circuit 38 selected, conducting PMOS 39 and NMOS tube 40, thus selected first phase-change material 35 and second phase-change material 36 that wherein will write data.
Such as: the SW supposing the 1st row in Fig. 2
1the row defectiveness of <0>, have selected the SW be connected with WL<0>-WL<m-1Grea tT.GreaT.GT in this step
0<0>, SW
1<0> ... .SW
m-1<0>.
The first switch S 31 in each information storage circuit 38 that step 2, test procedure control conducting is selected and the 3rd switch S 33, turn off second switch S32, write " 0 " by write circuit 31 to the first phase-change material 35.
In this step, due to the first switch S 31 and the 3rd switch S 33 conducting, write circuit 31 is write " 0 " the first phase-change material 35, and write signal, through the 3rd switch S 33 ground connection, therefore shields the second phase-change material 36.
Now circuit state as shown in fig. 4 a, and the state of an information storage circuit 38 of selection is only shown in Fig. 4 a, and actual all states by the information storage circuit 38 selected are identical with it, no longer repeat specification here.
Step 3, test procedure control the second switch S32 in each information storage circuit 38 of conducting selection, turn off the 3rd switch S 33, by write circuit 31 to the second phase-change material 36 one writing.
In this step, due to the first switch S 31 and second switch S32 conducting, therefore shield the first phase-change material 35, write signal through the first switch S 31 and second switch S32 to the second phase-change material 36 one writing.
Now circuit state as shown in Figure 4 b, and the state of an information storage circuit 38 of selection is only shown in Fig. 4 b, and actual all states by the information storage circuit 38 selected are identical with it, no longer repeat specification here.
Now, phase-change material 35 is high value, and phase-change material 36 is low resistance.
Step 4, the first switch S 31, second switch S32 and the 3rd switch S 33 turned off in each information storage circuit 38 of selection.
When normal work, the first switch S 31 in this information storage circuit 38, second switch S32 and the 3rd switch S 33 turn off, PMOS 39 and NMOS tube 40 conducting, and the switch controlling signal 37 of output is low level, and the corresponding line switch controlled is turned off.
Here, by writing " 0 " to phase-change material 35 and to phase-change material 36 one writing, the information that corresponding line switch has been turned off being stored in phase-change material 35 and phase-change material 36 li.Like this when system worked well, corresponding line switch is just in the state of shutoff.
Above-mentioned 4 steps are used to capable for defectiveness removal, and step is below by the function that realization is capable with zero defect and redundant row replacement defectiveness is capable.
Step 5, row control signal 32 and switch gating signal 33 exported after logical circuit 34 information storage circuit 38 that row switch selection signal (gating signal) answers to the row Switch Controller selected, remove selected first phase-change material 35 and second phase-change material 36 that wherein will write data.
In this step, the row control signal 32 that logical circuit 34 inputs when receiving test and switch selection signal 33, to every a line, select an information storage circuit 38 of answering with the capable row Switch Controller that be connected, same sequence number of zero defect, export row switch selection signal to the information storage circuit 38 selected, remove selected first phase-change material 35 and second phase-change material 36 that wherein will write data.
Such as: the SW supposing the 1st row in Fig. 2
1the row defectiveness of <0>, have selected the SW be connected with WL<0>-WL<m-1Grea tT.GreaT.GT in this step
0<1>, SW
1<1> ... .SW
m-1<1>.
The first switch S 31 in each information storage circuit 38 that step 6, test procedure control conducting is selected and the 3rd switch S 33, turn off second switch S32, by write circuit 31 to the first phase-change material 35 one writing.
The principle of this step is identical with above-mentioned steps 2, and the data only write are not " 0 " but " 1 ".
Step 7, test procedure control the second switch S32 in each information storage circuit 38 of conducting selection, turn off the 3rd switch S 33, are write " 0 " by write circuit 31 to the second phase-change material 36.
The principle of this step is identical with above-mentioned steps 3, and the data only write are not " 1 " but " 0 ".
Now, phase-change material 35 is low resistance, and phase-change material 36 is high value.
Step 8, the first switch S 31, second switch S32 and the 3rd switch S 33 turned off in each information storage circuit 38 of selection.
Here, by writing " 0 " to phase-change material 35 one writing with to phase-change material 36, the information that corresponding line switch has been switched on is stored in phase-change material 35 and phase-change material 36 li.Like this when system worked well, corresponding line switch is just in the state of conducting.
Have passed through above-mentioned steps 5-8, achieve capable with zero defect and that redundant row replacement defectiveness is capable function.
Second preferred embodiment
The present embodiment is that the mode by increasing redundant columns realizes, the phase transition storage of the present embodiment and the phase change memory something in common of prior art are all have write circuit, storage array and Q redundant columns, difference is also to comprise, multiple information storage circuit and a row switch selection circuit.
Q redundant columns in the present embodiment and the storage line continuous arrangement of storage array.Each row control line of storage array is connected with Q+1 row switch.Wherein, the 1st row switch series is associated on column control line, and one end of the 2 to the Q+1 row switch is connected to column control line, and the other end is connected on lower 1 to the Q row control line of column successively.Wherein, each row Switch Controller should connect an information storage circuit.Row switch selection circuit is connected with all information storage circuits, and all information storage circuits are connected with write circuit again.
When testing out that storage array is a certain shows defect, first by row switch selection circuit, for all row after defectiveness row and defectiveness row, select the information storage circuit that current closed row Switch Controller is answered, by write circuit memory row switch OFF information in the information storage circuit selected, and described information storage circuit output switch control signal, turn off corresponding row switch; Again by row switch selection circuit, for all row after defectiveness row and defectiveness row, one is selected to arrange with zero defect the information storage circuit that row Switch Controller that be connected, same sequence number answers, by write circuit memory row switch conduction information in the information storage circuit selected, and described information storage circuit output switch control signal, the row switch that conducting is corresponding.
Fig. 5 shows the annexation of row switch and storage array and redundant columns in the phase transition storage of the present embodiment, and the row switch in Fig. 5 is in default conditions.
As shown in Figure 5, the storage array of the present embodiment phase transition storage has m storage line, a n memory row 21, altogether m*n phase-change memory cell 20.This phase transition storage has 3 redundant columns 22, and continuous arrangement is after n memory row 21.
In Fig. 5, the row control line BL<i> of each memory row is all connected with 4 row interrupteur SW _ B
i<j>, wherein i is from 0 to 3 from 0 to n-1, j.As: the row control line BL<0> of the 0th memory row is connected to SW_B
0<0>-SW_B
0<3> is totally 4 row switches; , the control line BL<n-1> of the (n-1)th row is connected to SW_B
n-1<0>-SW_B
n-1<3>.Wherein, 3 row of below these row and this row received respectively by 4 row switches of each memory row, namely the 0th row switch series is associated on column control line, and one end of the 1 to the 3 row switch is connected to column control line, and the other end is connected on lower 1 to the 3 row control lines of column successively.Redundant columns, as the spare columns of memory row, is connected with corresponding row switch in an identical manner, e.g., and row interrupteur SW _ B
n-2<0>-SW_B
n-2<3> will receive the (n-1)th row and two redundant columns (being designated as the redundancy example of 0 and 1 in figure) of below the n-th-2 row and these row respectively; Row interrupteur SW _ B
n-1<0>-SW_B
n-1<3> will receive 3 redundant columns of below the (n-1)th row and this row respectively.
Fig. 5 shows the default conditions of row switch, is specially the SW_B<0> of each memory row ... SW_B
n-1<0> conducting, SW_B
0<1>-SW_B
0<3> ..., SW_B
n-1<1>-SW_B
n-1<3> turns off.Now each row control signal BL<0> ... BL<n-1> removes the corresponding row that draw oneself up.Be more than arrange for 3 redundancies, if hypothesis has h redundant columns (h≤n), each row control signal is connected to g switch, then g need meet g=h+1.
Find that there is a certain listing when tested to stagger the time, be assumed to be in memory row 21 the 1st row (in Fig. 5 for digital 1 place memory row (in the application's text, row counting from the 0th row start) make mistakes, needs replace.
As shown in Figure 6, now the SW_B of the 1st row
1<0> disconnects, SW_B
1<1> closes.And the SW_B of following all row
2<0> ... SW_B
n-1<0> disconnects, SW_B
2<1> ... SW_B
n-1<1> closes.That is, arranged by the 2nd row replacement the 1st, the 3rd row replacement the 2nd arranges, and by that analogy, is finally arranged by the 0th row replacement (n-1)th of redundant columns 22.
In the present embodiment, the structure of information storage circuit and identical with the annexation of logical circuit with write circuit, difference is only that the control signal that each information storage circuit exports is used for controlling connected row switch.Its concrete principle of work is also identical, here no longer repeat specification.
From the above embodiments, when the present invention finding defective row or column when testing, the information of these row or column being directly stored in phase-change material, these information can also being preserved when power-off like this.Controlled the break-make of respective switch when normal work by the information read in phase-change material, in circuit, directly replace defective row or column by corresponding redundancy row or column.Compare with regard to not needing all to carry out address at every turn when read-write like this, improve read or write speed, and eliminate comparator circuit.
Claims (9)
1. there is a phase transition storage for redundant circuit, comprise write circuit, a storage array and P redundant row or Q redundant columns, it is characterized in that: also comprise multiple information storage circuit, row or column switch selection circuit;
A described P redundant row or Q redundant columns continuous arrangement are after the row or column of storage array;
Every a line control line of described storage array is connected with P+1 row switch or each row control line is connected with Q+1 row switch; Wherein, the 1st row switch or row switch series are associated on the row or column control line of place; One end of 2 to the P+1 row switch or the 2 to the Q+1 row switch is connected to place row or column control line, and the other end is connected on lower 1 to P capable or 1 to the Q row control line of place row or column successively;
Each row switch described or each row Switch Controller should connect an information storage circuit; Described row or column switch selection circuit is connected with all information storage circuits; Described all information storage circuits are connected with write circuit;
When testing out a certain row or column defectiveness of storage array, first by row or column switch selection circuit, for all row or column after defectiveness row or column and defectiveness row or column, select the information storage circuit that current closed row switch or row Switch Controller are answered, in the information storage circuit selected, row or column switch OFF information is stored by write circuit, and described information storage circuit output switch control signal, turn off corresponding row switch or row switch; Again by row or column switch selection circuit, for all row or column after defectiveness row or column and defectiveness row or column, select the information storage circuit that a row switch that be connected with zero defect row or column, same sequence number or row Switch Controller are answered, in the information storage circuit selected, row or column switch conduction information is stored by write circuit, and described information storage circuit output switch control signal, the row switch that conducting is corresponding or row switch; Wherein,
Described information storage circuit comprises: three switches, two phase-change materials, PMOS, NMOS tube and phase inverters; The first end of the first switch in described three switches is connected with write circuit, and the second end is connected with the first end of the first phase-change material; The first end of the first phase-change material is also connected with the drain electrode of PMOS, and its second end is connected with the first end of the second phase-change material, and connecting valve control signal wire; The source electrode of PMOS is connected with power supply; Second end of the second phase-change material is connected with the drain electrode of NMOS tube; The source ground of NMOS tube; Second switch in described three switches is in parallel with the first phase-change material; The 3rd switch in described three switches is connected between switch controlling signal line and ground;
The row or column switch selection signal that described row or column switch selection circuit exports outputs to the first end of phase inverter and the grid of NMOS tube, and the second end of phase inverter is connected to the grid of PMOS.
2. phase transition storage as claimed in claim 1, is characterized in that: described information storage circuit is nonvolatile memory; It, by the row or column switch conduction of storage or the information of shutoff, exports to coupled row switch or row switch as control signal.
3. phase transition storage as claimed in claim 1, it is characterized in that: described row or column switch selection circuit is realized by logical circuit, its row or column control signal inputted when receiving test and switch selection signal, export the information storage circuit that row or column switch selection signal is answered to the row switch selected or row Switch Controller.
4. phase transition storage as claimed in claim 3, is characterized in that: described logical circuit is decoding scheme.
5. the phase transition storage as described in any one of claim 1-4, is characterized in that: described row switch or row switch are the switch with control end; Each row switch in described row switch or row switch or the control end of the row switch information storage circuit corresponding with it are connected.
6. phase transition storage realizes a method for redundancy, it is characterized in that: adopt phase transition storage according to claim 1; When testing out a certain row or column defectiveness of storage array, perform following steps:
A, by row or column switch selection circuit, for all row or column after defectiveness row or column and defectiveness row or column, select the information storage circuit that current closed row switch or row Switch Controller are answered, in the information storage circuit selected, row or column switch OFF information is stored by write circuit, and described information storage circuit output switch control signal, turn off corresponding row switch or row switch;
B, by row or column switch selection circuit, for all row or column after defectiveness row or column and defectiveness row or column, select the information storage circuit that a row switch that be connected with zero defect row or column, same sequence number or row Switch Controller are answered, in the information storage circuit selected, row or column switch conduction information is stored by write circuit, and described information storage circuit output switch control signal, the row switch that conducting is corresponding or row switch.
7. method as claimed in claim 6, it is characterized in that: described row or column switch selection circuit is realized by logical circuit, its row or column control signal inputted when receiving test and switch selection signal, export the information storage circuit that row or column switch selection signal is answered to the row switch selected or row Switch Controller.
8. method as claimed in claim 7, is characterized in that: described steps A comprises:
The row or column control signal that A1, logical circuit input when receiving test and switch selection signal, for all row or column after defectiveness row or column and defectiveness row or column, select the information storage circuit that current closed row switch or row Switch Controller are answered, export two-way row or column switch selection signal to the information storage circuit selected;
The first switch in each information storage circuit that A2, conducting are selected and the 3rd switch, turn off second switch, write 0 by write circuit to the first phase-change material;
Second switch in each information storage circuit that A3, conducting are selected, turns off the 3rd switch, writes 1 by write circuit to the second phase-change material;
A4, first, second, third switch turned off in each information storage circuit of selection, switch controlling signal line exports cut-off signals to corresponding row switch or row switch, turns off row switch or the row switch of correspondence.
9. method as claimed in claim 8, is characterized in that: described step B comprises:
B1, logical circuit receive row or column control signal and the switch selection signal of input, for all row or column after defectiveness row or column and defectiveness row or column, select the information storage circuit that a row switch that be connected with zero defect row or column, same sequence number or row Switch Controller are answered, export two-way row or column switch selection signal to the information storage circuit selected;
The first switch in each information storage circuit that B2, conducting are selected and the 3rd switch, turn off second switch, write 1 by write circuit to the first phase-change material;
Second switch in each information storage circuit that B3, conducting are selected, turns off the 3rd switch, writes 0 by write circuit to the second phase-change material;
B4, first, second, third switch turned off in each information storage circuit of selection, switch controlling signal line exports Continuity signal to corresponding row switch or row switch, the row switch that conducting is corresponding or row switch.
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| CN201210036652.1A CN102543171B (en) | 2012-02-17 | 2012-02-17 | Phase change memory with redundant circuit and redundancy method for phase change memory |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110265074A (en) * | 2018-03-12 | 2019-09-20 | 上海磁宇信息科技有限公司 | A kind of magnetic RAM and its operation method of stratification multiple redundancy |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105678003A (en) * | 2016-01-15 | 2016-06-15 | 中山芯达电子科技有限公司 | Redundancy device set used for error correction and modification and method for repairing circuit defect with redundancy device set |
| US9953728B2 (en) | 2016-07-21 | 2018-04-24 | Hewlett Packard Enterprise Development Lp | Redundant column or row in resistive random access memory |
| CN114428452B (en) * | 2022-04-06 | 2022-07-15 | 成都凯天电子股份有限公司 | Dual-redundancy control device of position detection and retraction control equipment and control method thereof |
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| CN1137677A (en) * | 1995-06-07 | 1996-12-11 | 三菱电机株式会社 | Memory circuit, data control circuit of memory circuit and address assigning circuit of memory circuit |
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| CN110265074B (en) * | 2018-03-12 | 2021-03-30 | 上海磁宇信息科技有限公司 | Hierarchical multiple redundancy magnetic random access memory and operation method thereof |
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