CN102540047A - Assessment method for test coverage - Google Patents
Assessment method for test coverage Download PDFInfo
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- CN102540047A CN102540047A CN201010587166XA CN201010587166A CN102540047A CN 102540047 A CN102540047 A CN 102540047A CN 201010587166X A CN201010587166X A CN 201010587166XA CN 201010587166 A CN201010587166 A CN 201010587166A CN 102540047 A CN102540047 A CN 102540047A
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Abstract
The invention discloses an assessment method for test coverage. The assessment method comprises following steps: S1, assessing the coverage of a tested object in a testable stage; S2, assessing the coverage of the tested object in a fixture manufacturing stage; and S3, assessing the coverage of the tested object in a final testing stage. The assessment method has the advantages that the test coverage of the testable stage, the test coverage of the fixture manufacturing stage and the test coverage of the final testing stage are respectively obtained via the S1, the S2 and the S3, testing programs applied onto an online testing machine are simplified, and a fixture manufacturing period is shortened.
Description
Technical field
The present invention relates to a kind of appraisal procedure of test coverage, belong to integrated circuit board electrodes production test field.
Background technology
Dwindling day by day of process and improving constantly of circuit complexity along with integrated circuit; SOC(system on a chip) (System-on-Chip particularly; SoC) appearance and widespread use, the integrated level of VLSI (very large scale integrated circuits) have developed into can the above degree of integrated several ten million transistors on the chip.So exploring and use low cost, high efficiency measuring technology and test macro has become an important topic in the chip testing.
On-line testing machine test (ICT Test) is widely used in electronics manufacturing enterprise, and its effect mainly is through anchor clamps, is interface with the test point on the circuit board (PCB), and the electronic devices and components that are installed on the circuit board are carried out electric test.The advantage of on-line testing machine test is that speed is fast, covers comprehensively.The shortcoming of on-line testing machine test is that test machine, anchor clamps and testing cost are too expensive.Because this test machine is to be used as interface to the point of the physical testing on the circuit board, test procedure and corresponding anchor clamps through special making generate test and excitation.Yet along with board design must become increasingly complex, components and parts are more and more, and pin is more and more closeer, make that the test procedure and the anchor clamps fabrication cycle that are applied on the on-line testing machine are more and more longer, and complexity is increasingly high.
Therefore, be necessary the appraisal procedure of existing test coverage is improved.
Summary of the invention
Technical matters to be solved by this invention is to provide the appraisal procedure of test coverage a kind of simplification, stage by stage.
For solving the problems of the technologies described above; The present invention adopts following technical scheme: a kind of appraisal procedure of test coverage; This appraisal procedure is in order to test the coverage rate of object to be tested; Said object to be tested comprises components and parts and to pin that should components and parts, said components and parts comprise digital device and analog device, and said appraisal procedure comprises the steps:
Step S1 in the testability stage, assesses the coverage rate of object to be tested; Wherein, step S1 comprises step S11, promptly; Components and parts storehouse to components and parts is analyzed, if the pin of corresponding element device by assignment, this pin is considered to be tested covering so;
Step S2 in the anchor clamps fabrication phase, assesses the coverage rate of object to be tested, and wherein, step S2 comprises step S21 and step S22, and pin only all is covered in step S21 and step S22, and this pin just is considered to be tested covering so;
Step S21 analyzes the components and parts storehouse of components and parts, if the pin of corresponding element device by assignment, this pin tentatively is considered to be tested covering so;
Step S22; Domain examining report to object to be tested is analyzed; If pin has test point, this pin tentatively is considered to be tested covering so, if this pin does not have test point; But this pin is on the connection netting twine of a plurality of boundary scanning devices, and this pin tentatively is considered to be tested covering so; And
Step S3 in the final test stage, assesses the coverage rate of object to be tested, and wherein, step S3 comprises: step S31, carry out the test coverage assessment to the pin of corresponding digital device; Step S32 assesses the stability of analog device; And step S33, the existence of components and parts is assessed.
As further improvement of the present invention, this appraisal procedure also comprised the step of initial value before step S1, and wherein, the pin that connects power supply or ground connection is immesurable, and the pin that connects 5 above shunt capacitances also is immesurable.
As further improvement of the present invention, object to be tested comprises some netting twines, and among the step S2, these netting twines all can be connected to by anchor clamps.
As further improvement of the present invention, among the step S31, if digital device is boundary scanning device and is covered by boundary scan testing that then the pin of corresponding digital device is considered to be tested covering.
As further improvement of the present invention, among the step S31, if digital device is a non-boundary scanning device, when then pin that should non-boundary scanning device being satisfied stuck at 0 fault and stuck at 1 fault, this pin just is considered to be tested covering.
As further improvement of the present invention, among the step S32, repeatedly the test the result calculate, obtain the value of standard deviation and processing procedure ability, if the value of processing procedure ability greater than 20, this analog device is considered to unsettled so.
As further improvement of the present invention, said standard deviation calculation formulas is:
Wherein,
XBe test value;
nBe testing time.
As further improvement of the present invention, the computing formula of said processing procedure ability is:
Wherein, μ is a testing mean;
USLThe tolerance value upper limit for this device;
LSLTolerance value lower limit for this device.
As further improvement of the present invention, among the step S33, the existence coverage rate of components and parts adopts following rule:
If these components and parts are electric capacity, have at least a capacity measurement or serial capacity measurement to cover all pins;
If these components and parts are connectors, has to be tested arriving of pin at least;
If these components and parts are diodes, two pins all need be covered by the diode test;
If these components and parts are inductance, two pins are covered by a wire jumper test or inductance measurement at least;
If these components and parts are jumper wire devices, two pins are covered by a wire jumper test at least;
If these components and parts are resistance, have at least the test of a resistance test or serial resistor to cover all pins.
As further improvement of the present invention, among the step S33, the existence coverage rate of components and parts adopts following rule:
If these components and parts are triodes, have at least a triode test to cover all pins;
If these components and parts are light emitting diodes, have at least a diode test or led color test to cover all pins;
If these components and parts are oscillators, have at least a simulation power supply test to cover and detect correct frequency;
If these components and parts are digital devices, have at least be fixed 0 fault and stuck at 1 fault of a pin to test;
If these components and parts are simulation power supply devices, has to be tested arriving of pin at least.
Compared to prior art; The present invention can obtain the test coverage in testability stage, anchor clamps fabrication phase and final test stage through step S1, step S2 and step S3 respectively, has simplified the test procedure that is applied on the on-line testing machine, the cycle that has shortened the anchor clamps making.
Description of drawings
Fig. 1 is the process flow diagram of the appraisal procedure of test coverage of the present invention.
Embodiment
The present invention has disclosed a kind of appraisal procedure of test coverage, in order to test the coverage rate of object to be tested.In this embodiment, said object to be tested is a circuit board, and it comprises the number of pins of some components and parts and corresponding these components and parts.Said components and parts comprise digital device and analog device.Please join shown in Figure 1ly, the appraisal procedure of test coverage of the present invention comprises the steps:
Step S1 in the testability stage, assesses the coverage rate of object to be tested, and wherein, step S1 comprises:
Step S11 analyzes the components and parts storehouse of components and parts, if the pin of corresponding element device by assignment, this pin is considered to be tested covering so;
Step S2 in the anchor clamps fabrication phase, assesses the coverage rate of object to be tested, and wherein, step S2 comprises step S21 and step S22, and pin only all is covered in step S21 and step S22, and this pin just is considered to be tested covering so;
Step S21 analyzes the components and parts storehouse of components and parts, if the pin of corresponding element device by assignment, this pin tentatively is considered to be tested covering so;
Step S22; Domain examining report to object to be tested is analyzed; If pin has test point, this pin tentatively is considered to be tested covering so, if this pin does not have test point; But this pin is on the connection netting twine of a plurality of boundary scanning devices, and this pin tentatively is considered to be tested covering so; And
Step S3 in the final test stage, assesses the coverage rate of object to be tested, and wherein, step S3 comprises:
Step S31 carries out the test coverage assessment to the pin of corresponding digital device;
Step S32 assesses the stability of analog device; And
Step S33 assesses the existence of components and parts.
The appraisal procedure of test coverage of the present invention also comprised the step of initial value before step S1, wherein, the pin that connects power supply or ground connection is immesurable, and the pin that connects 5 above shunt capacitances also is immesurable.
Object to be tested comprises some netting twines, and among the step S2, these netting twines all can be connected to by anchor clamps.
Among the step S21, be example with Agilent 3070 on-line testing machines:
capacitor?*,?1000p,?10,?10,?f
external?pins?1
device?*?pins?1
external?pins?2
device?*?pins?2
Then the pin 1,2 of these components and parts is to be tested covering.
Among the step S31, if digital device is boundary scanning device and is covered by boundary scan testing that then the pin of corresponding digital device is considered to be tested covering.Said pin is the TAP pin, and perhaps direct connection perhaps is BusWire, perhaps is SiliconNai.Need explanation be:, must satisfy these pins by interconnected a test, and the pin that links to each other to be on same netting twine if when being connected on the serial resistor to pin that should boundary scanning device; If then, but on two silicon nodes, have only these pins to be covered to so, and resistance is not covered to by an interconnected test to pin that should boundary scanning device.
Among the step S31, if digital device is a non-boundary scanning device, when then pin that should non-boundary scanning device being satisfied stuck at 0 fault (Stuck-At-0) and stuck at 1 fault (Stuck-At-1), this pin just is considered to be tested covering.
Among the step S32, calculate the result of repeatedly test, obtain the value of standard deviation (Standard Deviation) and processing procedure ability (Cpk).In this embodiment, if the value of processing procedure ability greater than 20, this analog device is considered to unsettled so, need be resurveyed or replace.
Standard deviation calculation formulas is:
Wherein,
XBe test value;
nBe testing time.
The computing formula of processing procedure ability is:
Wherein, μ is a testing mean;
USLThe tolerance value upper limit for this device;
LSLTolerance value lower limit for this device.
Among the step S33, the existence coverage rate of components and parts adopts following rule:
If these components and parts are electric capacity, have at least a capacity measurement or serial capacity measurement to cover all pins, do not comprise shunt capacitance;
If these components and parts are connectors, has to be tested arriving of pin at least;
If these components and parts are diodes, two pins all need be covered by the diode test;
If these components and parts are inductance, two pins are covered by a wire jumper test or inductance measurement at least;
If these components and parts are jumper wire devices, two pins are covered by a wire jumper test at least;
If these components and parts are resistance, have at least the test of a resistance test or serial resistor to cover all pins;
If these components and parts are triodes, have at least a triode test to cover all pins;
If these components and parts are light emitting diodes, have at least a diode test or led color test to cover all pins;
If these components and parts are oscillators, have at least a simulation power supply test to cover and detect correct frequency;
If these components and parts are digital devices, have at least be fixed 0 fault and stuck at 1 fault of a pin to test;
If these components and parts are simulation power supply devices, has to be tested arriving of pin at least.
Compared to prior art; The appraisal procedure of test coverage of the present invention can obtain the test coverage in testability stage, anchor clamps fabrication phase and final test stage through step S1, step S2 and step S3 respectively, has simplified the test procedure that is applied on the on-line testing machine, the cycle that has shortened the anchor clamps making.In addition, because this test coverage can reflect the defective of object to be tested, the tester can make corresponding adjustment according to this test coverage, when finally doing the on-line testing of plate level, obtains maximum coverage rate to reach, and reduces the purpose of risk.
In sum; More than be merely preferred embodiment of the present invention; Should not limit scope of the present invention with this, promptly every simple equivalent of being done according to claims of the present invention and description of the invention content changes and modifies, and all should still belong in the scope that patent of the present invention contains.
Claims (10)
1. the appraisal procedure of a test coverage; It is characterized in that this appraisal procedure is in order to testing the coverage rate of object to be tested, said object to be tested comprises components and parts and to pin that should components and parts; Said components and parts comprise digital device and analog device, and said appraisal procedure comprises the steps:
Step S1 in the testability stage, assesses the coverage rate of object to be tested, and wherein, step S1 comprises:
Step S11 analyzes the components and parts storehouse of components and parts, if the pin of corresponding element device by assignment, this pin is considered to be tested covering so;
Step S2 in the anchor clamps fabrication phase, assesses the coverage rate of object to be tested, and wherein, step S2 comprises step S21 and step S22, and pin only all is covered in step S21 and step S22, and this pin just is considered to be tested covering so;
Step S21 analyzes the components and parts storehouse of components and parts, if the pin of corresponding element device by assignment, this pin tentatively is considered to be tested covering so;
Step S22; Domain examining report to object to be tested is analyzed; If pin has test point, this pin tentatively is considered to be tested covering so, if this pin does not have test point; But this pin is on the connection netting twine of a plurality of boundary scanning devices, and this pin tentatively is considered to be tested covering so; And
Step S3 in the final test stage, assesses the coverage rate of object to be tested, and wherein, step S3 comprises:
Step S31 carries out the test coverage assessment to the pin of corresponding digital device;
Step S32 assesses the stability of analog device; And
Step S33 assesses the existence of components and parts.
2. appraisal procedure as claimed in claim 1 is characterized in that: this appraisal procedure also comprised the step of initial value before step S1, and wherein, the pin that connects power supply or ground connection is immesurable, and the pin that connects 5 above shunt capacitances also is immesurable.
3. appraisal procedure as claimed in claim 1 is characterized in that: object to be tested comprises some netting twines, and among the step S2, these netting twines all can be connected to by anchor clamps.
4. appraisal procedure as claimed in claim 1 is characterized in that: among the step S31, if digital device is boundary scanning device and is covered by boundary scan testing that then the pin of corresponding digital device is considered to be tested covering.
5. appraisal procedure as claimed in claim 1; It is characterized in that: among the step S31; If digital device is a non-boundary scanning device, when then pin that should non-boundary scanning device being satisfied stuck at 0 fault and stuck at 1 fault, this pin just is considered to be tested covering.
6. appraisal procedure as claimed in claim 1 is characterized in that: among the step S32, repeatedly the test the result calculate, obtain the value of standard deviation and processing procedure ability, if the value of processing procedure ability greater than 20, this analog device is considered to unsettled so.
7. appraisal procedure as claimed in claim 6 is characterized in that: said standard deviation calculation formulas is:
8. appraisal procedure as claimed in claim 6 is characterized in that: the computing formula of said processing procedure ability is:
Wherein, μ is a testing mean;
USLThe tolerance value upper limit for this analog device;
LSLTolerance value lower limit for this analog device.
9. appraisal procedure as claimed in claim 1 is characterized in that: among the step S33, the existence coverage rate of components and parts adopts following rule:
If these components and parts are electric capacity, have at least a capacity measurement or serial capacity measurement to cover all pins;
If these components and parts are connectors, has to be tested arriving of pin at least;
If these components and parts are diodes, two pins all need be covered by the diode test;
If these components and parts are inductance, two pins are covered by a wire jumper test or inductance measurement at least;
If these components and parts are jumper wire devices, two pins are covered by a wire jumper test at least;
If these components and parts are resistance, have at least the test of a resistance test or serial resistor to cover all pins.
10. appraisal procedure as claimed in claim 1 is characterized in that: among the step S33, the existence coverage rate of components and parts adopts following rule:
If these components and parts are triodes, have at least a triode test to cover all pins;
If these components and parts are light emitting diodes, have at least a diode test or led color test to cover all pins;
If these components and parts are oscillators, have at least a simulation power supply test to cover and detect correct frequency;
If these components and parts are digital devices, have at least be fixed 0 fault and stuck at 1 fault of a pin to test;
If these components and parts are simulation power supply devices, has to be tested arriving of pin at least.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108627755A (en) * | 2017-03-22 | 2018-10-09 | 株洲中车时代电气股份有限公司 | A kind of circuit board overall process test coverage analysis method |
| CN108627716A (en) * | 2017-03-22 | 2018-10-09 | 株洲中车时代电气股份有限公司 | A kind of current transformer complete machine overall process detection coverage ratio analysis method |
| CN112131826A (en) * | 2020-08-28 | 2020-12-25 | 上海望友信息科技有限公司 | PCB detection and evaluation method, evaluation device, electronic equipment and storage medium |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108627755A (en) * | 2017-03-22 | 2018-10-09 | 株洲中车时代电气股份有限公司 | A kind of circuit board overall process test coverage analysis method |
| CN108627716A (en) * | 2017-03-22 | 2018-10-09 | 株洲中车时代电气股份有限公司 | A kind of current transformer complete machine overall process detection coverage ratio analysis method |
| CN108627716B (en) * | 2017-03-22 | 2021-08-31 | 株洲中车时代电气股份有限公司 | Method for analyzing detection coverage rate of whole process of converter |
| CN112131826A (en) * | 2020-08-28 | 2020-12-25 | 上海望友信息科技有限公司 | PCB detection and evaluation method, evaluation device, electronic equipment and storage medium |
| CN112131826B (en) * | 2020-08-28 | 2023-08-15 | 上海望友信息科技有限公司 | PCB detection evaluation method, evaluation device, electronic equipment and storage medium |
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Effective date of registration: 20160201 Address after: Xinghan street Suzhou Industrial Park in Suzhou city in Jiangsu province 215021 B No. 5 Building 4 floor 13/16 unit Patentee after: Centec Networks (Suzhou) Inc. Address before: Xinghan street Suzhou Industrial Park in Suzhou city in Jiangsu province 215000 B No. 5 Building 4 Building 16 unit Patentee before: Suzhou Industrial Park ICP Technologies Co., Ltd. |
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Address after: 215000 unit 13 / 16, 4th floor, building B, No.5 Xinghan street, Suzhou Industrial Park, Jiangsu Province Patentee after: Suzhou Shengke Communication Co.,Ltd. Address before: 215021 unit 13 / 16, floor 4, building B, No. 5, Xinghan street, Suzhou Industrial Park, Suzhou, Jiangsu Patentee before: CENTEC NETWORKS (SU ZHOU) Co.,Ltd. |