CN102509718B - Wafer-level chip size encapsulation technology for GaAs (gallium arsenide) CCD (Charge Coupled Device) image sensor - Google Patents
Wafer-level chip size encapsulation technology for GaAs (gallium arsenide) CCD (Charge Coupled Device) image sensor Download PDFInfo
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- CN102509718B CN102509718B CN201110419761.7A CN201110419761A CN102509718B CN 102509718 B CN102509718 B CN 102509718B CN 201110419761 A CN201110419761 A CN 201110419761A CN 102509718 B CN102509718 B CN 102509718B
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- 229910001218 Gallium arsenide Inorganic materials 0.000 title claims abstract description 28
- 238000005516 engineering process Methods 0.000 title claims abstract description 25
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 title abstract description 25
- 238000005538 encapsulation Methods 0.000 title abstract description 12
- 238000002161 passivation Methods 0.000 claims abstract description 17
- 239000011521 glass Substances 0.000 claims abstract description 15
- 229920005989 resin Polymers 0.000 claims abstract description 13
- 239000011347 resin Substances 0.000 claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 claims abstract description 10
- 238000001312 dry etching Methods 0.000 claims abstract description 5
- 229910052751 metal Inorganic materials 0.000 claims abstract description 5
- 239000002184 metal Substances 0.000 claims abstract description 5
- 238000005260 corrosion Methods 0.000 claims abstract description 4
- 230000007797 corrosion Effects 0.000 claims abstract description 4
- 239000000853 adhesive Substances 0.000 claims abstract description 3
- 230000001070 adhesive effect Effects 0.000 claims abstract description 3
- 238000000053 physical method Methods 0.000 claims abstract description 3
- 238000004544 sputter deposition Methods 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims description 57
- 238000005530 etching Methods 0.000 claims description 18
- 238000001465 metallisation Methods 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 13
- 238000004806 packaging method and process Methods 0.000 claims description 10
- 230000004888 barrier function Effects 0.000 claims description 9
- 239000007767 bonding agent Substances 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 7
- 238000007747 plating Methods 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 238000001259 photo etching Methods 0.000 claims description 5
- 238000001020 plasma etching Methods 0.000 claims description 5
- 238000005520 cutting process Methods 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 4
- 239000003292 glue Substances 0.000 claims description 4
- 239000007788 liquid Substances 0.000 claims description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims description 4
- 238000004528 spin coating Methods 0.000 claims description 4
- 238000009826 distribution Methods 0.000 claims description 3
- 238000012546 transfer Methods 0.000 claims description 3
- 241000826860 Trapezium Species 0.000 claims description 2
- 239000003518 caustics Substances 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 239000003822 epoxy resin Substances 0.000 claims description 2
- 238000001459 lithography Methods 0.000 claims description 2
- 229920000647 polyepoxide Polymers 0.000 claims description 2
- 238000010992 reflux Methods 0.000 claims description 2
- 238000007711 solidification Methods 0.000 claims description 2
- 230000008023 solidification Effects 0.000 claims description 2
- 238000009713 electroplating Methods 0.000 abstract description 3
- 230000008054 signal transmission Effects 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000002955 isolation Methods 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000009616 inductively coupled plasma Methods 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 2
- 230000001953 sensory effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 208000015181 infectious disease Diseases 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000011031 large-scale manufacturing process Methods 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
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Abstract
The invention relates to a wafer-level chip size encapsulation technology for a GaAs (gallium arsenide) CCD (Charge Coupled Device) image sensor. The technology is characterized by comprising the following steps of: (1) firstly bonding a glass wafer and a GaAs wafer through a resin adhesive so as to protect the active surface of a chip and improve the strength of a chip wafer; (2) manufacturing a trapezoidal-slot structure by a wet corrosion or physical method so as to reduce the lining thickness of a chip interconnection area; (3) manufacturing vertical interconnected through holes by a dry etching technology so as to expose a pad on the active surface of the chip; (4) sputtering seed-layer metal and electroplating, and manufacturing a hole metalizing and RDL layer to realize circuit interconnection from the active surface to the back surface of the chip; (5) manufacturing a passivation layer, a UBM layer and raised points; and (6) finally scribing to form an independent encapsulation chip. As the trapezoidal-slot structure on the back realizes thickness reduction only in the area with the pad, the cost is effectively lowered; and through the interconnection of the vertical through holes, the encapsulation interconnection density can be improved, and the signal transmission path is shortened.
Description
Technical field
The present invention relates to GaAs CCD graphical sensory device Wafer-level Chip Scale Package technique and structure, relate to or rather a kind of GaAs ccd image sensor Wafer-level Chip Scale Package technique that adopts trapezoid groove structure and vertical through hole interconnection technique to realize, GaAs ccd image sensor is MEMS (MicroElectroMechanical System, microelectromechanical systems) senser element, therefore belongs to MEMS device package field.
Background technology
MEMS refers to and adopts Micrometer-Nanometer Processing Technology to make, integrates the system of microsensor, micro parts, miniature actuator, signal processing, control circuit etc.MEMS device has very wide application prospect in a lot of fields, and wherein imageing sensor is particularly extensive as a kind of its application of MEMS device.Imageing sensor pixel structure is very easily subject to polluting and its performance of destroying infection, and Wafer-level Chip Scale Package can get up fragile pixel structural defence in the encapsulation incipient stage, was conducive to improve the reliability and stability of encapsulation.In addition, Wafer-level Chip Scale Package was considered encapsulation problem ，Yu Qian road process compatible before scribing, thereby can improve packaging density, reduces costs.Therefore, Wafer-level Chip Scale Package is the development inexorable trend of MEMS encapsulation technology.
Gallium arsenide semiconductor material is one of conventional compound semiconductor, and comparing its advantage with silicon has that saturated electrons mobility is high, noise is little, breakdown voltage is high, therefore than silicon, is more suitable for high-frequency high-power occasion, as microwave, mobile communication, radar system etc.; GaAs is that direct band gap material and switch speed are fast, so photoelectric properties are superior, and ccd image sensor is one of its application; In addition, gallium arsenide substrate does not need the isolation of insulating, the isolation technology that this is complicated for encapsulating structure saves.Yet compare with silicon materials, the silicon base CMOS technique of GaAs technology and large-scale production is difficult to compatibility, this more GaAs ccd image sensor Wafer-level Chip Scale Package challenge has been proposed.
Vertical through hole interconnection technique is one of reliable selection realizing in wafer level packaging imageing sensor Wafer-level Chip Scale Package, in silica-based image sensor package technology, is widely used.The effects such as the interconnection mode that this electrical interconnection is more traditional is as short in the advantage of Bonding is to be electrically connected to distance, and interconnection density is high, parasitic, to crosstalk are little, can realize in addition the 3 D stereo encapsulation of device.
As shown in Figures 1 and 2, in traditional silicon based image sensor Wafer-level Chip Scale Package interconnection technique, perpendicular interconnection through hole technology and T shape interconnection technique are modal two kinds of packaging interconnection technology.Two kinds of interconnection techniques all have multiple version, and respectively have pluses and minuses.
As shown in Figure 1, in image device packaging technology and structure that the people such as Kazumasa Tanida propose at document US2010/0252902, what use is vertical through hole interconnection technique, and the common processing step of perpendicular interconnection through hole technology is glass wafer/Silicon Wafer bonding, Silicon Wafer attenuate, through hole making, via metal, RDL layer and stud bump making, scribing etc.Be characterized in image sensor substrate directly making perpendicular interconnection through hole, the method for making through hole is generally plasma etch process, shortcoming be the method for GaAs substrate, technology difficulty is very big; And high temperature and high-octane plasma process have been used in the via process of making high-aspect-ratio.
As shown in Figure 2, the people such as Badehi have proposed T-shaped interconnection technique at document WO99/40624, and the common processing step of T-shaped interconnection technique is: glass wafer/Silicon Wafer bonding, Silicon Wafer attenuate, dovetail groove etching, glass wafer/Silicon Wafer bonding, dovetail groove etching, RDL layer and salient point, scribing.The feature of this structure is " sandwich " structure that adopts glass-chip-glass.Be characterized in adopting and extend pad at imageing sensor side making dovetail groove, thereby form T-shaped connection, dovetail groove can adopt machining process or plasma etch process, and shortcoming is that process costs is high, and reliability and interconnection density are lower.
Summary of the invention
In order to reduce packaging cost, improve packaging density, and for imageing sensor provides reliable protection, the present invention considers that the feature of GaAs material combines perpendicular interconnection through hole technology and trapezoid groove structure.Avoided the shortcomings such as vertical through hole interconnection technique technology difficulty is large, simultaneously lower than T-shaped interconnection technique cost, interconnection density is high.The object of this invention is to provide a kind of low-cost GaAs ccd image sensor Wafer-level Chip Scale Package technique.
The technical solution used in the present invention is: first by resin adhesive, carry out the bonding between glass wafer and gaas wafer, protection chip active face also improves chip die intensity; Then by wet etching or physical method, make trapezoid groove structure ，Shi chip interconnects district substrate thickness attenuate; Then by dry etching technology, make perpendicular interconnection through hole, chip active face pad is come out; Then sputtering seed layer metal plating, make hole metallization and RDL layer, thereby realize chip active face to the circuit interconnection of chip back; Then make passivation layer, UBM layer and salient point; Last scribing forms individual packages chip.(referring to embodiment).
According to the above, concrete technology step of the present invention is as follows:
A. glass wafer/gaas wafer bonding
(a) first at chip active face spin coating one deck bonding agent, and glass wafer and gaas wafer are carried out to bonding, the thickness of this bonding agent is 5-15 μ m;
(b) bonding agent curing process, condition of cure is 80-120 ℃ of hot curing 100-150min after vacuum exhaust.
B. make trapezoid groove structure
(a) after completing steps A, at chip back, carry out thin glue photoetching, form interconnection district wet etching window;
(b) GaAs corrosion is to be 1H in volume ratio
2sO
4-8H
2o
2-1H
2in the etching liquid of O, carry out, the temperature that dovetail groove is made is 20-40 ℃, time 6-10 hour;
C. make perpendicular interconnection through hole
(a) after completing steps B, photoresist is uniformly distributed in chip back and dovetail groove, form the mask of dry etching perpendicular interconnection through hole;
(b) in ICP (Inductively Coupled Plasma, inductively coupled plasma)-RIE (reactive ion etching) etching system, carry out perpendicular interconnection via etch, etching gas is Cl
2or BCl
3;
(c) insulating barrier under etching gaas wafer chip active face pad.
D. hole metallization and RDL layer are made
(a) after completing steps C, carry out seed layer deposition, Seed Layer is Ti/Pt/Au layer, and wherein Ti/Pt layer is barrier layer, and Au layer is adhesion layer;
(b) thick resist lithography defines hole metallization and RDL layer plating window, and photoresist thickness is 10-20 μ m;
(c) electroplate Au layer, thickness of coating is that 5-15 μ m can interconnect reliably to guarantee the lead-in wire of making along inclined-plane in dovetail groove;
(d) plating seed layer etching.
E. passivation layer, UBM layer and stud bump making
(a) after completing steps D, deposit passivation layer 108, passivation material is epoxy resin organic resin;
(b) make UBM layer, comprise the techniques such as passivation layer etching, UBM layer deposition and UBM layer etching;
(c) In bump process, comprises and electroplates In technique and In salient point reflux technique;
F. scribing
After completing E step, thereby carry out scribing process, form independently packaged chip.
Described technique is further characterized in that:
(1) described trapezoid groove structure and perpendicular interconnection through hole are distributed in chip back interconnection Qu Sibian;
(2) described perpendicular interconnection through hole can distribute by single-row in dovetail groove bottom, also can many arranged distribution;
(3) described bonding agent condition of cure is 80-120 ℃ after vacuum exhaust, hot curing 100-150min;
(4) method of formation dovetail groove can be caustic solution:
(a) after completing steps A, at chip back, carry out thin glue photoetching, form interconnection district wet etching window;
(b) GaAs corrosion is 1H in volume ratio
2sO
4+ 8H
2o
2+ 1H
2in O etching liquid according to carrying out dovetail groove making under the temperature and time of strict control;
The trapezoid groove structure of made is of a size of: groove top wide 500-600 μ m, the wide 150-250 μ of trench bottom m, groove depth 300-340 μ m;
(5) in step D, the hole metallization of perpendicular interconnection through hole and RDL layer form simultaneously; Electroplate the lead-in wire of making along inclined-plane that Au forms on dovetail groove sidewall;
(6) in step e, passivation layer is the organic resin of spin coating, and the mobility before organic resin solidifies is filled in dovetail groove it, to guarantee the planarization of chip back;
(7) described scribing process,, first with thicker GaAs saw blade cutting gaas wafer, then uses thinner glass saw blade glass-cutting wafer, thereby forms independently packaged chip;
(8) described trapezium structure includes the perpendicular interconnection through hole that a circle is arranged, and salient point adopts part-structure;
(9) sensor chip signal from active face through perpendicular interconnection through hole and trapezoid groove structure by pad, hole in metallization, RDL layer and salient point transfer to chip back, thereby realize wafer level packaging.
Actual effect of the present invention is on the basis of wafer level technique, to have realized the relieved package of imageing sensor.The encapsulating structure providing in the present invention, guaranteeing, under the prerequisite of reliability, to have reduced packaging cost and technology difficulty, has improved the interconnection density of encapsulation.
Accompanying drawing explanation
Fig. 1 is that the people such as Kazumasa Tanida are in the silica-based image sensor package structure of the employing perpendicular interconnection through hole technology realization of document US2010/0252902 proposition;
Fig. 2 is that the people such as Badehi are in the silica-based image sensor package structure of the T-shaped interconnection technique realization of employing of document WO99/40624 proposition;
Fig. 3 is GaAs ccd image sensor Wafer-level Chip Scale Package body 20 profiles of making according to best mode for carrying out the invention;
Fig. 4 is partial detailed interconnection structure in the encapsulating structure obtaining according to best mode for carrying out the invention;
Fig. 5 makes the process chart of GaAs ccd image sensor Wafer-level Chip Scale Package structure according to best mode for carrying out the invention, Fig. 5 A-Fig. 5 H is respectively from initial disk until the main technological steps that scribing finishes; Wherein, chip die cross section before A. encapsulation; B. bonding; C. make dovetail groove; D. make perpendicular interconnection through hole; E. the isolating metalization that insulate and making RDL layer; F. make passivation layer; G. make salient point.
In figure:
Insulating barrier 03 active face pad under 01GaAs substrate 02 pad
04 bonding material 05 glass wafer 06 metallization & RDL
07 insulation isolation 08UBM layer 09 salient point
13 dovetail groove 14 perpendicular interconnection through hole 20 packaging bodies
Embodiment
In order to make advantage of the present invention and good effect find full expression, below in conjunction with drawings and Examples, substantive distinguishing features of the present invention and significant progress are described further.
As shown in Figure 3, be according to the profile of the GaAs ccd image sensor Wafer-level Chip Scale Package body 20 of best mode for carrying out the invention making.
As shown in Figure 4, be encapsulating structure profile and the interconnection structure according to best mode for carrying out the invention, in trapezoid groove structure 13, comprise in the present embodiment the perpendicular interconnection through hole 14 that a circle is arranged, salient point 09 adopts partial array structure.As can be seen from Figure 4 sensor chip signal from active face through perpendicular interconnection through hole and trapezoid groove structure by pad 03, hole in metallization and RDL layer 06 and salient point 09 transfer to chip back, thereby realize wafer level packaging.
According to best mode for carrying out the invention, Fig. 5 is the process chart that application best mode for carrying out the invention is made encapsulating structure.
Fig. 5 A is chip die cross section before encapsulation, comprises gallium arsenide substrate 01, insulating barrier 02 and pad 03, according to best mode for carrying out the invention pad size, is 50 * 50 μ m
2, solder pad space length 100-200 μ m.
Fig. 5 B is glass wafer 05/ gaas wafer 01 bonding technology, according to best mode for carrying out the invention bonding material, is 5-15 μ m light-transmissive resin bonding agent 04.
Fig. 5 C is dovetail groove 13 manufacture crafts, according to best mode for carrying out the invention dovetail groove 13 structures, according to individual pen pad, make, adopt the rear wet-cleaned of trapezoidal saw blade cutting to make, it is of a size of groove top wide 500-600 μ m, the wide 150-250 μ of trench bottom m, groove depth 300-340 μ m.
Fig. 5 D is perpendicular interconnection through hole 14 manufacture crafts, according to best mode for carrying out the invention perpendicular interconnection through hole 14, adopts ICP-RIE dry etch process to make, and aperture and hole depth are respectively 40-60 μ m and 80-120 μ m.
Fig. 5 E isolation of insulating, insulating barrier under etching GaAs chip wafer active face pad.
Fig. 5 F is hole metallization & RDL layer 06 manufacture craft, according to best mode for carrying out the invention hole metallization & RDL layer 06, adopt the Au layer of electroplating 5-15 μ m, seed layer materials is Ti/Pt/Au, wherein Ti/Pt layer is barrier layer, Au layer is adhesion layer, and electroplating technology can complete the metallization & RDL layer of perpendicular interconnection through hole simultaneously and make.
Fig. 5 G is passivation layer 08 manufacture craft, according to best mode for carrying out the invention passivation layer 08, adopts the thick resin material of 5-15 μ m, and the mobile performance before resin solidification is fully filled in dovetail groove 13 structures resin material.
Fig. 5 H is salient point 09 manufacture craft, according to the material of best mode for carrying out the invention salient point 09, be In, UBM layer adopts and Seed Layer same material and structure, the Ti/Pt/Au composite bed depositing, Ti/Pt layer is barrier layer, and Au layer is adhesion layer, and salient point 09 is arranged according to partial array, salient point diameter is 100-150 μ m, and spacing is 200-400 μ m.
Claims (10)
1. a GaAs ccd image sensor Wafer-level Chip Scale Package structural manufacturing process, is characterized in that 1. first by resin adhesive, carrying out glass wafer and gaas wafer bonding, and protection chip active face also improves chip die intensity; 2. then by wet etching or physical method, make trapezoid groove structure ，Shi chip interconnects district substrate thickness attenuate; 3. then by dry etching technology, make perpendicular interconnection through hole, chip active face pad is come out; 4. sputtering seed layer metal plating again, makes hole metallization and RDL layer, thereby realizes chip active face to the circuit interconnection of chip back; 5. then make passivation layer, UBM layer and salient point; 6. last scribing forms individual packages chip.
2. by technique claimed in claim 1, it is characterized in that concrete technology step:
A. glass wafer/gaas wafer bonding
(a) first at chip active face spin coating one deck bonding agent, and glass wafer and gaas wafer are carried out to bonding, the thickness of this bonding agent is 5-15 μ m;
(b) bonding agent curing process, condition of cure is 80-120 ℃ after vacuum exhaust;
B. dovetail groove is made
(a) after completing steps A, at chip back, carry out thin glue photoetching, form interconnection district wet etching window;
(b) by volume ratio, be 1H
2sO
4-8H
2o
2-1H
2o corrosive liquid cleans and collapses limit to obtain the surface that edge is bright and clean.
C. perpendicular interconnection through hole is made
(a) after completing steps B, carry out photoetching, first make photoresist be uniformly distributed in chip back and dovetail groove, form the mask of dry etching perpendicular interconnection through hole;
(b) in ICP-RIE etching system, carry out perpendicular interconnection via etch, etching gas is Cl
2or BCl
3;
(c) insulating barrier under etching gaas wafer chip active face pad.
D. hole metallization and RDL layer are made
(a) after completing steps C, carry out seed layer deposition, Seed Layer is Ti/Pt/Au layer, and wherein Ti/Pt layer is barrier layer, and Au layer is adhesion layer;
(b) thick resist lithography defines hole metallization and RDL layer plating window, and photoresist thickness is 10-20 μ m;
(c) electroplate Au layer, thickness of coating is that 5-15 μ m can interconnect reliably to guarantee the lead-in wire of making along inclined-plane in dovetail groove;
(d) plating seed layer etching.
E. metal layer and stud bump making under passivation layer, salient point
(a) after completing steps D, deposit passivation layer, passivation material is epoxy resin;
(b) make UBM layer, comprise the techniques such as passivation layer etching, UBM layer deposition and UBM layer etching;
(c) In bump process, comprises and electroplates In technique and In salient point reflux technique;
F. scribing
(a), after completing E step, thereby carry out scribing process, form independently packaged chip.
3. by the technique described in claim 1 or 2, it is characterized in that gaas wafer chip active face has adopted vertical through hole interconnection technique to the interconnection of chip back; The interconnection technique that gaas wafer has adopted trapezoid groove structure and perpendicular interconnection through hole technology to combine.
4. by technique claimed in claim 3, it is characterized in that trapezoid groove structure and perpendicular interconnection through hole are distributed in chip back interconnection Qu Sibian; Perpendicular interconnection through hole is single-row distribution in dovetail groove bottom, or many arranged distribution.
5. by technique claimed in claim 2, it is characterized in that be 100-150min the curing time after the bonding agent vacuum exhaust in steps A.
6. by technique claimed in claim 2, the method that it is characterized in that forming dovetail groove in step B is caustic solution:
(a) after completing steps A, at chip back, carry out thin glue photoetching, form interconnection district wet etching window;
Or (b) GaAs corrosion is 1H in volume ratio
2sO
4+ 8H
2o
2+ 1H
2in O etching liquid, under the temperature and time of controlling, carry out dovetail groove making;
The trapezoid groove structure of made is of a size of: groove top wide 500-600 μ m, the wide 150-250 μ of trench bottom m, groove depth 300-340 μ m.
7. by technique claimed in claim 2, it is characterized in that:
1. in step D, electroplate the lead-in wire of making along inclined-plane that Au forms on dovetail groove sidewall;
2. in step e, passivation layer is the organic resin of spin coating, is filled in dovetail groove, to guarantee the planarization of chip back before resin solidification.
8. by technique claimed in claim 2, it is characterized in that the scribing process adopting in step F is first by GaAs saw blade, to cut gaas wafer, then uses glass saw blade glass-cutting wafer, thereby forms independently packaged chip.
9. by technique claimed in claim 2, it is characterized in that:
1. described dovetail groove making temperature is 20-40 ℃, and the time is 6-10 hour;
2. aperture and the hole depth of ICP-RIE dry etch process making perpendicular interconnection through hole are respectively 40-60 μ m and 80-120 μ m;
3. described passivation layer adopts the thick resin material of 5-15 μ m;
4. In salient point is pressed partial array arrangement, and salient point diameter is 100-150 μ m, and spacing is 200-400 μ m.
10. by technique claimed in claim 2, it is characterized in that:
1. described trapezium structure includes the perpendicular interconnection through hole that a circle is arranged, and salient point adopts part-structure;
2. sensor chip signal from active face through perpendicular interconnection through hole and trapezoid groove structure by pad, hole in metallization, RDL layer and salient point transfer to chip back, thereby realize wafer level packaging.
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| CN201110419761.7A CN102509718B (en) | 2011-12-15 | 2011-12-15 | Wafer-level chip size encapsulation technology for GaAs (gallium arsenide) CCD (Charge Coupled Device) image sensor |
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| CN103441097B (en) * | 2013-08-28 | 2015-08-05 | 华进半导体封装先导技术研发中心有限公司 | A kind of lithographic method of deep hole bottom insulating layer of silicon oxide |
| CN103474364B (en) * | 2013-09-04 | 2016-11-09 | 惠州硕贝德无线科技股份有限公司 | A kind of novel method for packaging semiconductor |
| CN103474365B (en) * | 2013-09-04 | 2017-01-18 | 惠州硕贝德无线科技股份有限公司 | Method for packaging semiconductor |
| CN103700621B (en) * | 2013-12-27 | 2016-06-01 | 华进半导体封装先导技术研发中心有限公司 | The lithographic method of the vertical glass through hole of a kind of high aspect ratio |
| CN104409429A (en) * | 2014-11-23 | 2015-03-11 | 北京工业大学 | Chip package structure with stress sacrifice structure and package method |
| CN104681454B (en) * | 2015-02-28 | 2017-10-13 | 苏州科阳光电科技有限公司 | The packaging technology of device is locked for novel finger print |
| CN110739341A (en) * | 2019-10-30 | 2020-01-31 | 安徽熙泰智能科技有限公司 | Micro OLED display structure and preparation method thereof |
| CN111029321A (en) * | 2019-11-21 | 2020-04-17 | 华天科技（昆山）电子有限公司 | Semiconductor device and method for manufacturing the same |
| CN117810072A (en) * | 2024-03-01 | 2024-04-02 | 四川科尔威光电科技有限公司 | Control method for uniformity of wafer chip gold-tin alloy |
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| US6268619B1 (en) * | 1997-04-24 | 2001-07-31 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with high aspect ratio via hole including solder repelling coating |
| CN101802990A (en) * | 2007-07-31 | 2010-08-11 | 泰塞拉公司 | Semiconductor packaging process using through silicon vias |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6268619B1 (en) * | 1997-04-24 | 2001-07-31 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with high aspect ratio via hole including solder repelling coating |
| CN101802990A (en) * | 2007-07-31 | 2010-08-11 | 泰塞拉公司 | Semiconductor packaging process using through silicon vias |
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