CN102495294A

CN102495294A - System and method for testing parasitic inductance

Info

Publication number: CN102495294A
Application number: CN2011103895433A
Authority: CN
Inventors: 董文鹏; 党彦明
Original assignee: ZHONGDA PHOTOELECTRIC INDUSTRY (WUJIANG) CO LTD; Delta Electronics Shanghai Co Ltd
Current assignee: DELTA ELECTRONICS (JIANGSU) Ltd; Delta Electronics Shanghai Co Ltd
Priority date: 2011-11-30
Filing date: 2011-11-30
Publication date: 2012-06-13
Anticipated expiration: 2031-11-30
Also published as: CN102495294B

Abstract

The invention provides a system and a method for testing a parasitic inductance value. The system comprises a circuit to be tested, a driving device and a test device, wherein a direct current source supplies power to an inversion bridge arm of the circuit to be tested; the driving device is electrically connected to a control electrode of each switch body in the inversion bridge arm; the test device is used for testing an inversion bridge arm voltage which is carried by a switch body to be tested in the inversion bridge arm during instant turning-off and the change rate of a current which flows through the inversion bridge arm; and according to voltages of the switch body and the direct current source and the change rate of the current which flows through the inversion bridge arm, the parasitic inductance value is obtained by calculation. By adoption of the invention, under the control of the driving device, an upper bridge arm switch body keeps turned on, and a lower bridge arm switch body is turned on and turned off; and the test device tests a bridge arm voltage which is carried by the lower bridge arm switch body and the change rate of the current which flows through the lower bridge arm switch body, the parasitic inductance value is obtained by calculation, and quantization basis is provided for selection of design parameters of an absorption circuit, so that the reliability of an inverter is optimized, and the design cost of a product can be reduced.

Description

System and method for testing parasitic inductance

Technical Field

The present invention relates to parasitic inductances in inverter circuits, and more particularly to systems and methods for testing such parasitic inductances.

Background

Currently, in the main loop of the inverter, the power bus surge voltage mainly includes the turn-off surge voltage of the IGBT and the recovery surge voltage of the freewheeling diode. The main reason for generating these surge voltages is that parasitic inductances, such as parasitic inductance of a dc bus, parasitic inductance inside a power device, parasitic inductance appearing at the time of a power device lead, and the like, inevitably exist in the main circuit of the inverter. When the power device is subjected to commutation of the power circuit under the action of the driving circuit, the current flowing through the parasitic inductance may suddenly change, and thus the parasitic inductance generates a voltage (may also be referred to as a parasitic electromotive force) that prevents the current from changing. The voltage is superposed with the direct current bus voltage and loaded at two ends of the power device in the form of surge voltage, so that serious electromagnetic interference is generated.

In addition, parasitic inductance is a parameter that is highly detrimental to inverter performance. When the parasitic inductance in the main loop is ignored, the normal operation of the power device is not influenced. However, when the power device encounters a large-current fault, the controlled turn-off of the power device generates a parasitic voltage on the parasitic inductance, and if the parasitic inductance is too large, the more energy it stores during the turn-off process, and the higher the parasitic voltage. It is easy to see that when the voltage superimposed on both ends of the IGBT once exceeds the rated withstand voltage of the IGBT, the IGBT will break down and be damaged.

One solution in the prior art is to design the snubber circuit corresponding to the parasitic inductance using a snubber (i.e., a snubber). For example, the buffer may be a capacitor, two ends of the capacitor are connected across an inverter bridge arm of the inverter main circuit, and after a capacitance value matching an inductance value of the parasitic inductor is selected, the energy stored in the parasitic inductor is absorbed by the buffer capacitor. However, the relationship between the buffer capacitance and the parasitic inductance is:

C_{sn} = \frac{L_{S} {I_{O}}^{2}}{{(V_{CM} - V_{CC})}^{2}}

wherein L is_SParasitic inductance in the inversion main loop; i is_OIs the off-current of the IGBT, which under extreme conditions is equal to the maximum short-circuit current of the IGBT; v_CMThe maximum peak voltage allowed for the IGBT; and V_CCIs the dc bus voltage. As can be seen from the above-mentioned relational expression, when the capacitance value of the snubber capacitor is determined, the parasitic inductance in the main circuit must be accurately calculated in advance.

In view of this, a problem to be solved by related technical personnel in the industry is urgent, how to design a test scheme so as to accurately measure the parasitic inductance in the inversion main loop and improve the reliability of the inverter.

Disclosure of Invention

Aiming at the defects existing in the prior art that the parasitic inductance value is calculated when an inverter main loop designs an absorption circuit of the parasitic inductance, the invention provides a system and a method for testing the parasitic inductance.

According to one aspect of the present invention, there is provided a test system adapted to test the value of parasitic inductance in a circuit, the test system comprising:

the circuit to be tested is provided with an inverter bridge arm, wherein the inverter bridge arm is powered by a direct current source;

the driving device is electrically connected to the control electrode of each switch body in the inverter bridge arm and is used for controlling the switch bodies in the inverter bridge arm; and

the test device is used for measuring the voltage of the inverter bridge arm borne at the moment when a switch body to be tested in the inverter bridge arm is turned off and the change rate of the current flowing through the inverter bridge arm;

and calculating the inductance value of the parasitic inductor according to the voltage of the switch body, the direct-current source voltage and the change rate of the current flowing through the inverter bridge arm, which are measured by the testing device.

Preferably, the driving device provides a first driving signal and a second driving signal which are electrically isolated from each other for the circuit to be tested; the first driving signal controls a switch body in the inverter bridge arm, which is connected with the switch body to be tested in series, to maintain an on state, and the second driving signal controls the on and off of the switch body to be tested in the inverter bridge arm, which is measured by the measuring device.

Preferably, the second driving signal is a square wave pulse driving signal with a preset pulse width, and the square wave pulse driving signal is used for controlling the switch body to be tested to be close to or be switched off after reaching a saturation state. In addition, the width of the square wave pulse driving signal is between 0 and 10 us. More preferably, the width of the square wave pulse driving signal is between 6 and 8 us.

Preferably, the inverter bridge arm comprises an upper bridge arm switch body and a lower bridge arm switch body connected in series with the upper bridge arm switch body, and the lower bridge arm switch body is the switch body to be tested.

Preferably, the test device is an oscilloscope with a trigger function, and the oscilloscope starts a trigger operation at the moment when the switch body to be tested is turned off, so as to capture the waveform of the current flowing through the inverter bridge arm.

Preferably, the switches in the inverter bridge arm are all insulated gate bipolar transistors.

In accordance with still another aspect of the present invention, there is provided a method for testing an inductance value of a parasitic inductance, the method including:

providing a circuit to be tested, wherein the circuit to be tested comprises an inverter bridge arm which is powered by a direct current source;

providing a plurality of driving signals, and controlling a switch body in the inverter bridge arm by using the plurality of driving signals;

measuring the voltage of an inverter bridge arm borne at the moment when a switch body to be measured in the inverter bridge arm is turned off and the change rate of the current flowing through the inverter bridge arm; and

and calculating to obtain the inductance value of the parasitic inductance between the inverter bridge arm and the direct current source according to the voltage value of the direct current source, the voltage of the inverter bridge arm borne by the switch body to be tested, which is measured at the moment when the switch body to be tested is turned off, and the current change rate flowing through the inverter bridge arm.

Preferably, the dc source is a bus capacitor at the output of the rectifier.

Preferably, the instant when the switch body to be tested is turned off is that the switch body to be tested approaches the saturation conducting state or the saturation conducting state changes to turn-off.

Preferably, the plurality of driving signals include a first driving signal and a second driving signal, and the first driving signal controls a switch body in the inverter bridge arm, which is connected in series with the switch body to be tested, to maintain an on state; the second driving signal controls the on and off of a switch body to be measured in the inverter bridge arm measured by the measuring device.

Preferably, the second driving signal is a square wave pulse with a preset pulse width. In addition, the pulse width of the square wave is between 0 and 10 us. More preferably, the square wave pulse width is between 6 and 8 us.

By adopting the system and the method for testing the parasitic inductance, the upper bridge arm switch body and the lower bridge arm switch body of the inverter bridge arm are respectively driven by the first drive signal with constant amplitude and the second drive signal with adjustable pulse width and constant amplitude from the drive device, the change rate of the inverter bridge arm voltage borne at the moment of turning off the switch body to be tested in the inverter bridge arm and the current flowing through the inverter bridge arm is measured by the test device, the inductance value of the parasitic inductance is obtained by calculation, and a quantization basis is provided for the selection of the design parameters of the absorption circuit, so that the reliability of the inverter is optimal, and the design cost of a product can be reduced.

Drawings

The various aspects of the present invention will become more apparent to the reader after reading the detailed description of the invention with reference to the attached drawings. Wherein,

FIG. 1 shows the inductance L for the parasitic in the inverting primary loop_SSchematic diagram of the buffer circuit of (1);

FIG. 2A illustrates a schematic diagram of a system for testing the value of parasitic inductance in a circuit to be tested, in accordance with an aspect of the present invention;

FIG. 2B is a block diagram showing the structure of a driving apparatus of the test system in FIG. 2A;

fig. 2C is a schematic diagram showing a relationship between a driving voltage and a short-circuit time and a short-circuit current of the to-be-tested switch body of the inverter bridge arm in fig. 2A;

FIG. 2D is a block diagram of a test apparatus of the test system of FIG. 2A; and

fig. 3 illustrates a flow diagram of a method for testing the inductance value of a parasitic inductor in accordance with another aspect of the invention.

Detailed Description

In order to make the present disclosure more complete and complete, reference is made to the accompanying drawings, in which like references indicate similar or analogous elements, and to the various embodiments of the invention described below. However, it will be understood by those of ordinary skill in the art that the examples provided below are not intended to limit the scope of the present invention. In addition, the drawings are only for illustrative purposes and are not drawn to scale.

Specific embodiments of various aspects of the present invention are described in further detail below with reference to the accompanying drawings.

FIG. 1 shows the inductance L for the parasitic in the inverting primary loop_SSchematic diagram of a buffer circuit of (1). Referring to fig. 1, the inductance L on the dc bus of the inverter main circuit_SThe equivalent is represented as a parasitic inductance in the loop whose path is from node P, via upper bridge IGBTQ1, lower bridge IGBT Q2, node N, and energy storage capacitor C1 in that order, and back to node P. Further, the snubber capacitance C2 is adopted as a capacitor corresponding to the parasitic inductance L_SThe two ends of the capacitor C2 are bridged across the inverter bridge arm of the inverter main loop, that is, one end of the capacitor C2 is electrically connected to the collector of the upper bridge IGBT Q1, and the other end of the capacitor C2 is electrically connected to the emitter of the lower bridge IGBT Q2.

In the selection and parasitic inductance L_SThe capacitor C2, which is matched in inductance, absorbs the energy stored in the parasitic inductor through the buffer capacitor C2. In particular, the amount of the solvent to be used,

when the parasitic inductance L_SIn short circuit, the relationship between voltages can be expressed as formula 1:

<math> <mrow> <msub> <mi>v</mi> <mrow> <mi>ce</mi> <mrow> <mo>(</mo> <mi>t</mi> <mo>)</mo> </mrow> </mrow> </msub> <mo>=</mo> <msub> <mi>V</mi> <mi>CC</mi> </msub> <mo>+</mo> <mfrac> <mn>1</mn> <mi>C</mi> </mfrac> <mo>&Integral;</mo> <mi>i</mi> <mrow> <mo>(</mo> <mi>t</mi> <mo>)</mo> </mrow> <mi>dt</mi> </mrow> </math>

<math> <mrow> <msub> <mi>V</mi> <mi>CC</mi> </msub> <msub> <mrow> <mo>-</mo> <mi>v</mi> </mrow> <mrow> <mi>ce</mi> <mrow> <mo>(</mo> <mi>t</mi> <mo>)</mo> </mrow> </mrow> </msub> <mo>=</mo> <mo>-</mo> <mfrac> <mn>1</mn> <mi>C</mi> </mfrac> <mo>&Integral;</mo> <mi>i</mi> <mrow> <mo>(</mo> <mi>t</mi> <mo>)</mo> </mrow> <mi>dt</mi> </mrow> </math>

when the buffer capacitor C2 is open, the relationship between the voltages can be expressed as formula 2:

v_{ce (t)} = V_{CC} - L \frac{di (t)}{dt}

L \frac{di (t)}{dt} = V_{CC} - v_{ce (t)}

combining equation 1 and equation 2, then:

<math> <mrow> <mfrac> <mrow> <mi>di</mi> <mrow> <mo>(</mo> <mi>t</mi> <mo>)</mo> </mrow> </mrow> <mi>dt</mi> </mfrac> <mo>=</mo> <mo>-</mo> <mfrac> <mn>1</mn> <mrow> <msub> <mi>L</mi> <mi>S</mi> </msub> <mi>C</mi> </mrow> </mfrac> <mo>&Integral;</mo> <mi>i</mi> <mrow> <mo>(</mo> <mi>t</mi> <mo>)</mo> </mrow> <mi>dt</mi> </mrow> </math>

obtaining the parasitic inductance L after processing_SThe function relationship of the current of the upper circuit along with the time is as follows:

i (t) = I_{O} * \cos (t / \sqrt{L_{S} C})

after derivation, the function can be transformed into:

\frac{di (t)}{dt} = - \frac{I_{O}}{\sqrt{L_{S} C}} \sin (\frac{t}{\sqrt{L_{S} C}})

then pass through V_ce(t)And obtaining the maximum peak voltage V allowed to be loaded by the IGBT_CMComprises the following steps:

V_{CM} = V_{CC} + I_{O} \sqrt{L_{S} / C}

thus, the buffer capacitor C2 (i.e., C)_sn) And parasitic inductance L_SThe relationship between them is:

C_{sn} = \frac{L_{S} {I_{O}}^{2}}{{(V_{CM} - V_{CC})}^{2}}

wherein, I_OIs the off-current of the IGBT, which under extreme conditions is equal to the maximum short-circuit current of the IGBT; v_CCIs the dc bus voltage.

As can be seen from the above, the parasitic inductance L is determined_SThe capacitance of the buffer capacitor C2 can be precisely selected.

Therefore, the invention provides a system and a method for accurately measuring the value of parasitic inductance in an inverter bridge arm of a circuit to be measured. In detail, fig. 2A shows a schematic diagram of a system for testing a value of parasitic inductance in a circuit to be tested according to an aspect of the present invention, fig. 2B shows a structural block diagram of a driving apparatus of the testing system in fig. 2A, fig. 2C shows a schematic diagram of a relationship between a driving voltage and a short-circuit time and a short-circuit current of a switch body to be tested of an inverter bridge arm in fig. 2A, and fig. 2D shows a structural block diagram of the testing apparatus of the testing system in fig. 2A.

Referring to fig. 2A, 2B, 2C and 2D, the test system includes a circuit to be tested, a driving apparatus and a test apparatus 30. For example, the dc source may be a storage capacitor C1 or other devices or equipment capable of providing dc, the inverter bridge arm includes a plurality of switch bodies, and the switch bodies may be power switch devices such as Insulated Gate Bipolar Transistors (IGBTs), Integrated Gate Commutated Thyristors (IGCTs), Injection Enhanced Gate Transistors (IEGTs), and the like, taking an IGBT as an example, in fig. 2A, the storage capacitor C1 is connected in parallel with the IGBT inverter bridge arm, and the IGBT inverter bridge arm has an IGBT Q1 and an IGBT Q2, when the storage capacitor C1 is switched onWhen discharging is started and the IGBT Q1 and the IGBT Q2 are electrically turned on, the loop current path in the inverter main loop can be expressed as: from one end (e.g., node P) of the storage capacitor C1, the current sequentially passes through the collector C and emitter E of the IGBT Q1, the collector C and emitter E of the IGBT Q2, and reaches the other end (e.g., node N) of the storage capacitor C1. Due to the parasitic inductance in the inverting primary loop, the calculation formula (i.e., L) of the parasitic electromotive force of the parasitic inductance when the loop current changes is used_SXdi/dt) that is required to determine the voltage value of the parasitic electromotive force and the variation of the current in unit time (also called the current variation rate), so as to obtain the inductance value L of the parasitic inductance_S。

The driving device is electrically connected to a control electrode (such as a gate of an IGBT) of each switch body in the inverter bridge arm, and is used for controlling the switch bodies in the inverter bridge arm. In an embodiment, the driving device provides a first driving voltage VD1 and a second driving voltage VD2 for the inverter bridge arm, which are electrically isolated from each other, wherein the first driving voltage VD1 is electrically connected between the gate and the emitter of the IGBT Q1 for controlling the switch IGBT Q1 of the inverter bridge arm, which is connected in series with the switch IGBT Q2 to be tested, to maintain an on state, and the second driving voltage VD2 is electrically connected between the gate and the emitter of the IGBT Q2 for controlling the switch IGBT Q2 to be tested, which is measured by the measuring device, in the inverter bridge arm to be switched on and off. In one embodiment, as shown in fig. 2A, the driving apparatus includes a microprocessor 201 and a buffer circuit 203. The microprocessor 201 has a plurality of keys corresponding to a plurality of external I/os, and when the keys are in a predetermined key combination state, the buffer circuit 203 outputs the first driving voltage VD1 and the second driving voltage VD 2. The first driving voltage VD1 and the second driving voltage VD2 are electrically isolated from each other, that is, the buffer circuit 203 outputs two relatively independent driving voltages VD1 and VD 2. Preferably, in order to cooperate with the testing system of the present invention, the first driving voltage VD1 is a constant dc voltage, and the second driving voltage VD2 is a square-wave pulse driving voltage with adjustable pulse width and constant amplitude, and the square-wave pulse is used to control the IGBT Q2 to be tested to approach or turn off after reaching a saturation state. For example, the voltage magnitudes of the first driving voltage VD1 and the second driving voltage VD2 can be set to be the same, such as + 15V. Taking the example of loading 15V voltage on the switch body to be tested, in order to avoid the damage of the IGBT Q2 of the switch body to be tested, the pulse width of the square wave is between 0 and 10 us. Considering delay influences such as turn-off time of the IGBT Q2 of the switch body to be tested, the pulse width of the square wave is 6-8 us. As can be seen from fig. 2C, the width of the square wave pulse can be varied according to the magnitude of the voltage applied to the transistor to be tested. In more detail, the higher the magnitude of the second driving voltage VD2 applied between the gate and the emitter of the IGBT Q2, the smaller the corresponding pulse width thereof should be set. Conversely, as the second drive voltage VD2 decreases in magnitude, its corresponding pulse width may increase accordingly. For example, when the amplitude of the second driving voltage is +15V, the square wave pulse width is between 0 and 10 us; when the amplitude of the second driving voltage is reduced to +11V, the square wave pulse width can be between 0 and 20 us. In the embodiment, the IGBT Q2 of the switch body to be tested can be turned off after approaching or reaching a saturation state by loading square wave pulse with the amplitude of 15V and the pulse width of 6-8 us, so that parasitic inductance existing under the maximum working current of the inverter loop can be conveniently measured. In other embodiments, the to-be-tested switch body IGBT Q2 may also be turned off when the to-be-tested switch body IGBT Q2 reaches the preset rated value. Therefore, the width of the square wave pulse can be set according to the maximum operating current of the inverter circuit, and according to the type of the switch to be tested, and is not limited to the specific numbers illustrated herein. Referring to fig. 2D, the test device 30 is configured to measure a voltage of the inverter bridge arm and a change rate of a current flowing through the inverter bridge arm at a moment when the to-be-tested switch IGBT Q2 in the inverter bridge arm is turned off, and the test system calculates and obtains an inductance value of the parasitic inductor according to the voltage of the switch body, the voltage of the dc source, and the change rate of the current flowing through the inverter bridge arm, which are measured by the test device.

In one embodiment, the testing apparatus is an oscilloscope with a trigger function, which starts the trigger operation of the oscilloscope at the moment when the to-be-tested switch IGBT Q2 is turned off, and captures the waveform of the current flowing through the inverter bridge arm. As shown in FIG. 2C, the oscilloscope with trigger function has a firstA voltage test channel 301, a second voltage test channel 303, and a current test channel 305. Wherein the first voltage test channel 301 is used for measuring the voltage V between the gate and the emitter of the IGBT Q2_GEThe grid voltage change of the IGBT Q2 is monitored, the damage of the IGBT Q2 is avoided, meanwhile, a trigger signal can be provided for the oscilloscope, and the oscilloscope is triggered to capture the current waveform. For example, when the IGBT Q2 is turned off, it is detected that the gate voltage of the IGBT Q2 jumps to zero, that is, the IGBT Q2 changes from the on state to the off state, and an oscilloscope is triggered to capture a current waveform. The second voltage test channel 303 is used to measure the voltage V between the collector and emitter of the IGBT Q2_CEAnd a current test channel 305 for measuring the current Ic flowing through the IGBT Q2. For example, the positive electrode of the test probe of the first voltage test channel 301 is electrically connected to the gate (labeled as Q) of the IGBT Q2_2G) The positive electrode of the test probe of the second voltage test channel 303 is electrically connected to the collector (labeled as Q) of the IGBT Q2_2C) And the negative electrodes of the test probes of the first voltage test channel 301 and the second voltage test channel 303 are electrically connected to the emitter (labeled as Q) of the IGBT Q2_2E). For another example, the current test channel 305 is electrically connected to the emitter of the IGBT Q2 to measure the current Ic flowing through the IGBT Q2 at the moment when the to-be-tested switch body IGBT Q2 is turned off, i.e., the current flowing through the inverter bridge arm. In this embodiment, the first voltage testing channel 301 may not be connected to the switch under test, and the oscilloscope is triggered to capture the current waveform of the inverter bridge arm by the current sampling signal of the current testing channel 305 or the voltage sampling signal of the second voltage testing channel. When the switch body IGBT Q2 to be tested is turned off, the change of current or the voltage V is caused_CEThe change of the voltage can be used as a trigger signal for an oscilloscope to grab the waveform of the current change when the IGBT Q2 is switched off.

During the test, first, the I/O key outside the microprocessor 201 is set to a predetermined key combination state (also referred to as a trigger signal) so that the buffer circuit 203 outputs the first driving voltage VD1 and the second driving voltage VD 2. Then, the test device 30 obtains the rate of change of the current Ic flowing through the inverter bridge arm from the state close to saturation or saturation on to the off state of the to-be-tested switch body IGBT Q2, and the voltage across the to-be-tested switch body IGBT Q2.

As mentioned above, due to the parasitic inductance in the loop, when the IGBT turns off and turns on, the parasitic inductance is charged by the increase of the current to generate the parasitic electromotive force V_εThe magnitude L of the parasitic electromotive force and the parasitic inductance_sThe mathematical relationship between the two is as follows:

V_ε＝L_s×dI_c/dt

in addition, due to parasitic electromotive force V_εAnd the voltage V across the storage capacitor C1_PNThe sum of which is equal to the voltage V between the collector and the emitter of the IGBT Q2_CEThus at V_PNAnd V_CEUnder known conditions, the parasitic inductance L can be accurately obtained_sThe inductance value of (c).

Fig. 3 illustrates a flow diagram of a method for testing the magnitude of parasitic inductance in an inverting primary loop, in accordance with another aspect of the invention. Referring to fig. 3 in combination with fig. 2A, in the testing method, step S31 is executed to provide a circuit to be tested, where the circuit to be tested includes an inverter bridge arm. The inverter bridge arm is powered by a direct current source. Then, step S33 is executed to provide a plurality of driving signals, and the plurality of driving signals are used to control the switches in the inverter leg, for example, a first driving voltage VD1 (i.e., a first driving signal) and a second driving voltage VD2 (i.e., a second driving signal) are respectively output to IGBT Q1 and IGBT Q2, where the first driving voltage VD1 controls IGBT Q1 in the inverter leg to maintain an on state, and the second driving voltage VD2 controls the on and off of IGBT Q2 in the inverter leg measured by the measuring device. Next, steps S35 and S37 are executed, the change rate of the voltage in the inverter bridge arm and the current flowing through the inverter bridge arm, which are borne by the to-be-tested switch body IGBT Q2 in the inverter bridge arm at the moment of turning off, is measured, and then the inductance value of the parasitic inductance existing between the inverter bridge arm and the dc source is calculated and obtained according to the voltage value of the dc source, the measured voltage at the moment of turning off the switch body IGBT Q2, and the change rate of the current flowing through the inverter bridge arm.

In one embodiment, the dc source is a bus capacitor at the output of the rectifier, and the dc voltage loaded by the bus capacitor supplies power to the inverter bridge arm.

In another embodiment, the second driving signal is a square wave pulse with a preset pulse width, and the square wave pulse is used to control the IGBT Q2 of the switch to be tested to approach or turn off after reaching the saturation state. For example, the square wave pulse width is between 0 and 10 us. Preferably, the square wave pulse width is between 6 and 8 us. The square wave pulse width design reason is consistent with that described above for the test device embodiment and is therefore not redundant in this embodiment of the measurement method.

It should be understood by those skilled in the art that fig. 3 schematically describes a method flow for measuring the parasitic inductance by using the lower arm switch body of the inverter arm as the switch body to be measured, but the invention is not limited thereto. For example, in other embodiments, the upper bridge arm switch body of the inverter bridge arm can be used as the switch body to be tested, and one driving signal is used to control the on and off of the upper bridge arm switch body in the inverter bridge arm measured by the measuring device, and another driving signal is used to control the lower bridge arm switch body in the inverter bridge arm connected in series with the upper bridge arm switch body to maintain the on state.

Hereinbefore, specific embodiments of the present invention are described with reference to the drawings. However, those skilled in the art will appreciate that various modifications and substitutions can be made to the specific embodiments of the present invention without departing from the spirit and scope of the invention. Such modifications and substitutions are intended to be included within the scope of the present invention as defined by the appended claims.

Claims

1. A test system adapted to test the value of parasitic inductance in a circuit, the test system comprising:

the testing device is used for measuring the voltage of the inverter bridge arm borne at the moment when a switch body to be tested in the inverter bridge arm is turned off and the change rate of the current flowing through the inverter bridge arm;

2. The test system of claim 1, wherein the driving device provides a first driving signal and a second driving signal electrically isolated from each other for the circuit under test; the first driving signal controls a switch body in the inverter bridge arm, which is connected with the switch body to be tested in series, to maintain an on state, and the second driving signal controls the on and off of the switch body to be tested in the inverter bridge arm, which is measured by the measuring device.

3. The test system as claimed in claim 2, wherein the second driving signal is a square-wave pulse driving signal with a preset pulse width, and the square-wave pulse driving signal is used to control the switch body to be tested to approach or reach a saturation state and then turn off.

4. The test system of claim 3, wherein the square wave pulse drive signal has a width of between 0 and 10 us.

5. The test system of claim 4, wherein the square wave pulse drive signal has a width of between 6-8 us.

6. The test system of claim 1, wherein the inverter bridge arm comprises an upper bridge arm switch body and a lower bridge arm switch body connected in series with the upper bridge arm switch body, and the lower bridge arm switch body is the switch body to be tested.

7. The test system according to claim 1, wherein the test device is an oscilloscope with a trigger function, which starts a trigger operation at the moment when the switch body to be tested is turned off, and captures the waveform of the current flowing through the inverter bridge arm.

8. The test system of claim 1, wherein the switches in the inverter leg are all insulated gate bipolar transistors.

9. A method for testing the inductance of a parasitic inductor, the method comprising:

10. The method of claim 9, wherein the dc source is a bus capacitor at the output of a rectifier.

11. The method as claimed in claim 9, wherein the moment when the switch body under test is turned off is that the switch body under test approaches a saturated on state or that the saturated on state changes to off.

12. The method according to claim 9, wherein the plurality of driving signals include a first driving signal and a second driving signal, and the first driving signal controls a switch body of the inverter bridge arm connected in series with the switch body to be tested to maintain an on state; and the second driving signal is used for measuring the on and off of a switch body to be measured in the inverter bridge arm by the measuring device.

13. The method of claim 12, wherein the second driving signal is a square wave pulse with a predetermined pulse width.

14. The method of claim 13, wherein the square wave pulse width is between 0 and 10 us.

15. The method of claim 14, wherein the square wave pulse width is between 6 and 8 us.

16. The method of claim 9, wherein the inverter bridge arm comprises an upper bridge arm switch body and a lower bridge arm switch body connected in series with the upper bridge arm switch body, and the lower bridge arm switch body is the switch body to be tested.

17. The method of claim 9, wherein the switches in the inverter leg are all insulated gate bipolar transistors.