CN102468297B - Adjustable holding voltage ESD protection device - Google Patents
Adjustable holding voltage ESD protection device Download PDFInfo
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- CN102468297B CN102468297B CN201110167566.XA CN201110167566A CN102468297B CN 102468297 B CN102468297 B CN 102468297B CN 201110167566 A CN201110167566 A CN 201110167566A CN 102468297 B CN102468297 B CN 102468297B
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- 239000004065 semiconductor Substances 0.000 claims abstract description 17
- 238000002955 isolation Methods 0.000 claims description 7
- 230000003068 static effect Effects 0.000 claims description 3
- 238000002347 injection Methods 0.000 description 45
- 239000007924 injection Substances 0.000 description 45
- 238000012423 maintenance Methods 0.000 description 12
- 238000000034 method Methods 0.000 description 11
- 238000010586 diagram Methods 0.000 description 9
- 230000001681 protective effect Effects 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 230000009286 beneficial effect Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/735—Lateral transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
Abstract
An electrostatic discharge (ESD) protection structure comprises a bipolar PNP transistor having an emitter formed by a first high voltage P type implanted region disposed underneath a first P+ region and a collector formed by a second high voltage P type implanted region disposed underneath a second P+ region. The ESD protection structure can have an adjustable threshold voltage by controlling the distance between the first high voltage P type implanted region and the second high voltage P type implanted region. Based upon a basic ESD protection structure, the ESD protection device can provide a reliable ESD protection for semiconductor devices having different voltage ratings.
Description
Technical field
The present invention relates to field of semiconductor devices, more particularly, relate to a kind of adjustable holding voltage ESD protection device.
Background technology
Static discharge (ESD) is because the accumulation of electrostatic charge causes the repid discharge of flowing between two objects.Because repid discharge can produce relatively large electric current, ESD can destroy semiconductor device.In order to reduce the semiconductor failure because ESD causes, develop esd protection circuit, to provide current discharge path.When an esd event occurs, discharging current is conducted by discharge path, and without by protected internal circuit.
In semiconductor technology, nmos pass transistor, silicon controlled rectifier (SCR) and RC is used to trigger PMOS transistor widely.But along with the development of submicron semiconductor processes, existing esd protection scheme may not meet the requirement that semi-conductor industry improves day by day.Such as, in high-voltage applications, because ME for maintenance is not high enough, the esd protection circuit based on SCR or NMOS may cause locking fault.On the other hand, although have relatively high ME for maintenance, RC triggers PMOS transistor may consume large chip region.And multiple application all requires different esd protection ME for maintenance.Existing ESD scheme may not provide the multiple esd protection ME for maintenance based on basic esd protection structure.
Summary of the invention
According to an aspect of the present invention, a kind of static discharge (ESD protective device) is provided, comprises: bipolar PNP transistor, comprising: emitter, formed by the first high-voltage P-type region and the P+ region be arranged on described first high-voltage P-type region; And collector electrode, formed by the second high-voltage P-type region and the 2nd P+ region be arranged on described second high-voltage P-type region.
Preferably, the first high-voltage P-type region is arranged under the first isolated area.
Preferably, the second high-voltage P-type region is arranged under the first isolated area.
Preferably, the first high-voltage P-type region is by high pressure N well region and the second high-voltage P-type zone isolation.
Preferably, bipolar PNP transistor has base stage, and this base stage is floating or be electrically connected to described emitter.
Preferably, the distance between described first high-voltage P-type region and described second high-voltage P-type region is between 1 μm to 10 μm.
Preferably, described first high-voltage P-type region has 10
15/ cm
3to 10
16/ cm
3doping content.
According to a further aspect in the invention, a kind of esd protection structure is provided, comprises: high pressure N trap; First high-voltage P-type region, is arranged on described high pressure N trap; One P+ region, is arranged on described first high-voltage P-type region; 2nd P+ region, a contiguous described P+ region is arranged; And N+ region, be arranged on described high pressure N trap.
Preferably, a described P+ region is by the first isolated area and described 2nd P+ zone isolation.
Preferably, this structure comprises further: the second high-voltage P-type region, is arranged on described high pressure N trap.
Preferably, described first high-voltage P-type region has 10
15/ cm
3to 10
16/ cm
3doping content.
Preferably, described 2nd P+ region is arranged on described second high-voltage P-type region.
Preferably, a described P+ region forms the emitter of bipolar PNP transistor.
Preferably, a described P+ region and described first high-voltage P-type region form the emitter of bipolar PNP transistor.
Preferably, described 2nd P+ region forms the collector electrode of bipolar PNP transistor.
Preferably, described 2nd P+ region and described second high-voltage P-type region form the described emitter of described bipolar PNP transistor.
According to another aspect of the invention, a kind of semiconductor chip is provided, comprises: bipolar PNP transistor, comprising: emitter, formed by the first high-voltage P-type region and the P+ region be arranged on described first high-voltage P-type region; And collector electrode, formed by the second high-voltage P-type region and the 2nd P+ type region be arranged on described second high-voltage P-type region; First pad, is electrically connected with the described emitter of described bipolar PNP transistor; And second pad, be electrically connected with the described collector electrode of described bipolar PNP transistor.
Preferably, this semiconductor chip also comprises: multiple circuit, has the first terminal be electrically connected with described first pad and the second terminal be electrically connected with described second pad.
Preferably, described second pad ground connection.
Preferably, this semiconductor chip also comprises: multiple bipolar PNP transistor, is electrically connected in series between described first pad and described second pad.
Accompanying drawing explanation
In order to understand the present invention and advantage thereof better, make following description by reference to the accompanying drawings as a reference now, wherein:
Fig. 1 illustrates the simplification sectional view of the esd protection structure according to embodiment;
Fig. 2 illustrates the equivalent circuit diagram of the esd protection structure shown in Fig. 1;
Fig. 3 illustrates the I-V curve of the esd protection circuit of the Fig. 1 with different SEC value;
Fig. 4 illustrates the simplification sectional view of the esd protection structure according to embodiment;
Fig. 5 illustrates the equivalent circuit diagram of the esd protection structure shown in Fig. 4;
Fig. 6 illustrates the simplification sectional view of the esd protection structure according to another embodiment;
Fig. 7 illustrates the equivalent circuit diagram of the esd protection structure shown in Fig. 6;
Fig. 8 illustrates integrated circuit level esd protection schematic diagram; And
Fig. 9 illustrates the another esd protection scheme adopting multiple esd protection circuit of connecting between I/O pad and VSS pad.
Unless otherwise noted, the respective digital in different accompanying drawing and symbol are often referred to appropriate section.Draw accompanying drawing to be clearly shown that the related fields of multiple embodiment and must not draw in proportion.
Embodiment
Below describe manufacture and use of this preferred embodiment in detail.But should expect, the invention provides can specialize in multiple specific environment multiple can application invention thought.Described specific embodiment only illustrates and manufactures and use ad hoc fashion of the present invention, does not limit the scope of the invention.
Fig. 1 illustrates the simplification sectional view of the esd protection structure 100 according to embodiment.Esd protection structure 100 comprises a P+ region 102, the 2nd P+ region 104, isolated area 112, second isolated area 114, first high-voltage P-type injection region 110, high-voltage P-type injection region 108, second, N+ region 116, first and high pressure N trap (HVNW) 106.HVNW 106 is formed by dopant material being injected substrate.Such as, antimony and/or arsenic can be injected into about 10
15/ cm
3to 10
16cm
3doping content.First high-voltage P-type injection region 108 and a P+ region 102 are sequentially arranged on HVNW 106.First high-voltage P-type injection region 108 is arranged under a P+ region 102.According to embodiment, after doping, the first high-voltage P-type injection region 108 has about 10
15/ cm
3with 10
16/ cm
3between doping content.Similarly, the second high-voltage P-type injection region 110 and the 2nd P+ region 104 are sequentially arranged on HVNW 106.Second high-voltage P-type injection region 110 is arranged under the 2nd P+ region 104.According to embodiment, after doping, the second high-voltage P-type doped region 110 has about 10
15/ cm
3to 10
16/ cm
3between doping content.
First isolated area 112 and the second isolated area 114, for isolating active area, flow between adjacent active regions to prevent Leakage Current.Isolated area (such as, 112) can (such as, heat growth, deposition) and material (such as, silica, silicon nitride) be formed in several ways.In this embodiment, the first isolated area 112 and the second isolated area 114 can isolate the manufacture of (STI) technology by surface channel.
N+ region 116 is arranged in HVNW 106 in the side in the 2nd P+ region 104.N+ region 116 is isolated by the second isolated area 114 and the 2nd N+ region 104.One P+ region 102 is isolated by the first isolated area 112 and the 2nd P+ region 104.The top of the first high-voltage P-type injection region 108 and the top of the second high-voltage P-type injection region 110 are isolated by the first isolated area 112.As shown in fig. 1, the bottom of the first high-voltage P-type injection region 108 is isolated by the bottom of HVNW 106 and the second high-voltage P-type injection region 110.Distance between first high-voltage P-type injection region 108 and the second high-voltage P-type injection region 110 is set to SEC.
Those skilled in the art will recognize that, Fig. 1 illustrates the ideal profile of doping.Distance SEC may change after DIFFUSION TREATMENT subsequently.Distance SEC shown in Fig. 1 is for illustrating multiple inventive aspects of multiple embodiment.The invention is not restricted to any specific range between two high-voltage P-type injection zones.
According to an embodiment, SEC is customized parameter.As shown in Figure 1, SEC represents the distance between two high-voltage P-type injection regions (that is, 108 and 110).More particularly, SEC is the distance at the edge 124 of high-voltage P-type injection region, edge 122 to the second 110 from the first high-voltage P-type injection region 108.In semiconductor doping process, dopant material can be added via ion implantation.By controlling the doping scope of high-voltage P-type injection region (such as, 108), SEC can correspondingly change.As about Fig. 3 described below, SEC helps to provide the adjustable threshold voltage of esd protection.
It should be noted that the doping techniques used in previous case is selected for demonstration object purely, and be not intended to multiple embodiment of the present invention to be limited to any specific doping techniques.Those skilled in the art will recognize that, embodiment (such as, adopting diffusion technique) can be adopted.
In FIG, esd protection structure 100 provides esd protection scheme on chip.For esd protection application, the 2nd P+ region 104 is connected with I/O (I/O) pad usually, and a P+ region 102 is connected with power supply VSS pad usually, the usual ground connection of power supply VSS pad or be connected with power supply.The beneficial aspects of described embodiment is, the adjustable threshold voltage of ESD protective device allows the different voltage esd protection schemes obtained from the same structure shown in Fig. 1.
Fig. 2 shows the equivalent circuit diagram of the esd protection structure 100 shown in Fig. 1.The equivalent electric circuit 200 of the esd protection structure 100 shown in Fig. 1 comprises the bipolar PNP transistor 202 with emitter 204, base stage 210 and collector electrode 206.Base stage 210 is connected with N+ region 116 by resistor 206.Resistor 206 represents the dead resistance in HVNW 106 (not shown, but shown in Figure 1).Emitter 204 is formed by the 2nd P+ region 104 and the second high-voltage P-type injection region 110.Collector electrode 206 is formed by a P+ region 102 and the first high-voltage P-type injection region 108.Refer again to Fig. 1, the second high-voltage P-type injection region 110 and the 2nd P+ region 104 have identical conduction type, but have different doping contents.2nd P+ region 104 is extended to darker region by the second high-voltage P-type injection region 110.Similarly, a P+ region is extended to darker region by the first high-voltage P-type injection region 108.The emitter 204 of bipolar PNP transistor 202 and the extension of collector electrode 206 cause the change of the breakdown voltage characteristic between emitter 204 and collector electrode 206.
In a word; simplified electrical circuit diagram 200 illustrates that the related circuit of esd protection structure 100 forms a bipolar PNP transistor (such as; 202); wherein; its emitter and collector by P+ region (such as; 104) and be arranged on high-voltage P-type injection region (such as, 108) under P+ region and formed.But should be realized that, although Fig. 2 shows the esd protection circuit with a bipolar PNP transistor (such as, PNP transistor 202), esd protection circuit can hold the bipolar PNP transistor of any amount.And, should be understood that and the multiple bipolar PNP transistor be connected in series can be used to realize esd protection circuit.In other words, other configurations (such as, bipolar PNP transistor in parallel is connected to bipolar PNP transistor in parallel) of multiple bipolar PNP transistor are also in the desired extent of the present embodiment.
Esd protection circuit 200 is usually located at the VSS place of I/O pad and device to be protected (not shown, but shown in Figure 8).2nd P+ region 104 is connected with I/O pad usually, and a P+ region 102 is connected with VSS usually, the usual ground connection of VSS or be connected to power supply.If esd event occurs, then between the 2nd P+ region 104 and a P+ region 102, apply voltage peak.Thus bipolar PNP transistor 202 experiences voltage peak, it can exceed the puncture voltage of bipolar PNP transistor 202.As a result, bipolar PNP transistor 202 enters avalanche conduction pattern.As the result of avalanche conduction, bipolar PNP transistor provides current path, makes esd discharge electric current can flow to collector electrode 206 from emitter 204.Voltage clamp between emitter 204 and collector electrode 206 to comparatively low level, makes it possible to protect the internal circuit be connected with emitter 204 by the conduction of bipolar PNP 202.
Refer again to Fig. 2, base stage 210 is connected with emitter 204 by resistor 208.In this embodiment, resistor 208 represents the volume resistance of HVNW 106.It should be noted that the resistance between base stage 210 and emitter 204 can have an impact to the collector-emitter breakdown voltage of bipolar PNP transistor 202.Direct connection between N+ region 116 and the 2nd P+ region 104 is only provided for illustration purpose, and is only provided for the example providing the function that can comprise in this embodiment.Those skilled in the art will recognize that, in esd protection application, N+ region 116 can floating (float) or be connected with the 2nd P+ region 104 by the external resistor of esd protection structure 100 outside.
Fig. 3 illustrates three curves illustrating and have the electric current relative voltage feature of the esd protection circuit 200 of different SEC value.The trunnion axis of Fig. 3 represents the ESD voltage striding across esd protection circuit (such as, esd protection circuit 200).The vertical axis of Fig. 3 represents the ESD electric current flowing through esd protection circuit.Curve 302, curve 304 and curve 306 illustrate and flow through the electric current that SEC is respectively the esd protection circuit 200 of 1.6 μm, 2 μm and 2.5 μm.
As shown in Figure 3, the puncture voltage for curve 302,304 and 306 closely similar (about 15V).Once the ESD voltage applied exceedes puncture voltage, then increase by three ESD electric currents and the ESD voltage in proportion applied.But at identical ESD current class place, different SEC value causes esd protection circuit 200 to have different ME for maintenance.Such as, when the SEC esd protection circuit 200 (shown in curve 302) that is 1.6 μm provides the ESD electric current of 0.004, respective sustain voltage is just over 20V.On the contrary, for identical ESD current class, SEC is the ME for maintenance that the esd protection circuit 200 (shown in curve 306) of 2.5 μm has about 23V.Similarly, when esd protection circuit 200 has the SEC of 2 μm, curve 304 illustrates that ME for maintenance is about 21.5V.
Fig. 3 illustrates that the ESD protective device based on esd protection structure 100 can have different ME for maintenance by selecting different SEC values.The increase of SEC causes the proportional increase of respective sustain voltage.Like this, the beneficial aspects of the present embodiment is, by selecting different SEC values, can have the semiconductor device of different rated voltage (such as, 20V, 30V, 40V) based on identical basic structure manufacture.
Fig. 4 illustrates the simplification sectional view of the esd protection structure 400 according to embodiment.As shown in Figure 4, the first high-voltage P-type injection region 108 is arranged under a P+ region 102.But the second high-voltage P-type injection region 110 is not arranged in esd protection structure 400.First high-voltage P-type injection region 108 has the conduction type identical with a P+ region 102, makes the first high-voltage P-type injection region 108 that a P+ region 102 can be made to extend to darker grade.This help provides the ME for maintenance feature different from traditional bipolar PNP transistor.
Fig. 5 illustrates the equivalent circuit diagram of the esd protection structure 400 shown in Fig. 4.Esd protection circuit 500 comprises the bipolar PNP transistor 502 with emitter 504, base stage 510, collector electrode 506 and resistor 508.As shown in Figure 4, the first high-voltage P-type injection region 108 and a P+ region 102 form collector electrode 506.Emitter 504 is formed by the 2nd P+ region 104.Resistor 508 represents the dead resistance in HVNW 106 (not shown, but shown in Figure 4).Be similar to the esd protection circuit 200 described about Fig. 2, once the voltage striding across emitter 504 and collector electrode 506 exceedes the puncture voltage of bipolar PNP transistor 502, esd protection circuit 500 just can provide ESD current path.
Fig. 6 illustrates the simplification sectional view of the esd protection structure 600 according to another embodiment.As shown in Figure 6, the second high-voltage P-type injection region 110 is arranged under the 2nd P+ region 10.But the first high-voltage P-type injection region 108 is not arranged in esd protection structure 600.Second high-voltage P-type injection region 110 has the conduction type identical with the 2nd P+ region 104, makes the second high-voltage P-type injection region 110 the 2nd P+ region 104 can be extended to darker grade.This help provides the ESD current path with the feature different from conventional PNP transistor.
Fig. 7 illustrates the equivalent circuit diagram of the esd protection structure 600 shown in Fig. 6.Esd protection circuit 700 comprises the bipolar PNP transistor 702 with emitter 704, base stage 710, collector electrode 706 and resistor 708.As shown in Figure 6, the second high-voltage P-type injection region 110 and the 2nd P+ region 104 form emitter 704.Collector electrode 706 is formed by a P+ region 102.Resistor 708 represents the dead resistance in HVNW 106 (not shown, but shown in Figure 6).Be similar to the esd protection circuit 200 described about Fig. 2, once the voltage striding across emitter 704 and collector electrode 706 exceedes the puncture voltage of bipolar PNP transistor 702, esd protection circuit 700 just can provide ESD current path.
Fig. 8 illustrates integrated circuit level esd protection schematic diagram.Integrated circuit (IC) chip 800 has VDD pad 808, I/O pad 806 and VSS pad 804.Internal circuit 802 is connected with VDD pad 808 and VSS pad 804.Internal circuit 802 comprises the input be connected with I/O pad 806 further.Esd protection circuit 200 is connected between I/O pad 806 and VSS pad 804.It should be noted that esd protection circuit 200 is only provided for illustration purpose.Esd protection circuit between I/O pad 806 and VSS pad 804 can be respectively any one in the esd protection circuit 200,500 and 700 shown in Fig. 2, Fig. 5 and Fig. 7.
When esd event occurs between I/O pad 806 and VSS pad 804; esd protection circuit 200 conduct ESD current; and esd protection circuit (such as; esd protection circuit 200) connection by the voltage clamp between I/O pad 806 and VSS pad 804 at maximum voltage (it is assigned to internal circuit 802) below, to protect the internal circuit be connected between I/O pad 706 and VSS pad 705.The beneficial aspects of described circuit-level esd protection is, esd protection circuit is provided for the bypass of ESD current flowing, to protect internal circuit.
Fig. 9 illustrates the another esd protection scheme adopting and be connected in series multiple esd protection circuit between I/O pad and VSS pad.Be similar to Fig. 8, Fig. 9 comprises integrated circuit 800, VDD pad 808, I/O pad 806, VSS pad 804 and internal circuit 802.But Fig. 8 comprises being connected in series of the esd protection circuit be electrically connected with I/O pad 806 and VSS pad 804 further.In high-voltage applications, single esd protection circuit (esd protection circuit 200 such as, shown in Fig. 8) can not provide reliable esd protection.On the contrary, the multiple esd protection circuits 200 be connected in series can provide adjustable esd protection breakdown point and adjustable esd protection ME for maintenance.
In fig .9, if esd event occurs, then between I/O pad 806 and VSS pad 804, voltage peak is applied.The esd protection circuit be connected in series can almost be connected simultaneously.Each esd protection circuit all provides esd protection ME for maintenance.The voltage 806 of I/O pad is clamped down on the level under the maximum rated voltage of internal circuit 802 by the summation of the puncture voltage of all ESD circuit be connected in series, and makes internal circuit 802 protected.
In the present embodiment, by controlling the distance between two high-voltage P-type injection regions, ESD protective device can have the adjustable threshold voltage for esd protection.Esd protection circuit provides esd protection scheme flexibly for the semiconductor device with different rated voltage.
According to an embodiment; ESD protective device has bipolar PNP transistor, and bipolar PNP transistor has by the first high-voltage P-type injection region and is arranged on emitter that the P+ type region on the first high-voltage P-type injection region formed and by the second high-voltage P-type injection region be arranged on the collector electrode that the 2nd P+ region on the second high-voltage P-type injection region formed.Distance between first high-voltage P-type injection region and the second high-voltage P-type injection region is SEC.The ME for maintenance of ESD protective device regulates by selecting different SEC values.
According to a kind of modification of above-described embodiment; ESD protective device has bipolar PNP transistor, and bipolar PNP transistor has by the first high-voltage P-type injection region and is arranged on the emitter that the P+ region on the first high-voltage P-type injection region is formed and the collector electrode formed by the 2nd P+ region.
According to another modification of above-described embodiment; ESD protective device has bipolar PNP transistor, and bipolar PNP transistor has the emitter that formed by a set P+ region and by high-voltage P-type injection region be arranged on the collector electrode that the 2nd P+ region on high-voltage P-type injection region formed.
Although describe embodiments of the invention and advantage thereof in detail, should be appreciated that, when not deviating from the spirit and scope of the present invention be defined by the following claims, can various change, substitutions and modifications be carried out.
In addition, the scope of the application be not limited to describe in this specification technique, machine, manufacture, material composition, device, method and step specific embodiment.Those skilled in the art from openly can easy understand, can according to content of the present disclosure utilize perform the function substantially identical with corresponding embodiment described herein or realize the existing of basic identical result or the technique developed after a while, machine, manufacture, material form, means, method or step.Therefore, the scope of claims comprises these techniques, machine, manufacture, material composition, means, method or step.
Claims (20)
1. static discharge (ESD) protection device, comprising:
Bipolar PNP transistor, comprising:
Emitter, is formed by the first high-voltage P-type region and the P+ region be arranged on described first high-voltage P-type region; And
Collector electrode, is formed by the second high-voltage P-type region and the 2nd P+ region be arranged on described second high-voltage P-type region;
Wherein, the top in the first high-voltage P-type region and the top in the second high-voltage P-type region are by the first isolated area isolation.
2. device according to claim 1, wherein, described first high-voltage P-type region is arranged under the first isolated area.
3. device according to claim 1, wherein, described second high-voltage P-type region is arranged under described first isolated area.
4. device according to claim 1, wherein, described first high-voltage P-type region is by high pressure N well region and described second high-voltage P-type zone isolation.
5. device according to claim 1, wherein, described bipolar PNP transistor has base stage, and described base stage is floating or be electrically connected to described emitter.
6. device according to claim 1, wherein, the distance between described first high-voltage P-type region and described second high-voltage P-type region is between 1 μm to 10 μm.
7. device according to claim 1, wherein, described first high-voltage P-type region has 10
15/ cm
3to 10
16/ cm
3doping content.
8. an esd protection structure, comprising:
High pressure N trap;
First high-voltage P-type region, is arranged on described high pressure N trap;
One P+ region, is arranged on described first high-voltage P-type region;
2nd P+ region, a contiguous described P+ region is arranged; And
N+ region, is arranged on described high pressure N trap;
Wherein, the top in the first high-voltage P-type region and the top in the second high-voltage P-type region are by the first isolated area isolation.
9. structure according to claim 8, wherein, a described P+ region is by the first isolated area and described 2nd P+ zone isolation.
10. structure according to claim 8, comprises further: the second high-voltage P-type region, is arranged on described high pressure N trap.
11. structures according to claim 8, wherein, described first high-voltage P-type region has 10
15/ cm
3to 10
16/ cm
3doping content.
12. structures according to claim 8, wherein, described 2nd P+ region is arranged on described second high-voltage P-type region.
13. structures according to claim 8, wherein, a described P+ region forms the emitter of bipolar PNP transistor.
14. structures according to claim 8, wherein, a described P+ region and described first high-voltage P-type region form the emitter of bipolar PNP transistor.
15. structures according to claim 8, wherein, described 2nd P+ region forms the collector electrode of bipolar PNP transistor.
16. structures according to claim 10, wherein, described 2nd P+ region and described second high-voltage P-type region form the emitter of bipolar PNP transistor.
17. 1 kinds of semiconductor chips, comprising:
Bipolar PNP transistor, comprising:
Emitter, is formed by the first high-voltage P-type region and the P+ region be arranged on described first high-voltage P-type region; And
Collector electrode, is formed by the second high-voltage P-type region and the 2nd P+ type region be arranged on described second high-voltage P-type region;
Wherein, the top in the first high-voltage P-type region and the top in the second high-voltage P-type region are by the first isolated area isolation;
First pad, is electrically connected with the described emitter of described bipolar PNP transistor; And
Second pad, is electrically connected with the described collector electrode of described bipolar PNP transistor.
18. semiconductor chips according to claim 17, comprise further: multiple circuit, have the first terminal be electrically connected with described first pad and the second terminal be electrically connected with described second pad.
19. semiconductor chips according to claim 17, wherein, described second pad ground connection.
20. semiconductor chips according to claim 17, comprise further: multiple bipolar PNP transistor, are electrically connected in series between described first pad and described second pad.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US41431910P | 2010-11-16 | 2010-11-16 | |
| US61/414,319 | 2010-11-16 | ||
| US12/952,641 US8390096B2 (en) | 2010-11-16 | 2010-11-23 | Adjustable holding voltage ESD protection device |
| US12/952,641 | 2010-11-23 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102468297A CN102468297A (en) | 2012-05-23 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20160277017A1 (en) * | 2011-09-13 | 2016-09-22 | Fsp Technology Inc. | Snubber circuit |
| US8853825B2 (en) | 2011-09-27 | 2014-10-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | ESD protection apparatus |
| DE102013009305B4 (en) | 2013-06-04 | 2018-12-06 | X-Fab Semiconductor Foundries Ag | Integrated protection device for integrated high-voltage MOS transistors in CMOS circuits |
| CN103354230B (en) * | 2013-07-12 | 2015-10-21 | 江苏艾伦摩尔微电子科技有限公司 | The electrostatic discharge protective TVS device of high maintenance voltage |
| US9543420B2 (en) | 2013-07-19 | 2017-01-10 | Nxp Usa, Inc. | Protection device and related fabrication methods |
| CN104465644B (en) * | 2013-09-23 | 2017-06-09 | 中芯国际集成电路制造(上海)有限公司 | Electrostatic protection SCR structure |
| US9177953B2 (en) | 2013-10-31 | 2015-11-03 | Taiwan Semiconductor Manufacturing Company Limited | Circular semiconductor device with electrostatic discharge (ESD) device and functional device |
| US10483257B2 (en) * | 2014-02-18 | 2019-11-19 | Nxp Usa, Inc. | Low voltage NPN with low trigger voltage and high snap back voltage for ESD protection |
| EP3107122B1 (en) | 2015-06-17 | 2019-06-12 | Nxp B.V. | An electrostatic discharge protection device |
| US10263419B2 (en) * | 2016-06-15 | 2019-04-16 | Infineon Technologies Ag | Transient voltage protection circuits, devices, and methods |
| CN107680908A (en) * | 2016-08-01 | 2018-02-09 | 中芯国际集成电路制造(北京)有限公司 | High-voltage semi-conductor device and preparation method thereof |
| US11527528B2 (en) | 2020-04-21 | 2022-12-13 | Globalfoundries Singapore Pte. Ltd. | Electrostatic discharge protection devices and methods of forming electrostatic discharge protection devices |
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| US6847059B2 (en) * | 2000-10-18 | 2005-01-25 | Yamaha Corporation | Semiconductor input protection circuit |
| US7205611B2 (en) * | 2003-11-07 | 2007-04-17 | Kabushiki Kaisha Toshiba | Semiconductor device including a protection circuit |
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| US7244992B2 (en) * | 2003-07-17 | 2007-07-17 | Ming-Dou Ker | Turn-on-efficient bipolar structures with deep N-well for on-chip ESD protection |
| FR2866764A1 (en) * | 2004-02-25 | 2005-08-26 | St Microelectronics Sa | Power amplifying circuit for operational amplifier, has one circuit module with inputs coupled to main electrodes of one set of transistors, and another circuit module with outputs connected to main electrodes of another set of transistors |
| US8193560B2 (en) * | 2009-06-18 | 2012-06-05 | Freescale Semiconductor, Inc. | Voltage limiting devices |
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| US6847059B2 (en) * | 2000-10-18 | 2005-01-25 | Yamaha Corporation | Semiconductor input protection circuit |
| US7205611B2 (en) * | 2003-11-07 | 2007-04-17 | Kabushiki Kaisha Toshiba | Semiconductor device including a protection circuit |
| CN101097915A (en) * | 2006-06-12 | 2008-01-02 | 恩益禧电子股份有限公司 | Electrostatic discharge protection method and device for semiconductor device |
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| US20120119330A1 (en) | 2012-05-17 |
| CN102468297A (en) | 2012-05-23 |
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