JP2006093361A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an ESD protection circuit for achieving an ESD protection function for a high breakdown voltage MOS transistor in a semiconductor device wherein an NPN transistor and the MOS transistor are formed on one chip. <P>SOLUTION: In a bipolar ESD protection element 19 for ESD protection of the high breakdown voltage MOS transistor 20 in a BiMOS semiconductor device, the low breakdown voltage bipolar NPN transistor 21 and the high breakdown voltage MOS transistor 20 are formed on the same substrate, and a continuous semiconductor layer 6 of the same type is provided as the layer under the base layer 14 of the ESD protection element 19. Thus, the base width of the base layer of the ESD protection element 19 is increased so that the breakdown voltage of the ESD protection element 19 is improved. In the semiconductor device wherein the NPN transistor 21 and the high breakdown voltage MOS transistor 20 are formed on one chip, the ESD protection circuit for achieving the ESD protection function for the high breakdown voltage MOS transistor is thereby provided. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit manufactured by a BiMOS process and ESD protected, and a method of manufacturing a semiconductor device.

  One factor that damages a semiconductor integrated circuit is breakdown due to static electricity (hereinafter referred to as ESD). ESD is generally discharged from machinery such as a human body or a device, or a semiconductor package. As test models for these ESDs, three types of ESD models are standardized: a human body model (hereinafter referred to as HBM), a machine model (hereinafter referred to as MM), and a charge charging model (hereinafter referred to as CDM). . HBM and MM are ESD phenomena of a time of about 100 nsec and are characterized by thermal breakdown inside the semiconductor. On the other hand, CDM is not destroyed by thermal factors inside the semiconductor, but the rise of the waveform is very steep, and it is an ESD phenomenon in a very short time (about 1 nsec) compared to HBM, MM, etc. Many breakdown modes such as insulating film breakdown are observed (see, for example, Non-Patent Document 1).

In order to prevent such ESD destruction, a protection circuit is usually provided at an input terminal or an output terminal of the integrated circuit. An example thereof will be described below with reference to FIG.
FIG. 13 is a circuit diagram for explaining the ESD protection circuit, which is an example in which the high voltage MOS transistor 20 connected to the output terminal (bonding pad 18) of the semiconductor integrated circuit is protected by the ESD protection element 19.

  The drain electrode 26 of the high voltage MOS transistor 20 is connected to the bonding pad 18 and the source electrode 29 is connected to the ground. The ESD protection element 19 is connected in parallel with the high voltage MOS transistor 20, the collector electrode 22 is connected to the drain electrode 26 of the high voltage MOS transistor 20, and the base electrode 23 is connected to the emitter electrode 24 through a resistor 25 of about several tens KΩ. The emitter electrode 24 is grounded.

The operation of the ESD protection element 19 in the ESD protection circuit configured as described above will be described with reference to FIGS.
FIG. 14 is a diagram showing the current-voltage characteristic of the protected element by the ESD protection circuit, which is a generally well-known snapback characteristic of the NPN transistor, and the potential relationship between the breakdown voltage of the protected element and the power supply voltage. Shows about.

  Usually, the design of an ESD protection element uses three types of parameters: a trigger point (Vt1, It1), a holding point (Vh, Ih), and a breakdown point (Vt2, It2). As shown in FIG. 14, ESD protection of the internal circuit can be provided by designing Vt1 at a voltage lower than the breakdown region of the protected element and designing the holding voltage Vh higher than the power supply voltage of the internal circuit. Therefore, optimal ESD protection can be provided by designing according to the design window as shown in FIG.

When a positive surge is applied to the bonding pad 18 of FIG. 13, the potential of the collector electrode 22 of the ESD protection element 19 rises, and a reverse breakdown of the diode formed between the collector bases (hereinafter simply referred to as a primary breakdown). (FIG. 14: BVcbo). Current starts to flow from the collector electrode 22 toward the base electrode 23 due to the primary breakdown, and flows from the base electrode 23 to the ground via the resistor 25. At this time, the potential of the base electrode 23 rises due to the potential drop of the resistor 25, and the ESD protection element 19 starts to operate (FIG. 14: trigger point; hereinafter, the trigger potential is simply referred to as Vt1 and the trigger current is referred to as It1). Here, Vt1 is a transistor operation start voltage and correlates with the resistance value of the resistor 25 connected to BVcbo and the base. In other words, how to increase the base potential is a problem. When it is desired to lower Vt1, measures such as decreasing the BVcbo to cause a breakdown current to flow to the resistor 25 or increasing the resistance value of the resistor 25 are taken. Is done. When the ESD protection element starts to operate, the resistance between the collector 22 and the emitter 24 becomes low, so that the potential between the collector 22 and the emitter 24 decreases (FIG. 14: holding point. Hereinafter, the holding voltage is Vh, the holding current. Is described as Ih). Thereafter, the potential of the bonding pad 18 rises according to the current flowing through the ESD protection element 19 (FIG. 14: snapback region). Eventually, when the current that flows increases, the device runs out of heat due to heat generation inside the transistor (hereinafter simply referred to as secondary breakdown), and breaks down when the melting point of Si reaches about 1400 ° C due to excessive current due to secondary breakdown. (FIG. 14: breakdown point. Hereinafter, the breakdown voltage is described as Vt2 and the breakdown current is It2) (see, for example, Non-Patent Document 2 and Non-Patent Document 3).
EIA, “EIA / JEDEC STANDARD” KAI ESMARK, “Device Simulator of ESD Protection Elements” Wang, “Onchip ESD Protection for Integrated Circuits”, Kluwer Academic Publishers, 2002/01

  An NPN transistor used in a low voltage circuit block (hereinafter simply referred to as an NPN transistor) and a high breakdown voltage output MOS transistor (hereinafter simply referred to as a high voltage MOS transistor) used in a high voltage circuit block are formed on one chip. In a semiconductor device manufactured at the same time and ESD-protecting a high-breakdown-voltage MOS transistor, when the ESD protection element is configured by using the above-mentioned NPN transistor, the ESD protection element is compared with the high-breakdown-voltage MOS transistor when a surge is applied at power-on. Therefore, the above-mentioned NPN transistor is destroyed, and the above-mentioned ESD protection circuit protects the high-voltage MOS transistor from ESD. There was a problem that it was difficult to perform the function.

  According to the semiconductor device and the manufacturing method of the semiconductor device of the present invention, in the semiconductor device in which the NPN transistor and the high voltage MOS transistor are formed on one chip, an ESD protection circuit that performs an ESD protection function for the high voltage MOS transistor is provided. Objective.

  In order to achieve the above object, a semiconductor device according to claim 1 of the present invention comprises a high breakdown voltage MOS transistor, an ESD protection element connected in parallel with the high breakdown voltage MOS transistor, and a low breakdown voltage NPN bipolar transistor on the same substrate. In the BiMOS type semiconductor device formed above, the ESD protection element has a P type base diffusion layer formed by the same diffusion process as that for the NPN bipolar transistor, and is formed at the bottom of the P type base diffusion layer. A p-type semiconductor layer is provided in contact therewith.

The semiconductor device according to claim 2 is characterized in that a diffusion depth of the P-type semiconductor layer is 1.5 times or more larger than a diffusion depth of the P-type base diffusion layer.
A method of manufacturing a semiconductor device according to claim 3 includes the step of forming an N-type buried diffusion layer in a formation planned region where an NPN bipolar transistor, a high voltage MOS transistor and an ESD protection element are to be formed on a P-type substrate. A step of forming an N-type epitaxial layer on the entire surface of the P-type substrate, an isolation formation scheduled region for isolating each element in the N-type epitaxial layer, and a base formation scheduled region of the ESD protection element A step of forming a well; a step of forming a field oxide film at a predetermined position on the N-type epitaxial layer and the P-type well; and a body diffusion layer in a body formation scheduled region of the high breakdown voltage MOS transistor in the N-type epitaxial layer And forming the high breakdown voltage MOS transistor at a predetermined location on the N-type epitaxial layer. Forming a polysilicon gate of the transistor, forming a base diffusion layer on the NPN bipolar transistor and the P-type well for the ESD protection element, and forming an emitter diffusion layer in each of the base diffusion layers. And at least a step of performing.

  5. A method of manufacturing a semiconductor device according to claim 4, wherein a step of forming an N-type well in an NPN bipolar transistor region, a high breakdown voltage MOS transistor region and an ESD protection element region on a main surface of a P-type substrate, and surrounding each element region Forming a P-type well in a planned isolation region for isolation and a base formation planned region in the ESD protection element region, and the high breakdown voltage MOS transistor region and the ESD protection element on the main surface of the P-type substrate A step of forming an N-type well in the region, a step of forming a field oxide film at a predetermined location on the P-type well and the N-type well, and a body diffusion layer on a surface layer of the N-type well of the high voltage MOS transistor And forming a polysilicon gate at a predetermined position of the N-type well of the high voltage MOS transistor. Forming a base diffusion layer on the surface of the N-type well of the NPN bipolar transistor and the P-type well of the ESD protection element, and forming at least an emitter diffusion layer in each of the base diffusion layers. It is characterized by including.

  6. The method of manufacturing a semiconductor device according to claim 5, wherein an N-type buried diffusion layer is formed in an NPN bipolar transistor region, a high voltage MOS transistor region, and an ESD protection element region on a main surface of the P-type substrate, and the P-type substrate. Forming a P-type epitaxial layer on the entire surface of the N-type buried diffusion layer, and forming an N-type in the NPN bipolar transistor region, the high breakdown voltage MOS transistor region, and the collector region of the ESD protection element in the P-type epitaxial layer. A step of forming a well; a step of forming a field oxide film at a predetermined position on the P-type epitaxial layer and the N-type well; and a body diffusion layer on a surface layer in the high breakdown voltage MOS transistor region in the N-type well. Forming the high breakdown voltage MOS in the N-type well Forming a polysilicon gate at a predetermined location on the transistor region; forming a base diffusion layer in a surface layer in the NPN bipolar transistor region in the N-type well and in a P-type well of the ESD protection element; Forming an emitter diffusion layer in each of the base diffusion layers.

  As described above, in a semiconductor device in which a low breakdown voltage NPN transistor and a high breakdown voltage MOS transistor are formed on one chip, an ESD protection circuit that performs an ESD protection function for the high breakdown voltage MOS transistor can be provided.

  In the semiconductor device and the manufacturing method of the semiconductor device of the present invention, the base width of the transistor constituting the ESD protection element is increased by providing the well layer of the same type as the lower layer of the base diffusion layer of the ESD protection element. The voltage resistance of the protection element itself can be improved, and in a semiconductor device in which a low breakdown voltage NPN transistor and a high breakdown voltage MOS transistor are formed on one chip, the high breakdown voltage MOS transistor can be protected from ESD.

Embodiments of the present invention will be described below with reference to the drawings.
Example 1
1 is a cross-sectional view showing a semiconductor device according to a first embodiment of the present invention.

  As shown in FIG. 1, an NPN transistor 21 used in a circuit block having a rated voltage of 5V, a high voltage MOS transistor 20 used in a circuit block having a rated voltage of 15V, and an NPN bipolar transistor type ESD protection element 19 (hereinafter simply referred to as ESD protection). (Referred to as an element) are simultaneously fabricated on one chip. The ESD protection element 19 is designed to have a holding voltage Vh that is higher than the power supply voltage of 15 V, and to have a transistor operating voltage lower than the breakdown voltage of the high voltage MOS transistor 20.

  The collector electrode 22 of the ESD protection element 19 and the drain electrode 26 of the high breakdown voltage MOS transistor 20 are connected to the bonding pad 18 provided for leading out as an external terminal. The base electrode 23 of the ESD protection element 19 is connected to the emitter electrode 24 through the resistor 25, and the emitter electrode 24 is electrically grounded. In the high voltage MOS transistor 20, the source electrode 29 is electrically grounded, and the gate electrode 27 is connected to the internal circuit. An equivalent circuit diagram is shown in FIG.

  Hereinafter, the 5V rated low withstand voltage NPN transistor 21 and the 15V rated high withstand voltage MOS transistor 20 in the first embodiment will be described with reference to FIGS. 2, 3, 4, 4, 5, 6, 7, 8 and 9. A method of manufacturing the ESD protection element 19 by combining it with the BiMOS process will be described. Note that there are two types of semiconductor device manufacturing methods described here: a method using N-type epitaxial and a method not using N-type epitaxial, and the differences in the processes are from FIG. 2 to FIG. The process procedure from 5 onwards is the same. Therefore, FIG. 2 to FIG. 4 are divided into two types and will be described below.

  2 is a process cross-sectional view illustrating an N-type impurity layer forming process in the first embodiment, FIG. 3 is a process cross-sectional view illustrating an epitaxial layer forming process in the first embodiment, and FIG. 4 is a well forming process in the first embodiment. FIG. 5 is a process cross-sectional view for explaining a low-concentration P-type well forming process in Example 1, FIG. 6 is a process cross-sectional view for explaining a field oxide film forming process in Example 1, and FIG. FIG. 8 is a process cross-sectional view illustrating a base diffusion layer forming process in the first embodiment, and FIG. 9 is a process cross-sectional view illustrating a transistor forming process in the first embodiment. is there.

  First, in the process using epitaxial as shown in FIG. 2A, N type impurity ions are implanted into the P type substrate 1 over the entire surface of the high voltage MOS transistor 20 and the ESD protection element 19 to form a buried diffusion layer. An N-type impurity layer 47 is formed. On the other hand, the process without using the epitaxial process is shown in FIG.

Next, in FIG. 3A, an N-type epitaxial layer 48 having a concentration of about 1 × 10 ¹⁵ / cm ³ is formed on the P-type substrate 1. At this time, an N type buried diffusion layer 4 is formed. In FIG. 3B of the process not using N-type epitaxial, the P-type substrate 1 remains.

4A, a P-type well 2 and an N-type well 3 having a concentration of about 1 × 10 ¹⁶ / cm ³ are formed in each element region from the surface of the semiconductor substrate to the inside of Si to about 1 μm. At this time, the P-type well 2 is formed as a separation layer of each element at the position of the base formation scheduled region in the ESD protection element portion. On the other hand, the same implantation is performed in the process using no epitaxial layer in FIG.

In FIG. 5, the process using epitaxial is the same as that in FIG. In the process not using epitaxial, the N-type well 4 having a concentration of about 1 × 10 ¹⁸ / cm ³ is formed at a depth of about 2 μm by high energy implantation over the entire surface of the high voltage MOS transistor 20 and the ESD protection element 19. . The N-type well 4 cancels out the P-type impurity and the N-type impurity, and the P-type well 2 formed in the base formation scheduled region of the ESD protection element 19 has a lower concentration than the P-type well 2 for separation. Layer 6 is formed. The process after FIG. 5 is the same procedure whether epitaxial is used or not.

  In FIG. 6, a field oxide film 17 is formed on the silicon substrate surface by a well-known LOCOS method. Next, the body diffusion layer 11 is formed by ion-implanting P-type impurities into the body position of the high voltage MOS transistor 20. Then, in FIG. 7, the polysilicon gate 16 of the high voltage MOS transistor 20 is formed.

  Next, in FIG. 8, the base diffusion layer 8 of the NPN transistor 21 is formed, and at the same time, the base diffusion layer 14 of the ESD protection element 19 is formed. At this time, the base diffusion layer 14 of the ESD protection element 19 is obtained by adding the concentration of the P-type semiconductor layer 6 formed in advance and the concentration of the base diffusion layer 8 of the NPN transistor 21 used in the internal circuit. Thus, a P-type diffusion layer 14 having a higher concentration is formed.

  9, openings are formed at the positions of the emitter diffusion layer 7 of the NPN transistor 21 and the emitter diffusion layer 15 and the collector contact 13 of the ESD protection element 19, and the positions of the source diffusion layer 12 and the drain diffusion layer 10 of the high voltage MOS transistor 20. N-type impurities are ion-implanted.

  Next, the electrodes of each element are connected so that the ESD protection element 19 and the high voltage MOS transistor 20 are connected to the circuit of FIG. By such a procedure, the NPN transistor 21, the ESD protection element 19 and the high voltage MOS transistor 20 having different ratings can be simultaneously manufactured on one chip as shown in FIG.

  In the BiMOS process used in this embodiment, for example, the high breakdown voltage MOS transistor 20 can have BVDS (corresponding to BVcbo in FIG. 14) = about 23V and Vt2 = about 30V under certain process conditions. At this time, the base width of the base diffusion layer of the ESD protection element 19 is increased by about 1.5 times by combining the base diffusion layer 14 formed simultaneously with the base diffusion layer of the low breakdown voltage NPN transistor 21 and the P well layer 6. Vh> 15V and Vt1 <30V are satisfied. Since the BVcbo of the ESD protection element 19 (which is 21 V under this condition) is lower than the BVDS of the high voltage MOS transistor 20, the ESD protection element 19 breaks down faster than the high voltage MOS transistor, and the surge current is mainly caused by the ESD protection element 19 To flow into. Then, the ESD protection element 19 starts to start the snapback operation at a voltage lower than Vt2 of the high voltage MOS transistor 20. Therefore, the relationship between Vt2 of the high voltage MOS transistor 20 and Vt1 of the ESD protection element 19 is Vt2> Vt1. Further, the ESD protection element 19 has a lower hfe in the vertical direction due to the expansion of the base width. In the snapback characteristic, Vt1 can be expressed by the product of Vh and the nth root of hfe. Therefore, Vh of the ESD protection element 19 increases compared to before adding the P well 6. Based on the above principle, Vh of the ESD protection element 19 satisfies Vh> 15V. That is, the ESD protection element snaps back at a voltage higher than the rated voltage of the DMOS and lower than the breakdown voltage, and therefore fits in the design window of FIG.

  Therefore, in the voltage range in which the high breakdown voltage MOS transistor normally operates, the ESD protection element has a voltage lower than BVDS of the high breakdown voltage transistor when a positive surge is applied to the bonding pad 18 in the equivalent circuit diagram of FIG. 19 operates, and the potential of the bonding pad 18 is fixed at Vh of the ESD protection element 19. Since the surge current flows from the bonding pad 18 through the ESD protection element 19 to the ground, ESD protection of the high voltage MOS transistor 20 is possible, and the NPN transistor and the high voltage MOS transistor are formed on one chip. In the semiconductor device, even if the ESD protection element is formed by using a low breakdown voltage bipolar process, an ESD protection circuit that performs an ESD protection function for the high breakdown voltage MOS transistor can be provided.

As described above, the circuit of this embodiment uses the diffusion layer forming process of the element manufactured on one chip, and realizes the process of increasing the breakdown voltage of the ESD protection element 19 and reducing the transistor operating voltage. There is a merit that it can be manufactured without newly increasing.
(Example 2)
The second embodiment will be described below with reference to FIG.

FIG. 10 is a sectional view showing a semiconductor device according to the second embodiment of the present invention.
The semiconductor device shown in FIG. 10 is formed using a BiMOS process in which a P-type epitaxial layer 32 formed by epitaxial growth is formed on a P-type silicon substrate 30. The protection circuit is the same as that of the first embodiment shown in FIG.

  10, the ESD protection element 19 includes an N-type buried diffusion layer 31 as a collector, a P-type epitaxial layer 43, and a base diffusion layer formed simultaneously with the P-type epitaxial layer including the base diffusion layer 34 of the low breakdown voltage NPN transistor 21. The N-type diffusion layer on the surface of the P-type epitaxial layer is configured as an emitter diffusion layer 45. The ESD protection element 19 is connected in parallel with the high voltage MOS transistor 20, the base electrode 23 is connected to the ground together with the emitter electrode 24 through the resistor 25, and the collector electrode 22 is connected to the drain electrode 26 of the high voltage MOS transistor 20. Has been.

The manufacturing method of FIG. 10 will be described below with reference to FIGS.
FIG. 11 is a process cross-sectional view illustrating a P-type epitaxial layer growth process in the second embodiment, and FIG. 12 is a process cross-sectional view illustrating an N-type well formation process in the second embodiment.

First, in FIG. 11, N-type impurities are ion-implanted into the entire surface of the high-breakdown-voltage MOS transistor 20 and the ESD protection element 19 with respect to the P-type silicon substrate 30, and then P is grown at a concentration of about 1 × 10 ¹⁶ / cm ³ by epitaxial growth. A type epitaxial layer 32 is formed. At this time, an N-type buried diffusion layer 31 is formed at the position of the high voltage MOS transistor 20 and the ESD protection element.

  Next, in FIG. 12, N-type wells are formed in the NPN bipolar transistor region, the high voltage MOS transistor region, and the ESD protection element region in the P-type epitaxial layer 32. At this time, the P-type epitaxial layer 32 in which the N-type well is not formed serves as a separation layer between the elements (NPN bipolar transistor, high voltage MOS transistor, ESD protection element). The N well layer becomes the collector layer 35 of the low breakdown voltage NPN transistor 21, the drain layer 38 of the high breakdown voltage MOS transistor 20, and the collector layer 38 of the ESD protection element 19.

The steps after LOCOS are the same as those in the first embodiment, and the description thereof is omitted below.
As described above, the structure of the second embodiment is as shown in FIG. 10, and the base diffusion layer 44 of the ESD protection element 19 is the same as the base diffusion layer 34 of the low breakdown voltage NPN transistor 21 on the P-type epitaxial layer 43. If the diffusion width, the base width is larger than that of the base diffusion layer 34, and the diffusion layer concentration similar to that of the first embodiment is selected for each element, the design satisfying the design window of the protection element in FIG. ESD protection of the high voltage MOS transistor 20 is possible. Therefore, in a semiconductor device in which an NPN transistor and a high breakdown voltage MOS transistor are formed on one chip, even if the ESD protection element is formed using a low breakdown voltage bipolar process, an ESD that performs an ESD protection function for the high breakdown voltage MOS transistor. A protection circuit can be provided.

Therefore, also in this embodiment, an optimum ESD protection element can be provided without increasing new processes.
In the description of the first and second embodiments, the BiMOS process in which the high breakdown voltage transistor is formed of a MOS transistor has been described. However, the same can be realized in the BiCMOS process in which the high breakdown voltage transistor is formed of a CMOS transistor.

  As described above, according to the present invention, in a semiconductor device in which an NPN transistor and a high voltage MOS transistor are formed on one chip, an ESD protection circuit that performs an ESD protection function for the high voltage MOS transistor can be provided. It is useful for a semiconductor integrated circuit manufactured by a process and ESD protected and a method for manufacturing a semiconductor device.

Sectional drawing which shows the semiconductor device in Example 1 of this invention Process sectional drawing explaining the N type impurity layer formation process in Example 1 Process sectional drawing explaining the epitaxial layer formation process in Example 1 Process sectional drawing explaining the well formation process in Example 1 Process sectional drawing explaining the low concentration P type well formation process in Example 1 Process sectional drawing explaining the field oxide film formation process in Example 1 Process sectional drawing explaining the polysilicon gate formation process in Example 1 Process sectional drawing explaining the base diffused layer formation process in Example 1 Process sectional drawing explaining the transistor formation process in Example 1 Sectional drawing which shows the semiconductor device in Example 2 of this invention Process sectional drawing explaining the P-type epitaxial layer growth process in Example 2 Process sectional drawing explaining the N-type well formation process in Example 2 Circuit diagram illustrating ESD protection circuit The figure which shows the current-voltage characteristic of the to-be-protected element by an ESD protection circuit

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 P type substrate 2 P type well 3 Collector layer of low breakdown voltage NPN transistor 4 N type well 6 P type semiconductor layer 7 Emitter diffusion layer 8 Base diffusion layer 10 Drain diffusion layer 11 Body diffusion layer 12 Source diffusion layer 13 Collector contact 14 Base Diffusion layer 15 Emitter diffusion layer 16 Polysilicon gate 17 Field oxide film 18 Bonding pad 19 ESD protection element 20 High voltage MOS transistor element 21 NPN transistor element 22 Collector electrode of ESD protection element 23 Base electrode of ESD protection element 24 ESD protection element of ESD protection element Emitter electrode 25 Resistance 26 Drain electrode of high voltage MOS transistor 27 Gate electrode of high voltage MOS transistor 29 Source electrode of high voltage MOS transistor 30 P-type silicon substrate 31 N-type buried diffusion layer 2 P-type epitaxial layer 34 base diffusion layer 35 the collector layer 38 drain layer 42 collector diffusion layer 43 P-type epitaxial layer 44 base diffusion layer 45 emitter diffusion layer 47 N-type impurity layer 48 N-type epitaxial layer

Claims (5)

A BiMOS type semiconductor device in which a high voltage MOS transistor, an ESD protection element connected in parallel with the high voltage MOS transistor, and a low voltage NPN bipolar transistor are formed on the same substrate,
The ESD protection element has a P-type base diffusion layer formed in the same diffusion process as that for the NPN bipolar transistor, and includes a P-type semiconductor layer in contact with the bottom of the P-type base diffusion layer. A semiconductor device.   The semiconductor device according to claim 1, wherein a diffusion depth of the P-type semiconductor layer is 1.5 times or more larger than a diffusion depth of the P-type base diffusion layer. Forming an N-type buried diffusion layer in a planned formation region where an NPN bipolar transistor, a high voltage MOS transistor and an ESD protection element are scheduled to be formed on a P-type substrate;
Forming an N-type epitaxial layer on the entire surface of the P-type substrate;
Forming a P-type well in an isolation formation scheduled region for isolating the elements in the N-type epitaxial layer and a base formation scheduled region of the ESD protection element;
Forming a field oxide film at predetermined locations on the N-type epitaxial layer and the P-type well;
Forming a body diffusion layer in a body formation scheduled region of the high breakdown voltage MOS transistor in the N-type epitaxial layer;
Forming a polysilicon gate of the high voltage MOS transistor at a predetermined location on the N type epitaxial layer;
Forming a base diffusion layer on the NPN bipolar transistor and the P-type well for the ESD protection element;
And a step of forming an emitter diffusion layer in each of the base diffusion layers. Forming an N-type well in an NPN bipolar transistor region, a high voltage MOS transistor region, and an ESD protection element region on the main surface of the P-type substrate;
Forming a P-type well in a planned isolation region for surrounding and separating each element region and a base formation planned region in the ESD protection element region;
Forming an N-type well in the high-breakdown-voltage MOS transistor region and the ESD protection element region on the main surface of the P-type substrate;
Forming a field oxide film at predetermined locations on the P-type well and the N-type well;
Forming a body diffusion layer on the surface layer of the N-type well of the high voltage MOS transistor;
Forming a polysilicon gate at a predetermined location of the N-type well of the high voltage MOS transistor;
Forming a base diffusion layer on the surface layer of the N-type well of the NPN bipolar transistor and the P-type well of the ESD protection element;
And a step of forming an emitter diffusion layer in each of the base diffusion layers. Forming an N-type buried diffusion layer in the NPN bipolar transistor region, the high voltage MOS transistor region, and the ESD protection element region on the main surface of the P-type substrate;
Forming a P-type epitaxial layer on the entire surface of the P-type substrate and the N-type buried diffusion layer;
Forming an N-type well in the NPN bipolar transistor region, the high breakdown voltage MOS transistor region and the collector region of the ESD protection element in the P-type epitaxial layer;
Forming a field oxide film at predetermined locations on the P-type epitaxial layer and the N-type well;
Forming a body diffusion layer on a surface layer in the high breakdown voltage MOS transistor region in the N-type well;
Forming a polysilicon gate at a predetermined location on the high voltage MOS transistor region in the N-type well;
Forming a base diffusion layer in a surface layer in the NPN bipolar transistor region in the N-type well and in a P-type well of the ESD protection element;
And a step of forming an emitter diffusion layer in each of the base diffusion layers.

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