CN102467977B - Chip fixing pedestal and chip fixed-connection mode - Google Patents
Chip fixing pedestal and chip fixed-connection mode Download PDFInfo
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- CN102467977B CN102467977B CN201010532525.1A CN201010532525A CN102467977B CN 102467977 B CN102467977 B CN 102467977B CN 201010532525 A CN201010532525 A CN 201010532525A CN 102467977 B CN102467977 B CN 102467977B
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Abstract
The invention provides a chip fixing pedestal. The chip fixing pedestal is utilized for temporary failure analysis of a storage chip. The chip fixing pedestal comprises a pedestal, at least one pad zone located on the pedestal and a base located on the pad zone. The base is utilized for supporting a storage chip with storage chip base pins. Pad zone base pins are formed in the least one pad zone, wherein the number of the pad zone base pins which are arranged at the same side is great than or equal to that of the storage chip base pins. The invention also provides a chip fixed-connection mode suitable for the chip fixing pedestal. In the invention, the number of the pad zone base pins which are arranged at the same side is great than or equal to that of the storage chip base pins and thus leads for connecting the storage chip base pins and the pad zone base pins only cover one side of a data storage zone. In temporary failure analysis, the other side of the data storage zone of the storage chip can be completely exposed and thus temporary failure analysis accuracy is improved.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of chip fixed pedestal and be fixedly connected with mode with chip.
Background technology
For storage class chip, temporarily losing efficacy will the reliability of extreme influence data and system works.So can the temporary transient crash rate of effective survey calculation storage chip, the reliability for data and system works be very important.Wherein, accelerating soft error test (alpha particle accelerate soft errorrate) is a kind of method judging that storage chip temporarily lost efficacy, its concrete irradiation by radioactive source alpha particle, worsen the environment for use of storage chip, temporary transient failure analysis is carried out to it, to detect the performance of storage chip.Publication number is that the Chinese patent application of CN 101620254A provides a kind of system and method accelerating soft error test.
Be illustrated in figure 1 storage chip structural representation, comprise chip pin district 02 and the data storage area 011 and 012 being positioned at both sides, described pin district 02.Wherein, described chip pin district 02 has 62 pins.
Fig. 2 is the temporary transient failure analysis schematic diagram of prior art, as shown in Figure 2, storage chip described in Fig. 1 is positioned in the chip fixed pedestal shown in Fig. 2, described chip fixed pedestal comprises base 04, the base station (not shown) being positioned at the pad area 03 on described base 04 and being positioned on described pad area 03, and connected corresponding with the pin of pad area 03 for the pin in the pin district 02 of described storage chip by wire.Then, by radioactive source 05, by alpha particle-irradiation to the surface of described storage chip, to carry out temporary transient failure analysis to described storage chip.
But prior art often causes temporary transient failure analysis result inaccurate.
Summary of the invention
The problem that the present invention solves is to provide a kind of chip fixed pedestal and is fixedly connected with mode with chip, improves the accuracy of temporary transient failure analysis result.
For solving the problem, the invention provides a kind of chip fixed pedestal, for carrying out temporary transient failure analysis to storage chip, comprise: base, at least one pad area be positioned on base, the base station be positioned on pad area, described base station has the storage chip of pin for placing, pad area is formed with pin, and the pad area number of pin being wherein positioned at the same side is more than or equal to storage chip number of pin, is connected to side pad area pin to make storage chip pin correspondence.
Optionally, comprising: be positioned at the first pad area on base, the first pad area number of pin being positioned at the same side is more than or equal to storage chip number of pin, with the first pad area pin making storage chip pin correspondence be connected to side.
Optionally, comprise: be positioned at the first pad area on base and the second pad area successively, the number of pin of the first pad area and the second pad area that are positioned at the same side is more than or equal to storage chip number of pin, with the first pad area and the second pad area pin that make storage chip pin correspondence be connected to side.
Optionally, comprise: be positioned at the first pad area on base, the second pad area and the 3rd pad area successively, the number of pin being positioned at first pad area of the same side, the second pad area and the 3rd pad area is more than or equal to storage chip number of pin, is connected to the first pad area of side, the second pad area and the 3rd pad area pin to make storage chip pin correspondence.
Optionally, the pin of the first pad area and the second pad area is positioned at the same side.
Optionally, the first pad area pin is positioned at the both sides of the first pad area, and the second pad area pin is positioned at the both sides of the second pad area.
Optionally, the pin of the first pad area side is connected with the pin being positioned at the first pad area opposite side, and the pin being positioned at the second pad area side is connected with the pin of the second pad area opposite side.
Optionally, the second pad area pin of the pin and opposite side that are positioned at the first pad area side is connected.
Optionally, the height of described base, the first pad area, the second pad area and base station increases progressively successively, and namely the second pad area is positioned at the upper strata of pedestal, and the first pad area is positioned at the upper strata of the second pad area, and base station is positioned at the upper strata of the first pad area.
The present invention also provides a kind of chip of described chip fixed pedestal to be fixedly connected with mode, for carrying out temporary transient failure analysis to storage chip, comprising:
There is provided storage chip and chip fixed pedestal, and be placed on by described storage chip on the base station of described chip fixed pedestal, described storage chip comprises chip pin district and is positioned at the data storage area of both sides, described pin district;
Be connected with the pad area pin being positioned at side accordingly by the pin in the pin district of described storage chip by wire, described wire is coated with the data storage area being positioned at the same side, and the data storage area of opposite side is not covered by wire.
Optionally, also comprise the surface by radioactive source, radion being incident to described storage chip, to carry out temporary transient failure analysis to described storage chip.
Optionally, described storage chip surface is less than 1mm with the difference in height of radioactive source.
Compared with prior art, the present invention has the following advantages: be positioned at quantity and function that the pad area number of pin of the same side and function at least include storage chip in the present invention, the data storage area only covering side for the wire connected between storage chip pin and pad area pin can be made, when carrying out temporary transient failure analysis, the data storage area of the opposite side of storage chip can be exposed completely, improve the accuracy of temporary transient failure analysis.
Further, described first pad area side pin is connected with the first pad area pin of opposite side, second pad area side pin is connected with opposite side second pad area pin, or can be connected with the second pad area pin of the opposite side be positioned at corresponding thereto by the first pad area side pin.By above-mentioned different pin connected mode, expand described chip fixed pedestal environment for use, can according to testing requirement, dirigibility ground selects the pin of the first pad area and the second pad area both sides to arrange in pairs or groups.
Accompanying drawing explanation
Fig. 1 is the structural representation of storage chip.
Fig. 2 is the temporary transient failure analysis schematic diagram of prior art.
Fig. 3 to Fig. 5 is the chip fixed pedestal schematic diagram of one embodiment of the invention.
Fig. 6 is the chip fixed pedestal schematic diagram of another embodiment of the present invention.
Fig. 7 is the chip fixed pedestal schematic diagram of another embodiment of the present invention.
Fig. 8 to Figure 11 is that the chip of one embodiment of the invention is fixedly connected with mode schematic diagram.
Figure 12 is that the chip of another embodiment of the present invention is fixedly connected with mode schematic diagram.
Embodiment
In prior art, when adopting the test of acceleration soft error to carry out temporary transient failure analysis to storage chip, usually occur that test result is inaccurate.Inventor carries out research to chip fixed pedestal and connected mode thereof and finds, because when adopting alpha particle radioactive source to carry out irradiation test to the memory block of storage chip, should avoid there is coverture on memory block as far as possible, if have coverture, by causing, the memory block of storage chip temporary transient failure testing result is inaccurate.
But as shown in Figure 2, for the data storage area 011 and 012 that will cover with the wire in pin district 02 on storage chip connecting pad area 03, the radiation intensity being incident to data storage area 011 and 012 is then caused greatly to reduce, cannot the memory block actual performance of test storage chip, affect temporary transient failure analysis result.
For solving the problem, inventor provides a kind of chip fixed pedestal, for carrying out temporary transient failure analysis to storage chip, comprise: base, at least one pad area be positioned on base, the base station be positioned on pad area, described base station has the storage chip of pin for placing, pad area is formed with pin, and the pad area number of pin being wherein positioned at the same side is more than or equal to storage chip number of pin, is connected to side pad area pin to make storage chip pin correspondence.
The quantity of the pad area pin of the same side of the present invention is no less than the quantity of storage chip pin, make the pad area pin being positioned at side namely can meet the connection of storage chip pin, wire for connecting pad area pin and storage chip pin is only coated with the data storage area of side, the data storage area of opposite side can be exposed when carrying out temporary transient failure analysis, improve the accuracy of temporary transient failure analysis.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here to implement with multiple, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention.Therefore the present invention is not by the restriction of following public concrete enforcement.
As shown in Figure 3, being the chip fixed pedestal schematic diagram of one embodiment of the invention, comprising: base 100, being positioned at the first pad area 210, second pad area 220 on described base 100 and the base station 300 for placing storage chip successively.Described chip fixed pedestal, by the pin on described base 100, is connected with the testing tool of outside.Described base 100 for have physical strength without electric conductivity moulding material.Described base station 300 is conductive material.Wherein, be positioned at quantity and function that the total number of pin of the pad area of side and function are no less than storage chip, the number of pin of the first pad area 210 and the second pad area 220 that are namely positioned at side is added the quantity being no less than storage chip pin, and the pin function of the first pad area 210 and the second pad area 220 that are positioned at side is added the function at least including storage chip pin.
In the present embodiment, pin for the storage chip tested has 64, so be positioned at the first pad area 210 of side and the number of pin of the second pad area 220 and be 64, the first pad area 210 and the pin function of the second pad area 220 and the pin function one_to_one corresponding of storage chip.In the present embodiment, the pin of described first pad area 210 or the second pad area 220 lays respectively at the first corresponding pad area 210 or the both sides of the second pad area 220, is respectively 32.Wherein, described pin is conductive material.
Be illustrated in figure 4 chip fixed pedestal diagrammatic cross-section of the present invention, comprise: base 100, be positioned at the first pad area 210, second pad area 220 and base station 300 on described base 100 successively.And increase progressively highly successively.
The above-mentioned height design increased progressively successively can make the position of storage chip and the radioactive source that base station 300 is placed closest, and radioactive source particle can not be blocked by the first pad area 210 and the second pad area 220, avoid reducing the radiation intensity be incident on storage chip.
Be illustrated in figure 5 chip fixed pedestal schematic top plan view of the present invention, comprise: base 100, be positioned at the first pad area 210 and the second pad area 220 on described base 100 successively, and be positioned at the base station 300 on described second pad area 220, described base station 300 is for placing storage chip.
Wherein, described first pad area 210 has 64 pins, lays respectively at the both sides of described first pad area 210, and the pin of side is A1, and the pin of opposite side is B1; Described second pad area 220 has 64 pins, lays respectively at the both sides of described second pad area 220, and the pin of side is B2, and the pin of opposite side is A2.Wherein, described pin A2 and pin B1 is positioned at the same side, and described pin B2 and pin A1 is positioned at the same side.In the present embodiment, pin A2 and pin A1 is connection status, is connected with pin A1 while being namely connected with pin A2; Pin B2 and pin B1 is connection status, is connected with pin B1 while being namely connected with pin B2, and described connection is positioned at the inside of the first pad area 210 and the second pad area 220, and this figure is not shown.As other embodiments, pin A2 and pin B2 is connection status, is connected with pin B2 while being namely connected with pin A2; Pin B 1 and pin A1 is connection status, is connected with pin A1 while being namely connected with pin B1.By said structure, the collocation between pin can be realized more flexibly.
Identical with the quantity of the pin of storage chip respectively with the pin of the second pad area 220 by the first pad area 210, and lay respectively at the both sides of described first pad area 210 or the second pad area 220, the wire of storage chip pin and the first pad area 210 and the second pad area 220 can be made to be positioned at the same side, and described wire only covers the data storage area of the side of storage chip; During temporary transient failure analysis, the data storage area of the opposite side of storage chip can be exposed completely, improve the accuracy of temporary transient failure analysis.
The described pin of the first pad area 210 side is connected with the pin of the first pad area 210 of opposite side simultaneously, the described pin of the second pad area 220 side is connected with the pin of the second pad area 220 of opposite side, or can be connected with the pin of the second pad area 220 of the opposite side be positioned at corresponding thereto by the pin of the first pad area 210 side.By above-mentioned different pin connected mode, expand described chip fixed pedestal environment for use, can according to testing requirement, dirigibility ground selects the pin of the first pad area and the second pad area both sides to arrange in pairs or groups.
In the present embodiment, the pin of described first pad area 210 and the second pad area 220 lays respectively at the both sides of described first pad area 210 and the second pad area 220.As other embodiments, the pin of described first pad area 210 only can be positioned at the side of described first pad area 210, and similarly, the pin of described second pad area 220 also only can be positioned at the side of described second pad area 220.
In the present embodiment, the quantity of described pad area is 2, as other embodiments, also can be other quantity, meets the quantity and the function that are positioned at the quantity of the pad area pin of side and function and are no less than storage chip simultaneously.
As shown in Figure 6, for the chip fixed pedestal structural representation of another embodiment of the present invention, comprise: base 100, be positioned at the first pad area 210a on described base 100, and the base station 300 be positioned on described first pad area 210a, described base station 300 is for placing storage chip, and the number of pin being positioned at the first pad area 210a of the same side is more than or equal to storage chip number of pin, with the first pad area 210a pin making storage chip pin correspondence be connected to side.As other embodiments, the both sides of described first pad area 210a have the pin of some, meet the number of pin being positioned at the first pad area 210a of the same side simultaneously and are more than or equal to storage chip number of pin.
As shown in Figure 7, for the chip fixed pedestal structural representation of another embodiment of the present invention, comprise: base 100, be positioned at the first pad area 210b on described base 100 successively, second pad area 220b and the 3rd pad area 230b, and the base station 300 be positioned on described 3rd pad area 230b, described base station 300 is for placing storage chip, be positioned at the first pad area 210b of the same side, the number of pin of the second pad area 220b and the 3rd pad area 230b and be more than or equal to storage chip number of pin, with the pad area pin making storage chip pin correspondence be connected to side, comprise the first pad area 210b, the pin of the second pad area 220b and the 3rd pad area 230b.As other embodiments, the both sides of described first pad area 210b, the second pad area 220b and the 3rd pad area 230b have the pin of some, and the number of pin simultaneously meeting the first pad area 210b, the second pad area 220b and the 3rd pad area 230b that are positioned at the same side is more than or equal to storage chip number of pin.
Below in conjunction with described chip fixed pedestal of the present invention, the connected mode of described chip fixed pedestal of the present invention is described, comprise: storage chip and chip fixed pedestal are provided, and described storage chip being placed on the base station of described chip fixed pedestal, described storage chip comprises chip pin district and is positioned at the data storage area of both sides, described pin district; Be connected with the pad area pin being positioned at side accordingly by the pin in the pin district of described storage chip by wire, described wire is coated with the data storage area being positioned at the same side, and the data storage area of opposite side is not covered by wire.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
First, as shown in Figure 1, provide storage chip, described storage chip comprises chip pin district 02 and is positioned at the data storage area 011 and 012 of both sides, described pin district 02.
As shown in Figure 5, chip fixed pedestal being provided, comprising: base 100, being positioned at the first pad area 210, second pad area 220 on described base 100 and the base station 300 for placing storage chip successively.Its concrete structure can with reference to aforementioned.
As shown in Figure 8, described storage chip is positioned in chip fixed pedestal, particularly, is positioned on described base station 300.Wherein, the region close with side first pad area 210 is data storage area 011, and the region close with opposite side first pad area 210 is data storage area 012.
As shown in Figure 9, be connected corresponding with the pin district 02 of described storage chip for the side pin A2 of the second pad area 220 by wire, the side pin A2 of described second pad area 220 has 32 pins.
As shown in Figure 10, be connected corresponding with the pin district 02 of described storage chip for the side pin B1 of the first pad area 210 by wire, the side pin B1 of described first pad area 210 has 32 pins.
In the present embodiment, the side pin B1 of the first pad area 210 is selected to be connected with the pin district 02 of described storage chip with the side pin A2 of the second pad area 220, as other embodiments, the pin A1 of the first pad area 210 also can be selected to be connected with the pin district 02 of described storage chip with the side pin B2 of the second pad area 220.
Wherein, in this enforcement, the pin A1 of the first pad area 210 and pin A2 of the second pad area 220 is connection status; The pin B1 of the first pad area 210 and pin B2 of the second pad area 220 is connection status.So select arbitrarily to connect the pin being positioned at side, be connected with all simultaneously and be positioned at pin corresponding to opposite side.As other embodiments, can also the pin A1 of the first pad area 210 and pin B1 of the first pad area 210 be connection status; The pin B2 of the second pad area 220 and pin A2 of the second pad area 220 is connection status.
As shown in figure 11, by alpha particle radioactive source 500, radion is incident to the surface of described storage chip, to carry out temporary transient failure analysis to described storage chip.Wherein, described storage chip surface is less than 1mm with the difference in height of penetrating source.In the present embodiment, the half memory block 012 of described storage chip is completely outside exposed, is conducive to penetrating of radioactive source, provides the reliability of temporary transient failure analysis result.
As shown in figure 12, for another embodiment of the present invention, the chip fixed pedestal that it provides and the mode that is fixedly connected with of chip identical with previous embodiment, difference is: the region close with side first pad area 210 includes data storage area 011,012 and pin district 02 simultaneously.By connected mode same as the previously described embodiments, the wire for connecting can be made only to be coated with pin district 02, do not cover the data storage area 011 and 012 being positioned at both sides, described pin district 02, maximum possible makes described data storage area 011 and 012 be exposed to below radioactive source, be conducive to penetrating of radioactive source, the reliability of temporary transient failure analysis result is provided.
Compared with prior art, the present invention has the following advantages: be positioned at quantity and function that the pad area number of pin of the same side and function at least include storage chip in the present invention, the data storage area only covering side for the wire connected between storage chip pin and pad area pin can be made, when carrying out temporary transient failure analysis, the data storage area of the opposite side of storage chip can be exposed completely, improve the accuracy of temporary transient failure analysis.
Further, described first pad area side pin is connected with the first pad area pin of opposite side, second pad area side pin is connected with opposite side second pad area pin, or can be connected with the second pad area pin of the opposite side be positioned at corresponding thereto by the first pad area side pin.By above-mentioned different pin connected mode, expand described chip fixed pedestal environment for use, can according to testing requirement, dirigibility ground selects the pin of the first pad area and the second pad area both sides to arrange in pairs or groups.
Set forth detail in the above description so that fully understand the present invention.But the present invention can be different from alternate manner described here to implement with multiple, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention.Therefore the present invention is not by the restriction of following public concrete enforcement.
Claims (12)
1. a chip fixed pedestal, for carrying out temporary transient failure analysis to storage chip, it is characterized in that, comprise: base, be positioned at least one pad area on base, be positioned at the base station on pad area, described base station is for placing the storage chip for testing, described storage chip has chip pin district and is positioned at the data storage area of both sides, described chip pin district, the pad area surface of base station both sides is formed with pin, wherein, the described pin of pad area side is connected with the pin of opposite side, and wherein the pad area number of pin of side and function are more than or equal to storage chip number of pin and function to be positioned at base station, this side pad area pin is connected to make storage chip pin correspondence, at least expose the data storage area of side.
2. chip fixed pedestal according to claim 1, it is characterized in that, comprise: be positioned at the first pad area on base, the first pad area number of pin being positioned at the same side is more than or equal to storage chip number of pin, with the first pad area pin making storage chip pin correspondence be connected to side.
3. chip fixed pedestal according to claim 1, it is characterized in that, comprise: be positioned at the first pad area on base and the second pad area successively, the number of pin of the first pad area and the second pad area that are positioned at the same side is more than or equal to storage chip number of pin, with the first pad area and the second pad area pin that make storage chip pin correspondence be connected to side.
4. chip fixed pedestal according to claim 1, it is characterized in that, comprise: be positioned at the first pad area on base, the second pad area and the 3rd pad area successively, the number of pin being positioned at first pad area of the same side, the second pad area and the 3rd pad area is more than or equal to storage chip number of pin, is connected to the first pad area of side, the second pad area and the 3rd pad area pin to make storage chip pin correspondence.
5. chip fixed pedestal according to claim 3, it is characterized in that, the pin of the first pad area and the second pad area is positioned at the same side.
6. chip fixed pedestal according to claim 3, it is characterized in that, the first pad area pin is positioned at the both sides of the first pad area, and the second pad area pin is positioned at the both sides of the second pad area.
7. chip fixed pedestal according to claim 6, it is characterized in that, the pin of the first pad area side is connected with the pin being positioned at the first pad area opposite side, and the pin being positioned at the second pad area side is connected with the pin of the second pad area opposite side.
8. chip fixed pedestal according to claim 6, it is characterized in that, the second pad area pin of the pin and opposite side that are positioned at the first pad area side is connected.
9. chip fixed pedestal according to claim 1, it is characterized in that, the height of described base, the first pad area, the second pad area and base station increases progressively successively, namely the first pad area is positioned at the upper strata of base, second pad area is positioned at the upper strata of the first pad area, and base station is positioned at the upper strata of the second pad area.
10. the chip of chip fixed pedestal as claimed in claim 1 is fixedly connected with a mode, for carrying out temporary transient failure analysis to described chip, it is characterized in that, comprising:
Be provided for storage chip and the chip fixed pedestal of test, and described storage chip is placed on the base station of described chip fixed pedestal, described storage chip comprises chip pin district and is positioned at the data storage area of both sides, described pin district, described chip fixed pedestal comprises base and is positioned at the pad area on described base, the described pin of pad area side is connected with the pin of opposite side, and described base station wherein the number of pin of the pad area of side and function are more than or equal to storage chip number of pin and function;
Be connected with the pad area pin being positioned at base station side accordingly by the pin in the pin district of described storage chip by wire, described wire is coated with the data storage area being positioned at base station the same side, and the data storage area of base station opposite side is not covered by wire.
11. according to claim 10 chip be fixedly connected with mode, it is characterized in that, also comprise the surface by radioactive source, radion being incident to described storage chip, to carry out temporary transient failure analysis to described storage chip.
12. are fixedly connected with mode according to chip described in claim 11, it is characterized in that, described storage chip surface is less than 1mm with the difference in height of penetrating source.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201010532525.1A CN102467977B (en) | 2010-11-01 | 2010-11-01 | Chip fixing pedestal and chip fixed-connection mode |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201010532525.1A CN102467977B (en) | 2010-11-01 | 2010-11-01 | Chip fixing pedestal and chip fixed-connection mode |
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| CN102467977A CN102467977A (en) | 2012-05-23 |
| CN102467977B true CN102467977B (en) | 2015-04-01 |
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| JP2000011693A (en) * | 1998-06-26 | 2000-01-14 | Advantest Corp | Apparatus and method for transfer of data as well as apparatus and method for test of memory device |
| CN100544546C (en) * | 2005-10-27 | 2009-09-23 | 鸿富锦精密工业（深圳）有限公司 | Printed circuit board (PCB) |
| CN101206179B (en) * | 2006-12-22 | 2010-08-11 | 中芯国际集成电路制造(上海)有限公司 | Light emission microscope sample |
| US7872483B2 (en) * | 2007-12-12 | 2011-01-18 | Samsung Electronics Co., Ltd. | Circuit board having bypass pad |
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