CN102467967A - Read circuit and read method for electrically erasable read-only memory - Google Patents
Read circuit and read method for electrically erasable read-only memory Download PDFInfo
- Publication number
- CN102467967A CN102467967A CN2010105418434A CN201010541843A CN102467967A CN 102467967 A CN102467967 A CN 102467967A CN 2010105418434 A CN2010105418434 A CN 2010105418434A CN 201010541843 A CN201010541843 A CN 201010541843A CN 102467967 A CN102467967 A CN 102467967A
- Authority
- CN
- China
- Prior art keywords
- storage unit
- voltage
- read
- threshold voltage
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 16
- 230000007935 neutral effect Effects 0.000 claims abstract description 13
- 238000003860 storage Methods 0.000 claims description 101
- 238000012795 verification Methods 0.000 claims description 62
- 238000012937 correction Methods 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 230000000694 effects Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 239000000758 substrate Substances 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 208000004350 Strabismus Diseases 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Images
Landscapes
- Read Only Memory (AREA)
Abstract
A sensing circuit and a sensing method for an electrically erasable read-only memory, the sensing circuit includes a comparator, a reference resistor, a sensing resistor, a reference cell and a memory cell, only one reference cell needs to be configured in the sensing circuit, the same reference cell is utilized in the process of reading, the threshold voltage of the reference cell is set as the neutral threshold voltage, the voltage on the control grid of the reference cell is also set as a fixed value, thereby significantly reducing the configuration time during the manufacturing process, while the threshold value applied to the control gate of the memory cell varies with the operating mode, and, at the same time, since the voltages applied to the control gates of the memory cells during the read operation and the program verify operation are lower than those of the prior art, the gate voltage stress effect is reduced and the threshold voltage of the reference cell is set near the neutral threshold voltage, making the threshold voltage of the reference cell more stable.
Description
Technical field
The present invention relates to a kind of sensing circuit and reading method that is used for the electrically-erasable ROM (read-only memory).
Background technology
Conventional Flash EEPROM (electrically-erasable ROM (read-only memory)) comprises some storage unit.This storage unit is made on the P-type semiconductor substrate, and each unit comprises the drain terminal of a n+ type and the source end of a n+ type.The gate dielectric layer that one deck relative thin is arranged on the substrate, on be the floating boom that polysilicon forms.Being second layer dielectric layer on floating boom, is the control gate that polysilicon forms on the second layer dielectric layer.Channel region on the substrate is kept apart the source drain terminal.
The quantity of electric charge on the floating boom is by the number of electrons decision that is comprised in the floating boom.When programming, electronics is injected in the floating boom, thereby has improved the threshold voltage of storage unit.Threshold voltage is instigated the minimum voltage between needed control gate of memory cell conducts and the source end.When wiping, the electronics in the floating boom is removed, thereby reduces the threshold voltage of storage unit.Under programming state, the threshold voltage of storage unit is usually greater than+6.5V, and under erase status, and the threshold voltage of storage unit is usually less than+3.0V.
For confirming whether storage unit is programmed, add on the control gate one between+3.0V to the voltage the between+6.5V, normally+5.0V, the source end adds 0V, drain terminal adds the voltage between the 1V-2V.If memory cell conducts, electric current can flow through between the source leakage of storage unit, represent that this unit is in erase status, preserved data " 1 "; Otherwise, represent that then this unit is in programming state, preserved data " 0 ".
Fig. 1 is the simplification functional block diagram of a conventional FLASH storer.100 is semiconductor memery circuits of a routine, comprises that storage array 102,102 is made up of some storage unit MC11-MCnm.MC11-MCnm is arranged in the matrix of n * m in circuit.Each storage unit comprises a transistor (Qp11-Qpnm), and transistor is used for preserving data " 0 " or " 1 ".One among each transistorized drain terminal and the bit line BL0-BLm-1 links to each other the identical common ground potential VSS of source termination of all crystals pipe.One among each transistorized control gate and the word line WL0-WLn-1 links to each other.Memory circuitry 100 also comprises line decoder 104, column decoder 106, and Y transmission circuit 108.Line decoder 104 is chosen a corresponding word line according to row address signal Ai from WL0-WLn-1, and column decoder is chosen a corresponding bit lines according to column address signal Aj from BL0-BLm-1.Y transmission circuit 108 with bit line selected in the array with read or sensing circuit 110 links to each other.
Comprise a sensor amplifier in the sensing circuit 110, this sensor compares electric current and the reference current on the word line, and what the memory cell that the comparative result indication of sensor is chosen was preserved is " 0 " or " 1 ".
Fig. 2 is the schematic diagram of sensing circuit 110.Comprise a comparer 120 in the circuit, resistance is the reference resistance 122 of R2, the sensing resistor 124 that resistance is R1, the transistor Q of storage unit
P, and the transistor Q of reference unit
R1-Q
R4
One end of reference resistance 122 links to each other with a voltage source V CC, and the exemplary voltages value is 1.0V, and the other end links to each other at node A with the in-phase input end of comparer 120.Node A is through reference unit line REF and switch S 1-S4 and reference transistor Q
R1-Q
R4Drain terminal link to each other.One end of sensing resistor 124 links to each other with voltage source V CC, and the other end links to each other at node B with the inverting input of comparer 120.Node B is through selected bit line BL and memory transistor Q
PDrain terminal link to each other.Q
PAnd Q
R1-Q
R4Control gate all be connected to selected word line WL, accept identical control-grid voltage VG_SENSE.
When carrying out read operation, switch S 1 conducting, the electric current I CELL of storage unit with from Q
R1Electric current I REF compare.
When programming verification operation, switch S 2 conductings, the electric current I CELL of storage unit with from Q
R2Electric current I REF compare.
When wiping verification operation, switch S 3 conductings, the electric current I CELL of storage unit with from Q
R3Electric current I REF compare.
When carrying out wiping verification operation, switch S 4 conductings, the electric current I CELL of storage unit with from Q
R4Electric current I REF compare.
Q
R1Threshold voltage be RD_VT, Q
R2Threshold voltage be PGM_VT, Q
R3Threshold voltage be ERS_VT, Q
R4Threshold voltage be OEC_VT.Relation below these threshold voltages satisfy:
OEC_VT?<?ERS_VT?<?RD_VT?<?PGM_VT
Provided Q in the reference unit among Fig. 3
R1-Q
R4Reference current and control-grid voltage V
GCurve map.Because reference transistor is identical with memory transistor, so IDS curve A-D is parallel, also is parallel with the IDS curve of memory transistor.The difference of curve A-D is because different threshold voltages causes.
When carrying out read operation, switch S 1 conducting, Q
PAnd Q
R1Control gate making alive VG_SENSE all.Comparer 120 is relatively from the electric current I CELL of memory transistor with from Q
R1Reference current RD_IREF.If ICELL is greater than RD_IREF, then comparer 120 is exported " 1 ", on the contrary output " 0 ".
When programming verification, switch S 2 conductings, Q
PAnd Q
R2Control gate making alive VG_SENSE all.Comparer 120 is relatively from the electric current I CELL of memory transistor with from Q
R2Reference current PGM_IREF.If ICELL is less than ERS_IREF, Q is indicated in then comparer 120 outputs " 0 "
PThrough the programming verification.
When wiping verification, switch S 3 conductings, Q
PAnd Q
R3Control gate making alive VG_SENSE all.Comparer 120 is relatively from the electric current I CELL of memory transistor with from Q
R3Reference current ERS_IREF.If ICELL is greater than ERS_IREF, Q is indicated in then comparer 120 outputs " 1 "
PThrough wiping verification.
When carrying out wiping verification, switch S 4 conductings, Q
PAnd Q
R4Control gate making alive VG_SENSE all.Comparer 120 is relatively from the electric current I CELL of memory transistor with from Q
R2Reference current OEC_IREF.If ICELL is less than OEC_IREF, Q is indicated in then comparer 120 outputs " 0 "
PWipe verification through crossing.
Prior art has some defectives:
For verification that the FLASH storage array is read, programmed, wipe verification and cross and wipe verification, need be to 4 reference unit Q
R1-Q
R4Threshold voltage be configured.This layoutprocedure need be carried out programming-checking procedure repeatedly to reference unit, reaches the threshold value that needs up to reference unit.Therefore layoutprocedure consumes the more time, has increased cost.
2. because the programming verification is wiped the used reference unit Q of verification with crossing
R2And Q
R4Threshold value and the neutral threshold value UV_VT (threshold value when neutral threshold value refers to not have electric charge in floating the deleting of storage unit; Neutral threshold value changes with manufacturing process; The representative value of NOR type Flash storer possibly be distributed between the 2.3-3.5V) deviation bigger; Therefore electric charge takes place under the situation of disturbance easily losing existing, thereby causes threshold value to squint, and then threshold distribution and the data holding time of influence after programming.
Summary of the invention
A kind of sensing circuit and reading method that is used for the electrically-erasable ROM (read-only memory) provided by the invention reduced the setup time in the manufacture process, improved the threshold voltage stability of reference unit.
In order to achieve the above object, the present invention provides a kind of sensing circuit that is used for the electrically-erasable ROM (read-only memory), and this sensing circuit comprises comparer, reference resistance, and sensing resistor, the resistance of said reference resistance and sensing resistor is identical.
This sensing circuit also comprises reference unit and storage unit.
One termination voltage source of reference resistance, the other end links to each other with the in-phase input end of comparer at the datum node place.Datum node links to each other with the drain electrode end of reference unit through reference bit lines.One termination voltage source of sensing resistor, the other end links to each other with the inverting input of comparer at the storage node place.Storage node links to each other with the drain electrode end of storage unit through selected bit line.
The threshold voltage V of reference unit
TRBe adjusted near neutral threshold voltage UV_VT.
The voltage that is added on the reference unit control gate is a fixed voltage RVG.
It is different being added in voltage VG_SENSE on the storage unit control gate next in the different working pattern.
1, when carrying out read operation, makes VG_SENSE=VG_RD;
2, when wiping verification operation, make VG_SENSE=VG_ERS;
3, when programming verification operation, make VG_SENSE=VG_PGM;
4, when carrying out clashing verification operation, make VG_SENSE=VG_OEC.
Relation below above-mentioned 4 magnitudes of voltage satisfy:
VG_OEC?<?VG_ERS?<?VG_RD?<?VG_PGM
VG_OEC is by crossing the storage unit targets threshold decision wipe after the correction; VG_ERS is determined by the storage unit targets threshold after wiping; VG_PGM is by the storage unit targets threshold decision after programming; The decision threshold decision of VG_RD during by read operation.
The present invention also provides a kind of reading method that is used for the electrically-erasable ROM (read-only memory), and the method includes the steps of:
This threshold voltage V
TRBe adjusted near neutral threshold voltage UV_VT.
Step 2, the voltage RVG on the reference unit control gate is set;
This magnitude of voltage RVG is set to fixed value.
Step 3, the voltage VG_SENSE on the storage unit control gate is set.
Step 3.1, four magnitude of voltage VG_OEC, VG_ERS, VG_RD, VG_PGM are set, relation below above-mentioned 4 magnitudes of voltage satisfy:
VG_OEC?<?VG_ERS?<?VG_RD?<?VG_PGM。
VG_OEC is by crossing the storage unit targets threshold decision wipe after the correction; VG_ERS is determined by the storage unit targets threshold after wiping; VG_PGM is by the storage unit targets threshold decision after programming; The decision threshold decision of VG_RD during by read operation.
Step 3.2, when carrying out read operation, make VG_SENSE=VG_RD.
Step 3.3, when wiping verification operation, make VG_SENSE=VG_ERS.
Step 3.4, when programming verification operation, make VG_SENSE=VG_PGM.
Step 3.5, when carrying out clashing verification operation, make VG_SENSE=VG_OEC.
Which kind of operation step 4.1, judgement electrically-erasable ROM (read-only memory) are in, if wipe verification operation, then jump to step 4.2; If programme verification operation; Then jump to step 4.3,, then jump to step 4.4 if carried out wiping verification operation; If carry out read operation, then jump to step 4.5.
If step 4.2 storage unit (Q
C) threshold voltage V
TC<vG_ERS – RVG+V
TR, then through wiping verification.
If step 4.3 storage unit (Q
C) threshold voltage V
TC>VG_PGM – RVG+V
TR, then through the programming verification.
If step 4.4 storage unit (Q
C) threshold voltage V
TC>VG_OEC – RVG+V
TR, then wipe verification through crossing.
If step 4.5 storage unit (Q
C) threshold voltage V
TC>VG_RD – RVG+V
TR, then sense data is 0, on the contrary sense data is 1.
The present invention is carrying out read operation, the verification operation of programming, is wiping verification operation and cross in the process wipe verification operation and utilized same reference unit; And the voltage on the reference unit control gate also is a fixed value; Therefore only need reference unit of configuration; Thereby significantly reduced the setup time in the manufacture process, and be added in threshold value on the storage unit control gate with operational mode change, simultaneously; Technology was lower relatively in the past because read operation and programming are added in voltage on the storage unit control gate during verification operation; Therefore the gate voltage stress effect reduces, and the threshold voltage of reference unit is set near the neutral threshold voltage, makes that the threshold voltage of reference unit is more stable.
Description of drawings
Fig. 1 is the simplification functional block diagram of conventional FLASH storer in the background technology.
Fig. 2 is the schematic diagram of sensing circuit in the background technology.
Fig. 3 is the curve map (SQRT is a square root, and IDS is the source-drain current of unit under test, and SQRT (IDS) is exactly the square root of unit under test source-drain current) of the reference current of QR1-QR4 and control-grid voltage VG in the reference unit in the background technology.
Fig. 4 is the circuit diagram that is used for the sensing circuit of electrically-erasable ROM (read-only memory) provided by the invention.
Fig. 5 is the graph of a relation of reference current IREF in the sensing circuit provided by the invention, memory cell current ICELL and control-grid voltage VG.
Embodiment
Following according to Fig. 4 and Fig. 5, specify preferred embodiment of the present invention:
As shown in Figure 4, be the circuit diagram that is used for the sensing circuit of electrically-erasable ROM (read-only memory) provided by the invention, this sensing circuit comprises comparer 420, and resistance is the reference resistance 412 of R402, and resistance is the sensing resistor 414 of R401, R402=R401.
This sensing circuit also comprises reference unit Q
RWith storage unit Q
C
One termination voltage source VCC of reference resistance 412, the representative value of VCC are+1.0V that the other end links to each other with the in-phase input end of comparer 420 at datum node Y place.Datum node Y is through reference bit lines REF and reference unit Q
RDrain electrode end link to each other.One end of sensing resistor 414 links to each other with VCC, and the other end links to each other with the inverting input of comparer 420 at storage node X place.Storage node X is through selected bit line BL and storage unit Q
CDrain electrode end link to each other.
Different with background technology shown in Figure 2, the transistor Q in the reference unit
R1-Q
R4By a reference unit Q
RReplace.
Reference unit Q
RThreshold voltage V
TRBe adjusted near neutral threshold voltage UV_VT, value is 3.0V, and is therefore highly stable.
Be added in reference unit Q
RVoltage on the control gate is a fixed voltage RVG, and value is 3.5V.
Be added in storage unit Q
CVoltage VG_SENSE on the control gate is next in the different working pattern to be different.
1, when carrying out read operation, makes VG_SENSE=VG_RD;
2, when wiping verification operation, make VG_SENSE=VG_ERS;
3, when programming verification operation, make VG_SENSE=VG_PGM;
4, when carrying out clashing verification operation, make VG_SENSE=VG_OEC.
Relation below above-mentioned 4 magnitudes of voltage satisfy:
VG_OEC?<?VG_ERS?<?VG_RD?<?VG_PGM。
VG_OEC is by crossing the storage unit targets threshold decision wipe after the correction, crosses the storage unit targets threshold wiped after the correction greater than 0V such as hope, and then VG_OEC can get 0+RVG-V
TRBetween; VG_ERS is determined that by the storage unit targets threshold after wiping the storage unit targets threshold after wiping such as hope is less than 3.2V, and then VG_ERS can get 3.2+RVG-V
TRVG_PGM is by the storage unit targets threshold decision after programming, and greater than 6.2V, then VG_PGM can get 6.2+RVG-V such as the storage unit targets threshold after the hope programming
TRThe decision threshold decision of VG_RD during by read operation is 4.7V such as getting decision threshold, and when the threshold value of storage unit during less than 4.7V, sense data is 1, and when the threshold value of storage unit during greater than 4.7V, sense data is 0, and this moment, VG_RD can be set to 4.7+RVG-V
TR
Desirable VG_RD=4.4V, VG_ERS=3.8V, VG_PGM=6.5V, VG_OEC=0.7V.
The present invention also provides a kind of reading method that is used for the electrically-erasable ROM (read-only memory), and the method includes the steps of:
This threshold voltage V
TRBe adjusted near neutral threshold voltage UV_VT.
Neutral threshold voltage UV_VT can change with manufacturing process, possibly between 2.5-3.5V, fluctuate.So V
TRCan be arranged on the central value of fluctuation range, value is 3.0V.
Step 2, reference unit Q is set
RVoltage RVG on the control gate;
This magnitude of voltage RVG is set to fixed value.
The value of RVG is than threshold voltage V
TRSlightly high, such as about high 0.5V, value is 3.5V.
Step 3, storage unit Q is set
CVoltage VG_SENSE on the control gate.
Step 3.1, four magnitude of voltage VG_OEC, VG_ERS, VG_RD, VG_PGM are set, relation below above-mentioned 4 magnitudes of voltage satisfy:
VG_OEC?<?VG_ERS?<?VG_RD?<?VG_PGM。
VG_OEC is by crossing the storage unit targets threshold decision wipe after the correction, crosses the storage unit targets threshold wiped after the correction greater than 0V such as hope, and then VG_OEC can get 0+RVG-V
TRBetween; VG_ERS is determined that by the storage unit targets threshold after wiping the storage unit targets threshold after wiping such as hope is less than 3.2V, and then VG_ERS can get 3.2+RVG-V
TRVG_PGM is by the storage unit targets threshold decision after programming, and greater than 6.2V, then VG_PGM can get 6.2+RVG-V such as the storage unit targets threshold after the hope programming
TRThe decision threshold decision of VG_RD during by read operation is 4.7V such as getting decision threshold, and when the threshold value of storage unit during less than 4.7V, sense data is 1, and when the threshold value of storage unit during greater than 4.7V, sense data is 0, and this moment, VG_RD can be set to 4.7+RVG-V
TR
Step 3.2, when carrying out read operation, make VG_SENSE=VG_RD.
Step 3.3, when wiping verification operation, make VG_SENSE=VG_ERS.
Step 3.4, when programming verification operation, make VG_SENSE=VG_PGM.
Step 3.5, when carrying out clashing verification operation, make VG_SENSE=VG_OEC.
Which kind of operation step 4.1, judgement electrically-erasable ROM (read-only memory) are in, if wipe verification operation, then jump to step 4.2; If programme verification operation; Then jump to step 4.3,, then jump to step 4.4 if carried out wiping verification operation; If carry out read operation, then jump to step 4.5.
If step 4.2 storage unit (Q
C) threshold voltage V
TC<vG_ERS – RVG+V
TR, then through wiping verification.
When wiping verification operation, be added in storage unit Q
CVoltage VG_SENSE=VG_ERS on the control gate.Flow through reference unit Q
RElectric current I REF be 501 among Fig. 5.When satisfying VG_ERS-V
TC>RVG-V
TRThe time, flow through storage unit Q
CElectric current I CELL be 502 among Fig. 5, greater than IREF, 418 outputs " 1 " of the output terminal of comparer 420, the indication storage unit is an erase status, otherwise, when not satisfying VG_ERS-V
TC>RVG-V
TRThe time, flow through storage unit Q
CElectric current I CELL be 503 among Fig. 5, less than IREF, 418 outputs " 0 " of the output terminal of comparer 420.Therefore, has only the V of working as
TC<vG_ERS – RVG+V
TRThe time, storage unit could be through wiping verification.
If step 4.3 storage unit (Q
C) threshold voltage V
TC>VG_PGM – RVG+V
TR, then through the programming verification.
When programming verification operation, be added in the voltage VG_SENSE=VG_PGM on the storage unit control gate.Flow through reference unit Q
RElectric current I REF be 501 among Fig. 5.When satisfying VG_PGM-V
TC<rVG-V
TRThe time, flow through storage unit Q
CElectric current I CELL be 503 among Fig. 5, less than IREF, 418 outputs " 0 " of the output terminal of comparer 420, the indication storage unit is a programming state; Otherwise, when not satisfying VG_PGM-V
TC<rVG-V
TRThe time, flow through storage unit Q
CElectric current I CELL be 502 among Fig. 5, greater than IREF, 418 outputs " 1 " of the output terminal of comparer 420.Therefore, has only the V of working as
TC>VG_PGM – RVG+V
TRThe time, storage unit could be passed through the programming verification.
If step 4.4 storage unit (Q
C) threshold voltage V
TC>VG_OEC – RVG+V
TR, then wipe verification through crossing.
When carrying out wiping verification operation, be added in the voltage VG_SENSE=VG_OEC on the storage unit control gate.Flow through reference unit Q
RElectric current I REF be 501 among Fig. 5.When satisfying VG_OEC-V
TC<rVG-V
TRThe time, flow through storage unit Q
CElectric current I CELL be 503 among Fig. 5, less than IREF, 418 outputs " 0 " of the output terminal of comparer 420, the indication storage unit is mistake erase status not; Otherwise, when not satisfying VG_OEC-V
TC<rVG-V
TRThe time, the electric current I CELL that flows through storage unit QC is for 502 among Fig. 5, and greater than IREF, the output terminal 418 of comparer 420 is exported " 1 ".Therefore, has only the V of working as
TC>VG_OEC – RVG+V
TRThe time, storage unit could be wiped the programming verification through crossing.
If step 4.5 storage unit (Q
C) threshold voltage V
TC>VG_RD – RVG+V
TR, then sense data is 0, on the contrary sense data is 1.
When carrying out read operation, be added in the voltage VG_SENSE=VG_RD on the storage unit control gate.Flow through reference unit Q
RElectric current I REF be 501 among Fig. 5.
If storage unit is through wiping verification, V then
TC<vG_ERS – RVG+V
TR, so VG_RD-V
TC>RVG-V
TR, the electric current I REF that flows through storage unit this moment is for 502 among Fig. 5, and greater than IREF, the output terminal 418 of comparer 420 is exported " 1 ", and the data that indication is preserved are " 1 ".
If storage unit is through programming verification, then V
TC>VG_PGM – RVG+V
TR, so VG_RD-V
TC<rVG-V
TR, the electric current I REF that flows through storage unit this moment is for 503 among Fig. 5, and less than IREF, the output terminal 418 of comparer 420 is exported " 0 ", and the data that indication is preserved are " 0 ".
Although content of the present invention has been done detailed introduction through above-mentioned preferred embodiment, will be appreciated that above-mentioned description should not be considered to limitation of the present invention.After those skilled in the art have read foregoing, for multiple modification of the present invention with to substitute all will be conspicuous.Therefore, protection scope of the present invention should be limited appended claim.
Claims (10)
1. a sensing circuit that is used for the electrically-erasable ROM (read-only memory) is characterized in that, this sensing circuit comprises comparer (420), reference resistance (412), and sensing resistor (414), this sensing circuit also comprises reference unit (Q
R) and storage unit (Q
C);
One termination voltage source (VCC) of reference resistance (412), the other end is located to link to each other with the in-phase input end of comparer (420) in datum node (Y), and datum node (Y) is through reference bit lines (REF) and reference unit (Q
R) drain electrode end link to each other, a termination voltage source (VCC) of sensing resistor (414), the other end is located to link to each other with the inverting input of comparer (420) at storage node (X), storage node (X) is through selected bit line (BL) and storage unit (Q
C) drain electrode end link to each other.
2. the sensing circuit that is used for the electrically-erasable ROM (read-only memory) as claimed in claim 1 is characterized in that, said reference resistance (412) is identical with the resistance of sensing resistor (414).
3. the sensing circuit that is used for the electrically-erasable ROM (read-only memory) as claimed in claim 1 is characterized in that, said reference unit (Q
R) threshold voltage (V
TR) be adjusted near neutral threshold voltage (UV_VT).
4. the sensing circuit that is used for the electrically-erasable ROM (read-only memory) as claimed in claim 1 is characterized in that, is added in reference unit (Q
R) voltage on the control gate is a fixed voltage (RVG).
5. the sensing circuit that is used for the electrically-erasable ROM (read-only memory) as claimed in claim 4 is characterized in that, the described reference unit (Q that is added in
R) fixed voltage value (RVG) on the control gate is than threshold voltage (V
TR) height.
6. the sensing circuit that is used for the electrically-erasable ROM (read-only memory) as claimed in claim 1 is characterized in that, is added in storage unit (Q
C) voltage (VG_SENSE) on the control gate is different under the different working pattern:
When carrying out read operation, make VG_SENSE=VG_RD;
When wiping verification operation, make VG_SENSE=VG_ERS;
When programming verification operation, make VG_SENSE=VG_PGM;
When carrying out clashing verification operation, make VG_SENSE=VG_OEC.
7. the sensing circuit that is used for the electrically-erasable ROM (read-only memory) as claimed in claim 6 is characterized in that, relation below 4 magnitudes of voltage satisfy:
VG_OEC?<?VG_ERS?<?VG_RD?<?VG_PGM；
VG_OEC is by crossing the storage unit targets threshold decision wipe after the correction; VG_ERS is determined by the storage unit targets threshold after wiping; VG_PGM is by the storage unit targets threshold decision after programming; The decision threshold decision of VG_RD during by read operation.
8. reading method that is used for the electrically-erasable ROM (read-only memory) is characterized in that the method includes the steps of:
Step 1, reference unit (Q is set
R) threshold voltage (V
TR);
This threshold voltage (V
TR) be adjusted to neutral threshold voltage (UV_VT);
Step 2, reference unit (Q is set
R) voltage (RVG) on the control gate;
This magnitude of voltage RVG is set to fixed value, and this fixed value is than threshold voltage (V
TR) height;
Step 3, storage unit (Q is set
C) voltage (VG_SENSE) on the control gate;
Step 4, judgement storage unit (Q
C) threshold voltage (V
TC), according to threshold voltage (V
TC) difference and export different results.
9. the sensing circuit that is used for the electrically-erasable ROM (read-only memory) as claimed in claim 8 is characterized in that, described step 3 comprises following steps:
Step 3.1, four magnitude of voltage VG_OEC, VG_ERS, VG_RD, VG_PGM are set, relation below above-mentioned 4 magnitudes of voltage satisfy:
VG_OEC?<?VG_ERS?<?VG_RD?<?VG_PGM；
VG_OEC is by crossing the storage unit targets threshold decision wipe after the correction; VG_ERS is determined by the storage unit targets threshold after wiping; VG_PGM is by the storage unit targets threshold decision after programming; The decision threshold decision of VG_RD during by read operation;
Step 3.2, when carrying out read operation, make VG_SENSE=VG_RD;
Step 3.3, when wiping verification operation, make VG_SENSE=VG_ERS;
Step 3.4, when programming verification operation, make VG_SENSE=VG_PGM;
Step 3.5, when carrying out clashing verification operation, make VG_SENSE=VG_OEC.
10. the sensing circuit that is used for the electrically-erasable ROM (read-only memory) as claimed in claim 8 is characterized in that, described step 4 comprises following steps:
Which kind of operation step 4.1, judgement electrically-erasable ROM (read-only memory) are in, if wipe verification operation, then jump to step 4.2; If programme verification operation; Then jump to step 4.3,, then jump to step 4.4 if carried out wiping verification operation; If carry out read operation, then jump to step 4.5;
If step 4.2 storage unit (Q
C) threshold voltage V
TC<vG_ERS – RVG+V
TR, then through wiping verification;
If step 4.3 storage unit (Q
C) threshold voltage V
TC>VG_PGM – RVG+V
TR, then through the programming verification;
If step 4.4 storage unit (Q
C) threshold voltage V
TC>VG_OEC – RVG+V
TR, then wipe verification through crossing;
If step 4.5 storage unit (Q
C) threshold voltage V
TC>VG_RD – RVG+V
TR, then sense data is 0, on the contrary sense data is 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010541843.4A CN102467967B (en) | 2010-11-12 | 2010-11-12 | Readout circuit and readout method for electrically erasable read-only memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010541843.4A CN102467967B (en) | 2010-11-12 | 2010-11-12 | Readout circuit and readout method for electrically erasable read-only memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102467967A true CN102467967A (en) | 2012-05-23 |
| CN102467967B CN102467967B (en) | 2015-05-20 |
Family
ID=46071491
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201010541843.4A Active CN102467967B (en) | 2010-11-12 | 2010-11-12 | Readout circuit and readout method for electrically erasable read-only memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102467967B (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103578548A (en) * | 2012-08-09 | 2014-02-12 | 北京兆易创新科技股份有限公司 | Flash memory and method for determining reference units thereof |
| CN103943144A (en) * | 2014-04-30 | 2014-07-23 | 中国科学院上海微系统与信息技术研究所 | Reference resistance-optimized phase change memory reading circuit and reference resistance optical selection method |
| CN104934069A (en) * | 2015-07-15 | 2015-09-23 | 上海芯泽电子科技有限公司 | Read-write design method used for simplifying and determining non-volatile storage cell |
| CN106024063A (en) * | 2016-07-19 | 2016-10-12 | 北京兆易创新科技股份有限公司 | Data reading device and method of nonvolatile memory |
| CN106098103A (en) * | 2016-06-03 | 2016-11-09 | 北京兆易创新科技股份有限公司 | The replacement method of bad point unit in a kind of nonvolatile memory |
| CN107633865A (en) * | 2016-07-19 | 2018-01-26 | 北京兆易创新科技股份有限公司 | A kind of digital independent device and method of nonvolatile memory |
| CN108182957A (en) * | 2018-01-19 | 2018-06-19 | 上海磁宇信息科技有限公司 | A kind of MRAM reading circuits using reference voltage |
| CN111916124A (en) * | 2019-05-08 | 2020-11-10 | 中芯国际集成电路制造(上海)有限公司 | Data reading circuit and memory cell |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1221193A (en) * | 1997-11-20 | 1999-06-30 | 日本电气株式会社 | Non-volatile semiconductor memory |
| CN1501401A (en) * | 2002-07-16 | 2004-06-02 | ��������˹�����տ����� | Thin film magnetic memory device provided with magnetic tunnel junctions |
| CN101859606A (en) * | 2009-04-07 | 2010-10-13 | 北京芯技佳易微电子科技有限公司 | Method and equipment for adjusting reference unit threshold parameter and testing system |
-
2010
- 2010-11-12 CN CN201010541843.4A patent/CN102467967B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1221193A (en) * | 1997-11-20 | 1999-06-30 | 日本电气株式会社 | Non-volatile semiconductor memory |
| CN1501401A (en) * | 2002-07-16 | 2004-06-02 | ��������˹�����տ����� | Thin film magnetic memory device provided with magnetic tunnel junctions |
| CN101859606A (en) * | 2009-04-07 | 2010-10-13 | 北京芯技佳易微电子科技有限公司 | Method and equipment for adjusting reference unit threshold parameter and testing system |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103578548B (en) * | 2012-08-09 | 2016-08-03 | 北京兆易创新科技股份有限公司 | The determination method of flash memory and reference unit thereof |
| CN103578548A (en) * | 2012-08-09 | 2014-02-12 | 北京兆易创新科技股份有限公司 | Flash memory and method for determining reference units thereof |
| CN103943144B (en) * | 2014-04-30 | 2017-07-11 | 中国科学院上海微系统与信息技术研究所 | The phase transition storage reading circuit and reference resistance method for optimizing of reference resistance optimization |
| CN103943144A (en) * | 2014-04-30 | 2014-07-23 | 中国科学院上海微系统与信息技术研究所 | Reference resistance-optimized phase change memory reading circuit and reference resistance optical selection method |
| CN104934069A (en) * | 2015-07-15 | 2015-09-23 | 上海芯泽电子科技有限公司 | Read-write design method used for simplifying and determining non-volatile storage cell |
| CN106098103A (en) * | 2016-06-03 | 2016-11-09 | 北京兆易创新科技股份有限公司 | The replacement method of bad point unit in a kind of nonvolatile memory |
| CN106024063A (en) * | 2016-07-19 | 2016-10-12 | 北京兆易创新科技股份有限公司 | Data reading device and method of nonvolatile memory |
| CN107633865A (en) * | 2016-07-19 | 2018-01-26 | 北京兆易创新科技股份有限公司 | A kind of digital independent device and method of nonvolatile memory |
| CN107633865B (en) * | 2016-07-19 | 2024-02-20 | 兆易创新科技集团股份有限公司 | Data reading device and method of nonvolatile memory |
| CN108182957A (en) * | 2018-01-19 | 2018-06-19 | 上海磁宇信息科技有限公司 | A kind of MRAM reading circuits using reference voltage |
| CN108182957B (en) * | 2018-01-19 | 2023-10-03 | 上海磁宇信息科技有限公司 | MRAM readout circuit using reference voltage |
| CN111916124A (en) * | 2019-05-08 | 2020-11-10 | 中芯国际集成电路制造(上海)有限公司 | Data reading circuit and memory cell |
| CN111916124B (en) * | 2019-05-08 | 2022-05-13 | 中芯国际集成电路制造(上海)有限公司 | Data reading circuit and memory cell |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102467967B (en) | 2015-05-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102467967B (en) | Readout circuit and readout method for electrically erasable read-only memory | |
| CN101165807B (en) | Flash memory devices and methods of operating the same | |
| CN101849264B (en) | Controlling a memory device responsive to degradation | |
| US6510082B1 (en) | Drain side sensing scheme for virtual ground flash EPROM array with adjacent bit charge and hold | |
| KR950011295B1 (en) | Non-volatile semiconductor memory device read only memory and method of measuring threshold voltage | |
| US8547755B2 (en) | Method and apparatus of performing an erase operation on a memory integrated circuit | |
| JPH10320987A (en) | Multi-level non-volatile semiconductor memory device | |
| US7663932B2 (en) | Nonvolatile semiconductor memory device | |
| US8122307B1 (en) | One time programmable memory test structures and methods | |
| US8072815B2 (en) | Array of non-volatile memory cells including embedded local and global reference cells and system | |
| KR20050098904A (en) | Selection circuitor for accurate memory read operations | |
| CN101430935B (en) | Detection method for over-erasing memory unit in flash memory | |
| US8064263B2 (en) | Current sink system for source-side sensing | |
| US20090129154A1 (en) | Semiconductor memory device | |
| CN105304669A (en) | Non-volatile resistance-variable storage circuit and control method thereof | |
| US6075738A (en) | Semiconductor memory device | |
| JP4469649B2 (en) | Semiconductor flash memory | |
| CN100435242C (en) | Method of recovering overerased bits in a memory device | |
| CN100520968C (en) | Non-volatile semiconductor memory device | |
| JP3404712B2 (en) | Nonvolatile semiconductor memory device and writing method thereof | |
| CN106601291A (en) | Reference current generation circuit and method of flash memory | |
| US20060098492A1 (en) | Erase-verifying method of NAND type flash memory device and NAND type flash memory device thereof | |
| US8493768B2 (en) | Memory cell and memory device using the same | |
| CN102142279A (en) | Semiconductor storage device | |
| US7830708B1 (en) | Compensating for variations in memory cell programmed state distributions |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C53 | Correction of patent of invention or patent application | ||
| CB02 | Change of applicant information |
Address after: 200433, building 4, Fudan Science Park, No. 127 Guotai Road, Shanghai, Yangpu District Applicant after: Shanghai Fudan Microelectronic Group Co., Ltd. Address before: 200433, building 4, Fudan Science Park, No. 127 Guotai Road, Shanghai, Yangpu District Applicant before: Fudan Microelectronics Co., Ltd., Shanghai |
|
| COR | Change of bibliographic data |
Free format text: CORRECT: APPLICANT; FROM: FUDAN MICROELECTRONICS CO., LTD., SHANGHAI TO: SHANGHAI FUDAN MICROELECTRONICS GROUP COMPANY LIMITED |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |