CN102467967B - Readout circuit and readout method for electrically erasable read-only memory - Google Patents
Readout circuit and readout method for electrically erasable read-only memory Download PDFInfo
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- CN102467967B CN102467967B CN201010541843.4A CN201010541843A CN102467967B CN 102467967 B CN102467967 B CN 102467967B CN 201010541843 A CN201010541843 A CN 201010541843A CN 102467967 B CN102467967 B CN 102467967B
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Abstract
The invention relates to a readout circuit and a readout method for an electrically erasable read-only memory. The readout circuit comprises a comparator, a reference resistor, a sensing resistor, a reference unit and a storage unit, wherein the readout circuit is only configured with one reference unit, and the same reference unit is used in the process of reading operation; the threshold voltage of the reference unit is set into neutral threshold voltage; and the voltage on a reference unit control grid is set into a fixed value, so that the configuration time in the manufacturing process is obviously reduced, and the threshold added on a storage unit control grid is changed along with operating modes. Meanwhile, the voltage added on the storage unit control grid during the reading operation and programming verification operation is lower than that in the prior art, so that a stress effect of grid voltage is reduced, and the threshold voltage of the reference unit is set to a value approaching the neutral threshold voltage so as to be more stable.
Description
Technical field
The present invention relates to a kind of sensing circuit for electrically-erasable ROM (read-only memory) and reading method.
Background technology
Conventional Flash EEPROM (electrically-erasable ROM (read-only memory)) comprises some storage unit.This storage unit manufactures on P-type semiconductor substrate, and each unit comprises the drain terminal of a n+ type and the source of a n+ type.Substrate has the gate dielectric layer of one deck relative thin, on be polysilicon formed floating boom.Floating boom being second layer dielectric layer, second layer dielectric layer is the control gate that polysilicon is formed.Source and drain end is kept apart by the channel region on substrate.
The quantity of electric charge on floating boom is determined by the number of electrons comprised in floating boom.When programming, electronics is injected in floating boom, thus improves the threshold voltage of storage unit.Threshold voltage instigates the minimum voltage between control gate required for memory cell conducts and source.When wiping, the electronics in floating boom is removed, thus reduces the threshold voltage of storage unit.Under programming state, the threshold voltage of storage unit is greater than+6.5V usually, and under erase status, the threshold voltage of storage unit is less than+3.0V usually.
For determining whether storage unit is programmed, add the voltage between+3.0V to+6.5V on the control gate, normally+5.0V, source adds 0V, and drain terminal adds the voltage between 1V-2V.If memory cell conducts, electric current can flow through between the source and drain of storage unit, represents that this unit is in erase status, saves data " 1 "; Otherwise, then represent that this unit is in programming state, save data " 0 ".
Fig. 1 is the simplification functional block diagram of a conventional FLASH memory.100 is conventional semiconductor memery circuits, and comprise storage array 102,102 are made up of some storage unit MC11-MCnm.MC11-MCnm is arranged in the matrix of n × m in circuit.Each storage unit comprises a transistor (Qp11-Qpnm), and transistor is used for preserving data " 0 " or " 1 ".The drain terminal of each transistor is connected with in bit line BL0-BLm-1, and the source of all crystals pipe meets identical common ground potential VSS.The control gate of each transistor is connected with in wordline WL0-WLn-1 one.Memory circuitry 100 also comprises line decoder 104, column decoder 106, and Y transmission circuit 108.Line decoder 104 chooses a corresponding wordline according to row address signal Ai from WL0-WLn-1, and column decoder chooses a corresponding bit lines according to column address signal Aj from BL0-BLm-1.Bit line selected in array is connected with reading or sensing circuit 110 by Y transmission circuit 108.
Comprise a sensor amplifier in sensing circuit 110, this sensor compares electric current in wordline and reference current, and what the comparative result of sensor indicated the memory cell chosen to preserve is " 0 " or " 1 ".
Fig. 2 is the schematic diagram of sensing circuit 110.Comprise a comparer 120 in circuit, sensing resistor 124 that reference resistance 122 that resistance is R2, resistance are R1, the transistor Q of storage unit
p, and the transistor Q of reference unit
r1-Q
r4.
One end of reference resistance 122 is connected with a voltage source V CC, and typical voltage values is 1.0V, and the other end is connected at node A with the in-phase input end of comparer 120.Node A is by reference to unit wires REF and switch S 1-S4 and reference transistor Q
r1-Q
r4drain terminal be connected.One end of sensing resistor 124 is connected with voltage source V CC, and the other end is connected at node B with the inverting input of comparer 120.Node B is by selected bit line BL and memory transistor Q
pdrain terminal be connected.Q
pand Q
r1-Q
r4control gate be all connected to selected wordline WL, accept identical control-grid voltage VG_SENSE.
When carrying out read operation, switch S 1 conducting, the electric current I CELL of storage unit with from Q
r1electric current I REF compare.
When carrying out programming verification operation, switch S 2 conducting, the electric current I CELL of storage unit with from Q
r2electric current I REF compare.
When carrying out erasing verification operation, switch S 3 conducting, the electric current I CELL of storage unit with from Q
r3electric current I REF compare.
When carrying out erasing verification operation, switch S 4 conducting, the electric current I CELL of storage unit with from Q
r4electric current I REF compare.
Q
r1threshold voltage be RD_VT, Q
r2threshold voltage be PGM_VT, Q
r3threshold voltage be ERS_VT, Q
r4threshold voltage be OEC_VT.These threshold voltages meet following relation:
OEC_VT < ERS_VT < RD_VT < PGM_VT
Q in reference unit is given in Fig. 3
r1-Q
r4reference current and control-grid voltage V
gcurve map.Because reference transistor and memory transistor are identical, therefore IDS curve A-D is parallel, is also parallel with the IDS curve of memory transistor.The difference of curve A-D is because different threshold voltages causes.
When carrying out read operation, switch S 1 conducting, Q
pand Q
r1control gate all making alive VG_SENSE.Comparer 120 compares from the electric current I CELL of memory transistor with from Q
r1reference current RD_IREF.If ICELL is greater than RD_IREF, then comparer 120 exports " 1 ", otherwise exports " 0 ".
When carrying out programming verification, switch S 2 conducting, Q
pand Q
r2control gate all making alive VG_SENSE.Comparer 120 compares from the electric current I CELL of memory transistor with from Q
r2reference current PGM_IREF.If ICELL is less than ERS_IREF, then comparer 120 exports " 0 ", instruction Q
pby programming verification.
When carrying out erasing verification, switch S 3 conducting, Q
pand Q
r3control gate all making alive VG_SENSE.Comparer 120 compares from the electric current I CELL of memory transistor with from Q
r3reference current ERS_IREF.If ICELL is greater than ERS_IREF, then comparer 120 exports " 1 ", instruction Q
pby erasing verification.
When carrying out erasing verification, switch S 4 conducting, Q
pand Q
r4control gate all making alive VG_SENSE.Comparer 120 compares from the electric current I CELL of memory transistor with from Q
r2reference current OEC_IREF.If ICELL is less than OEC_IREF, then comparer 120 exports " 0 ", instruction Q
pverification is wiped by crossing.
Prior art has some defects:
1. wipe verification to read, programming verification, erasing verification to FLASH storage array and cross, need 4 reference unit Q
r1-Q
r4threshold voltage be configured.This layoutprocedure needs the programming-checking procedure of carrying out repeatedly to reference unit, until reference unit reaches the threshold value of needs.Therefore layoutprocedure consumes the more time, adds cost.
2. because programming School Affairs crosses the reference unit Q used by erasing verification
r2and Q
r4threshold value and neutral threshold value UV_VT (neutral threshold value refer to storage unit floating delete in threshold value when not having an electric charge, neutral threshold value changes with manufacturing process, the representative value of NOR type flash storage may be distributed between 2.3-3.5V) deviation larger, therefore easily there is electric charge to lose when there is disturbance, thus cause threshold value to offset, and then the threshold value after impact programming distributes and data retention over time.
Summary of the invention
A kind of sensing circuit for electrically-erasable ROM (read-only memory) provided by the invention and reading method, decrease the setup time in manufacture process, improve the threshold voltage stability of reference unit.
In order to achieve the above object, the invention provides a kind of sensing circuit for electrically-erasable ROM (read-only memory), this sensing circuit comprises comparer, reference resistance, sensing resistor, and described reference resistance is identical with the resistance of sensing resistor.
This sensing circuit also comprises reference unit and storage unit.
One termination voltage source of reference resistance, the other end is connected with the in-phase input end of comparer at datum node place.Datum node is connected with the drain electrode end of reference unit by reference to bit line.One termination voltage source of sensing resistor, the other end is connected with the inverting input of comparer at storage node place.Storage node is connected with the drain electrode end of storage unit by selected bit line.
The threshold voltage V of reference unit
tRbe adjusted to close to neutral threshold voltage UV_VT.
The voltage be added on reference unit control gate is a fixed voltage RVG.
The voltage VG_SENSE be added on storage unit control gate is then different under different mode of operations.
1, when carrying out read operation, VG_SENSE=VG_RD is made;
2, when carrying out erasing verification operation, VG_SENSE=VG_ERS is made;
3, when carrying out programming verification operation, VG_SENSE=VG_PGM is made;
4, when carrying out clashing verification operation, VG_SENSE=VG_OEC is made.
Above-mentioned 4 magnitudes of voltage meet following relation:
VG_OEC < VG_ERS < VG_RD < VG_PGM
VG_OEC is by crossing the storage unit targets threshold decision after erasing correction; VG_ERS is determined by the storage unit targets threshold after wiping; VG_PGM is determined by the storage unit targets threshold after programming; VG_RD is determined by decision threshold during read operation.
The present invention also provides a kind of reading method for electrically-erasable ROM (read-only memory), and the method includes the steps of:
Step 1, the threshold voltage V of reference unit is set
tR;
This threshold voltage V
tRbe adjusted to close to neutral threshold voltage UV_VT.
Step 2, the voltage RVG arranged on reference unit control gate;
This magnitude of voltage RVG is set to fixed value.
Step 3, the voltage VG_SENSE arranged on storage unit control gate.
Step 3.1, arrange four magnitudes of voltage VG_OEC, VG_ERS, VG_RD, VG_PGM, above-mentioned 4 magnitudes of voltage meet following relation:
VG_OEC < VG_ERS < VG_RD < VG_PGM。
VG_OEC is by crossing the storage unit targets threshold decision after erasing correction; VG_ERS is determined by the storage unit targets threshold after wiping; VG_PGM is determined by the storage unit targets threshold after programming; VG_RD is determined by decision threshold during read operation.
Step 3.2, when carrying out read operation, make VG_SENSE=VG_RD.
Step 3.3, when carrying out erasing verification operation, make VG_SENSE=VG_ERS.
Step 3.4, when carrying out programming verification operation, make VG_SENSE=VG_PGM.
Step 3.5, when carrying out clashing verification operation, made VG_SENSE=VG_OEC.
Step 4, judge storage unit (Q
c) threshold voltage (V
tC), according to threshold voltage (V
tC) difference and export different results.
Step 4.1, judge electrically-erasable ROM (read-only memory) be in which kind of operation, if carry out erasing verification operation, then jump to step 4.2, if carry out programming verification operation, then jump to step 4.3, if carried out erasing verification operation, then jump to step 4.4, if carry out read operation, then jump to step 4.5.
If step 4.2 storage unit (Q
c) threshold voltage V
tC< VG_ERS – RVG+V
tR, then by erasing verification.
If step 4.3 storage unit (Q
c) threshold voltage V
tC> VG_PGM – RVG+V
tR, then by programming verification.
If step 4.4 storage unit (Q
c) threshold voltage V
tC> VG_OEC – RVG+V
tR, then erasing verification was passed through.
If step 4.5 storage unit (Q
c) threshold voltage V
tC> VG_RD – RVG+V
tR, then sense data is 0, otherwise sense data is 1.
The present invention is carrying out read operation, programming verification operation, same reference unit is make use of in the process of erasing verification operation and excessively erasing verification operation, and the voltage on reference unit control gate is also a fixed value, therefore configuration reference unit is only needed, thus the setup time significantly reduced in manufacture process, and the threshold value be added on storage unit control gate is with operational mode change, simultaneously, because the voltage be added on storage unit control gate when read operation and programming verification operation is lower relative to conventional art, therefore gate voltage stress effect reduces, the threshold voltage of reference unit is arranged on neutral near threshold voltage, make the threshold voltage of reference unit more stable.
Accompanying drawing explanation
Fig. 1 is the simplification functional block diagram of conventional FLASH memory in background technology.
Fig. 2 is the schematic diagram of sensing circuit in background technology.
Fig. 3 is the reference current of QR1-QR4 in reference unit in background technology and the curve map (SQRT is square root, and IDS is the source-drain current of unit under test, and SQRT (IDS) is exactly the square root of unit under test source-drain current) of control-grid voltage VG.
Fig. 4 is the circuit diagram of the sensing circuit for electrically-erasable ROM (read-only memory) provided by the invention.
Fig. 5 is the graph of a relation of reference current IREF in sensing circuit provided by the invention, memory cell current ICELL and control-grid voltage VG.
Embodiment
Following according to Fig. 4 and Fig. 5, illustrate preferred embodiment of the present invention:
As shown in Figure 4, be the circuit diagram of the sensing circuit for electrically-erasable ROM (read-only memory) provided by the invention, this sensing circuit comprises comparer 420, and resistance is the reference resistance 412 of R402, and resistance is the sensing resistor 414, R402=R401 of R401.
This sensing circuit also comprises reference unit Q
rwith storage unit Q
c.
One termination voltage source V CC of reference resistance 412, the representative value of VCC is+1.0V, and the other end is connected with the in-phase input end of comparer 420 at datum node Y place.Datum node Y is by reference to bit line REF and reference unit Q
rdrain electrode end be connected.One end of sensing resistor 414 is connected with VCC, and the other end is connected with the inverting input of comparer 420 at storage node X place.Storage node X is by selected bit line BL and storage unit Q
cdrain electrode end be connected.
Different from the background technology shown in Fig. 2, the transistor Q in reference unit
r1-Q
r4by a reference unit Q
rreplaced.
Reference unit Q
rthreshold voltage V
tRbe adjusted to close to neutral threshold voltage UV_VT, value is 3.0V, therefore highly stable.
Be added in reference unit Q
rvoltage on control gate is a fixed voltage RVG, and value is 3.5V.
Be added in storage unit Q
cvoltage VG_SENSE on control gate is then different under different mode of operations.
1, when carrying out read operation, VG_SENSE=VG_RD is made;
2, when carrying out erasing verification operation, VG_SENSE=VG_ERS is made;
3, when carrying out programming verification operation, VG_SENSE=VG_PGM is made;
4, when carrying out clashing verification operation, VG_SENSE=VG_OEC is made.
Above-mentioned 4 magnitudes of voltage meet following relation:
VG_OEC < VG_ERS < VG_RD < VG_PGM。
VG_OEC is by crossing the storage unit targets threshold decision after erasing correction, and such as wished that wiping the storage unit targets threshold after correcting was greater than 0V, then VG_OEC can get 0+RVG-V
tRbetween; VG_ERS is determined by the storage unit targets threshold after wiping, and the storage unit targets threshold after such as wishing erasing is less than 3.2V, then VG_ERS can get 3.2+RVG-V
tR; VG_PGM is determined by the storage unit targets threshold after programming, and the storage unit targets threshold after such as wishing programming is greater than 6.2V, then VG_PGM can get 6.2+RVG-V
tR; VG_RD is determined by decision threshold during read operation, and such as getting decision threshold is 4.7V, and when the threshold value of storage unit is less than 4.7V, sense data is 1, and when the threshold value of storage unit is greater than 4.7V, sense data is 0, and now VG_RD can be set to 4.7+RVG-V
tR.
Desirable VG_RD=4.4V, VG_ERS=3.8V, VG_PGM=6.5V, VG_OEC=0.7V.
The present invention also provides a kind of reading method for electrically-erasable ROM (read-only memory), and the method includes the steps of:
Step 1, reference unit Q is set
rthreshold voltage V
tR;
This threshold voltage V
tRbe adjusted to close to neutral threshold voltage UV_VT.
Neutral threshold voltage UV_VT can change with manufacturing process, may fluctuate between 2.5-3.5V.Therefore V
tRcan be arranged on the central value of fluctuation range, value is 3.0V.
Step 2, reference unit Q is set
rvoltage RVG on control gate;
This magnitude of voltage RVG is set to fixed value.
The value of RVG is than threshold voltage V
tRslightly high, such as high about 0.5V, value is 3.5V.
Step 3, storage unit Q is set
cvoltage VG_SENSE on control gate.
Step 3.1, arrange four magnitudes of voltage VG_OEC, VG_ERS, VG_RD, VG_PGM, above-mentioned 4 magnitudes of voltage meet following relation:
VG_OEC < VG_ERS < VG_RD < VG_PGM。
VG_OEC is by crossing the storage unit targets threshold decision after erasing correction, and such as wished that wiping the storage unit targets threshold after correcting was greater than 0V, then VG_OEC can get 0+RVG-V
tRbetween; VG_ERS is determined by the storage unit targets threshold after wiping, and the storage unit targets threshold after such as wishing erasing is less than 3.2V, then VG_ERS can get 3.2+RVG-V
tR; VG_PGM is determined by the storage unit targets threshold after programming, and the storage unit targets threshold after such as wishing programming is greater than 6.2V, then VG_PGM can get 6.2+RVG-V
tR; VG_RD is determined by decision threshold during read operation, and such as getting decision threshold is 4.7V, and when the threshold value of storage unit is less than 4.7V, sense data is 1, and when the threshold value of storage unit is greater than 4.7V, sense data is 0, and now VG_RD can be set to 4.7+RVG-V
tR.
Step 3.2, when carrying out read operation, make VG_SENSE=VG_RD.
Step 3.3, when carrying out erasing verification operation, make VG_SENSE=VG_ERS.
Step 3.4, when carrying out programming verification operation, make VG_SENSE=VG_PGM.
Step 3.5, when carrying out clashing verification operation, made VG_SENSE=VG_OEC.
Step 4, judge storage unit Q
cthreshold voltage V
tC.
Step 4.1, judge electrically-erasable ROM (read-only memory) be in which kind of operation, if carry out erasing verification operation, then jump to step 4.2, if carry out programming verification operation, then jump to step 4.3, if carried out erasing verification operation, then jump to step 4.4, if carry out read operation, then jump to step 4.5.
If step 4.2 storage unit (Q
c) threshold voltage V
tC< VG_ERS – RVG+V
tR, then by erasing verification.
When carrying out erasing verification operation, be added in storage unit Q
cvoltage VG_SENSE=VG_ERS on control gate.Flow through reference unit Q
relectric current I REF be 501 in Fig. 5.When meeting VG_ERS-V
tC> RVG-V
tRtime, flow through storage unit Q
celectric current I CELL be 502 in Fig. 5, be greater than IREF, the output terminal 418 of comparer 420 exports " 1 ", and instruction storage unit is erase status, otherwise, when not meeting VG_ERS-V
tC> RVG-V
tRtime, flow through storage unit Q
celectric current I CELL be 503 in Fig. 5, be less than IREF, the output terminal 418 of comparer 420 exports " 0 ".Therefore, only have and work as V
tC< VG_ERS – RVG+V
tRtime, storage unit is just by erasing verification.
If step 4.3 storage unit (Q
c) threshold voltage V
tC> VG_PGM – RVG+V
tR, then by programming verification.
When carrying out programming verification operation, be added in the voltage VG_SENSE=VG_PGM on storage unit control gate.Flow through reference unit Q
relectric current I REF be 501 in Fig. 5.When meeting VG_PGM-V
tC< RVG-V
tRtime, flow through storage unit Q
celectric current I CELL be 503 in Fig. 5, be less than IREF, the output terminal 418 of comparer 420 exports " 0 ", and instruction storage unit is programming state; Otherwise, when not meeting VG_PGM-V
tC< RVG-V
tRtime, flow through storage unit Q
celectric current I CELL be 502 in Fig. 5, be greater than IREF, the output terminal 418 of comparer 420 exports " 1 ".Therefore, only have and work as V
tC> VG_PGM – RVG+V
tRtime, storage unit is just by programming verification.
If step 4.4 storage unit (Q
c) threshold voltage V
tC> VG_OEC – RVG+V
tR, then erasing verification was passed through.
When carrying out erasing verification operation, be added in the voltage VG_SENSE=VG_OEC on storage unit control gate.Flow through reference unit Q
relectric current I REF be 501 in Fig. 5.When meeting VG_OEC-V
tC< RVG-V
tRtime, flow through storage unit Q
celectric current I CELL be 503 in Fig. 5, be less than IREF, the output terminal 418 of comparer 420 exports " 0 ", instruction storage unit be not mistake erase status; Otherwise, when not meeting VG_OEC-V
tC< RVG-V
tRtime, the electric current I CELL flowing through storage unit QC is 502 in Fig. 5, is greater than IREF, and the output terminal 418 of comparer 420 exports " 1 ".Therefore, only have and work as V
tC> VG_OEC – RVG+V
tRtime, storage unit is just by crossing erasing programming verification.
If step 4.5 storage unit (Q
c) threshold voltage V
tC> VG_RD – RVG+V
tR, then sense data is 0, otherwise sense data is 1.
When carrying out read operation, be added in the voltage VG_SENSE=VG_RD on storage unit control gate.Flow through reference unit Q
relectric current I REF be 501 in Fig. 5.
If storage unit is by erasing verification, then V
tC< VG_ERS – RVG+V
tR, therefore VG_RD-V
tC> RVG-V
tR, the electric current I REF now flowing through storage unit is 502 in Fig. 5, is greater than IREF, and the output terminal 418 of comparer 420 exports " 1 ", and the data that instruction is preserved are " 1 ".
If storage unit is by programming verification, then V
tC> VG_PGM – RVG+V
tR, therefore VG_RD-V
tC< RVG-V
tR, the electric current I REF now flowing through storage unit is 503 in Fig. 5, is less than IREF, and the output terminal 418 of comparer 420 exports " 0 ", and the data that instruction is preserved are " 0 ".
Although content of the present invention has done detailed introduction by above preferred embodiment, will be appreciated that above-mentioned description should not be considered to limitation of the present invention.After those skilled in the art have read foregoing, for multiple amendment of the present invention and substitute will be all apparent.Therefore, protection scope of the present invention should be limited to the appended claims.
Claims (2)
1. for a sensing circuit for electrically-erasable ROM (read-only memory), it is characterized in that, this sensing circuit comprises comparer (420), reference resistance (412), and sensing resistor (414), this sensing circuit also comprises reference unit (Q
r) and storage unit (Q
c);
One termination voltage source (VCC) of reference resistance (412), the other end is connected with the in-phase input end of comparer (420) at datum node (Y) place, and datum node (Y) is by reference to bit line (REF) and reference unit (Q
r) drain electrode end be connected, a termination voltage source (VCC) of sensing resistor (414), the other end is connected with the inverting input of comparer (420) at storage node (X) place, and storage node (X) is by selected bit line (BL) and storage unit (Q
c) drain electrode end be connected;
Described reference resistance (412) is identical with the resistance of sensing resistor (414);
Described reference unit (Q
r) threshold voltage (V
tR) be adjusted to close to neutral threshold voltage UV_VT;
Be added in reference unit (Q
r) voltage on control gate is a fixed voltage (RVG);
Described is added in reference unit (Q
r) fixed voltage value (RVG) on control gate is than threshold voltage (V
tR) high;
Be added in storage unit (Q
c) voltage VG_SENSE on control gate is different under different mode of operations:
When carrying out read operation, make VG_SENSE=VG_RD;
When carrying out erasing verification operation, make VG_SENSE=VG_ERS;
When carrying out programming verification operation, make VG_SENSE=VG_PGM;
When carrying out clashing verification operation, made VG_SENSE=VG_OEC;
4 magnitudes of voltage meet following relation:
VG_OEC < VG_ERS < VG_RD < VG_PGM；
VG_OEC is by crossing the storage unit targets threshold decision after erasing correction; VG_ERS is determined by the storage unit targets threshold after wiping; VG_PGM is determined by the storage unit targets threshold after programming; VG_RD is determined by decision threshold during read operation.
2. for a reading method for electrically-erasable ROM (read-only memory), it is characterized in that, the method includes the steps of:
Step 1, reference unit (Q is set
r) threshold voltage V
tR;
This threshold voltage V
tRbe adjusted to neutral threshold voltage UV_VT;
Step 2, reference unit (Q is set
r) voltage RVG on control gate;
This magnitude of voltage RVG is set to fixed value, and this fixed value is than threshold voltage V
tRhigh;
Step 3, storage unit (Q is set
c) voltage VG_SENSE on control gate;
Step 4, judge storage unit (Q
c) threshold voltage V
tC, according to threshold voltage V
tCdifference and export different results;
Described step 3 comprises following steps:
Step 3.1, arrange four magnitudes of voltage VG_OEC, VG_ERS, VG_RD, VG_PGM, above-mentioned 4 magnitudes of voltage meet following relation:
VG_OEC < VG_ERS < VG_RD < VG_PGM；
VG_OEC is by crossing the storage unit targets threshold decision after erasing correction; VG_ERS is determined by the storage unit targets threshold after wiping; VG_PGM is determined by the storage unit targets threshold after programming; VG_RD is determined by decision threshold during read operation;
Step 3.2, when carrying out read operation, make VG_SENSE=VG_RD;
Step 3.3, when carrying out erasing verification operation, make VG_SENSE=VG_ERS;
Step 3.4, when carrying out programming verification operation, make VG_SENSE=VG_PGM;
Step 3.5, when carrying out clashing verification operation, made VG_SENSE=VG_OEC;
Described step 4 comprises following steps:
Step 4.1, judge electrically-erasable ROM (read-only memory) be in which kind of operation, if carry out erasing verification operation, then jump to step 4.2, if carry out programming verification operation, then jump to step 4.3, if carried out erasing verification operation, then jump to step 4.4, if carry out read operation, then jump to step 4.5;
If step 4.2 storage unit (Q
c) threshold voltage V
tC< VG_ERS – RVG+V
tR, then by erasing verification;
If step 4.3 storage unit (Q
c) threshold voltage V
tC> VG_PGM – RVG+V
tR, then by programming verification;
If step 4.4 storage unit (Q
c) threshold voltage V
tC> VG_OEC – RVG+V
tR, then erasing verification was passed through;
If step 4.5 storage unit (Q
c) threshold voltage V
tC> VG_RD – RVG+V
tR, then sense data is 0, otherwise sense data is 1.
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| CN108182957B (en) * | 2018-01-19 | 2023-10-03 | 上海磁宇信息科技有限公司 | MRAM readout circuit using reference voltage |
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