CN102457270A - Phase-locked loop with low-gain voltage-controlled oscillator - Google Patents
Phase-locked loop with low-gain voltage-controlled oscillator Download PDFInfo
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- CN102457270A CN102457270A CN2010105272216A CN201010527221A CN102457270A CN 102457270 A CN102457270 A CN 102457270A CN 2010105272216 A CN2010105272216 A CN 2010105272216A CN 201010527221 A CN201010527221 A CN 201010527221A CN 102457270 A CN102457270 A CN 102457270A
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Abstract
The invention discloses a phase-locked loop with a low-gain voltage-controlled oscillator. The phase-locked loop comprises a phase/frequency detector, a charge pump, a low-pass filter, an oscillator, a low-gain voltage-controlled circuit and a first frequency eliminator, wherein, the phase/frequency detector is used for generating a detection pulse according to a phase/frequency difference between a reference clock and a frequency-eliminated oscillation clock; the charge pump is used for generating detection voltages according to the detection pulse and further accumulating the detection voltages; the low-pass filter is used for generating an oscillator control voltage according to the detection voltages; the oscillator is used for generating an oscillation clock according to the oscillator control voltage; the low-gain voltage-controlled circuit is used for adjusting the oscillation clock of the oscillator according to a voltage boundary, temporarily determining the oscillation clock by using a first group of voltage boundaries and adjusting the oscillation clock to a relatively stable scope by using a second group of voltage boundaries within a relatively small scope; and the first frequency eliminator is used for eliminating the frequency of the oscillation clock of the oscillator, so as to generate the frequency-eliminated oscillation clock and transmit to the phase/frequency detector.
Description
Technical field
Present invention is directed to a kind of phase-locked loop and control method thereof, refer to a kind of phase-locked loop especially with low gain voltage controlled oscillator.
Background technology
Please with reference to Figure 1A, Figure 1A system is the sketch map of DESCRIPTION OF THE PRIOR ART low gain voltage controlled oscillator from start to the process of pinning clock.Shown in Figure 1A, when the control bit Bit_vco of oscillator was zero, oscillator control voltage VCTR slowly rose to the position greater than the circle 1 of the upper limit VH on voltage border from the position of circle 0.Therefore, the control bit Bit_vco of oscillator skips to one, and oscillator control voltage VCTR slowly rises to the position greater than the circle 3 of the upper limit VH on voltage border again from the position of circle 2 then.Control bit Bit_vco up to oscillator equals at 2 o'clock, and oscillator control voltage VCTR rises to the position of circle 5.At this moment, the running clock of oscillator just equals the running clock FLOCK that desire is pinned, and oscillator control voltage VCTR also drops down onto within the voltage border.Afterwards, the value of the control bit Bit_vco of oscillator no longer changes.
Please with reference to Figure 1B, Figure 1B system is for after explaining that the low gain voltage controlled oscillator pins clock stable, and oscillator control voltage VCTR comes back to the sketch map of labile state.Shown in Figure 1B, when the running clock of oscillator pinned in system, oscillator control voltage VCTR dropped on the position of circle 5, and wherein circle 5 is very near the upper limit VH on voltage border.And oscillator control voltage VCTR might be because the inner noise in temperature or phase-locked loop moves to circle 5 '.Because circle 5 ' pairing oscillator control voltage VCTR is the upper limit VH greater than the voltage border, therefore, the control bit Bit_vco of oscillator adds one (that is Bit_vco=3), and oscillator control voltage VCTR finally rests on the position of circle 6,7.But when stablized the phase-locked loop, when the control bit Bit_vco of the pairing oscillator of running clock of oscillator changed suddenly, the phase-locked loop needed locking again, and system can't normal operation.
Summary of the invention
One embodiment of the invention provide a kind of phase-locked loop with low gain voltage controlled oscillator.This phase-locked loop comprises a phase/frequency detector, a charge pump, a low pass filter, an oscillator, a low gain voltage-controlled circuit and one first frequency eliminator.This phase/frequency detector system produces one and detects pulse in order to poor according to the phase of a reference clock and a frequency elimination running clock; This charge pump system is coupled to this phase/frequency detector, and in order to detect pulse, produce one and detect voltage according to this, and this detection voltage that adds up; This low pass filter system is coupled to this charge pump, in order to detect voltage according to this, produces oscillator control voltage; This oscillator system is coupled to this low pass filter, in order to produce a running clock according to this oscillator control voltage; This low gain voltage-controlled circuit system is coupled to this low pass filter and this oscillator; In order to basis at least two group voltage borders; To adjust the running clock of this oscillator; Wherein utilize one first group of voltage border to fix tentatively this running clock, with one of the less second group of voltage border of scope this running clock is adjusted to stable scope again; Reach this first frequency eliminator system and be coupled to this oscillator and this phase/frequency detector, in order to running clock frequency elimination, to produce this frequency elimination running clock and to be sent to this phase/frequency detector this oscillator.
Another embodiment of the present invention provides a kind of control method of low gain voltage controlled oscillator.It is that a preset position and oscillator control voltage are a predetermined value that this method comprises the control bit of setting an oscillator; Relatively whether this oscillator control voltage exceeds the scope on one first group of voltage border; If this oscillator control voltage exceeds the scope on this first group of voltage border, the control bit that this oscillator is preset is adjusted a stratum, repeat again a step relatively this oscillator control the scope whether voltage exceeds this first group of voltage border; If this oscillator control voltage does not exceed the scope on this first group of voltage border, one second group of voltage border is changed on this first group of voltage border; Relatively whether this oscillator control voltage exceeds the scope on this second group of voltage border; If this oscillator control voltage exceeds the scope on this second group of voltage border, the control bit at this oscillator place is adjusted a stratum, repeat again a step relatively this oscillator control the scope whether voltage exceeds this second group of voltage border; If reach the scope that this oscillator control voltage does not exceed this second group of voltage border, this first group of voltage border recalled on this second group of voltage border, and with this oscillator control voltage output; Wherein this first group of voltage bounds is greater than this second group of voltage border.
Provided by the present invention have the phase-locked loop of low gain voltage controlled oscillator and a control method of low gain voltage controlled oscillator; System utilizes at least two group voltage borders; Make and control voltage according to the oscillator that running clock determined of first group of voltage border and the pinning of oscillator desire; Can be adjusted by the running clock of second group of voltage border and the pinning of oscillator desire again, thereby away from first group of voltage border.And after the running clock that oscillator control voltage is pinned by second group of voltage border and oscillator desire adjusted, optionally second group of voltage border being relaxed was first group of voltage border.So, will make that the phase-locked loop is more stable, and not influenced by the inner noise in temperature or phase-locked loop.
Description of drawings
Figure 1A is the sketch map of DESCRIPTION OF THE PRIOR ART low gain voltage controlled oscillator from start to the process of pinning clock;
Figure 1B is for after explaining that the low gain voltage controlled oscillator pins clock stable, and oscillator control voltage comes back to the sketch map of labile state;
Fig. 2 has the sketch map of the phase-locked loop of low gain voltage controlled oscillator for one embodiment of the invention explanation;
Fig. 3 A explanation low gain voltage-controlled circuit pins the sketch map of the running clock of oscillator according to first group of voltage border;
Fig. 3 B explanation low gain voltage-controlled circuit pins the sketch map of the running clock of oscillator according to second group of voltage border;
Fig. 4 A and Fig. 4 B are two kinds of sketch mapes of realizing the circuit framework of low gain voltage-controlled circuit;
Fig. 5 has the sketch map of the phase-locked loop of low gain voltage controlled oscillator for one embodiment of the invention explanation;
Fig. 6 has the sketch map of the phase-locked loop of low gain voltage controlled oscillator for one embodiment of the invention explanation;
Fig. 7 has the sketch map of the phase-locked loop of low gain voltage controlled oscillator for one embodiment of the invention explanation;
The flow chart of the control method of Fig. 8 A and Fig. 8 B another embodiment of the present invention explanation low gain voltage controlled oscillator;
According to first group of voltage border and second group of voltage border, the adjustment control bit is with the sketch map of the running clock that pins oscillator according to the method for Fig. 8 A and Fig. 8 B explanation low gain voltage-controlled circuit for Fig. 9 A;
The sketch map of Fig. 9 B key diagram 9A on time shaft;
The flow chart of the control method of Figure 10 A and Figure 10 B another embodiment of the present invention explanation low gain voltage controlled oscillator;
According to first group of voltage border and second group of voltage border, the adjustment control bit is with the sketch map of the running clock that pins oscillator according to the method for Figure 10 A and Figure 10 B explanation low gain voltage-controlled circuit for Figure 11 A;
The sketch map of Figure 11 B key diagram 11A on time shaft;
The flow chart of the control method of Figure 12 A and Figure 12 B another embodiment of the present invention explanation low gain voltage controlled oscillator;
According to first group of voltage border and second group of voltage border, the adjustment control bit is with the sketch map of the running clock that pins oscillator according to the method for Figure 12 A and Figure 12 B explanation low gain voltage-controlled circuit for Figure 13 A;
The sketch map of Figure 13 B key diagram 13A on time shaft;
The flow chart of the control method of Figure 14 A and Figure 14 B another embodiment of the present invention explanation low gain voltage controlled oscillator;
According to first group of voltage border and second group of voltage border, the adjustment control bit is with the sketch map of the running clock that pins oscillator according to the method for Figure 14 A and Figure 14 B explanation low gain voltage-controlled circuit for Figure 15 A;
The sketch map of Figure 15 B key diagram 15A on time shaft.
The main element symbol description:
200,500,600,700 phase-locked loops
202 phase/frequency detectors
204 charge pumps
206 low pass filters
208 oscillators
614,714 second frequency eliminators
210,510,710 low gain voltage-controlled circuits
212 first frequency eliminators
2102 comparators
2104 controllers
5106,7106 delay circuits
21022 voltage border upper limit comparators
21024 voltage border lower limit comparators
The ICLK input clock
CLK, FLOCK running clock
The CR comparative result
The CREF reference clock
DCLK frequency elimination running clock
DP detects pulse
The detection voltage that ADV adds up
VCTR oscillator control voltage
The Vm predetermined value
The VH upper limit
The upper limit on first group of voltage border of VH1
The upper limit on second group of voltage border of VH2
The upper limit on VH3 tertiary voltage border
The upper limit on VHn n voltage border
The VL lower limit
The lower limit on first group of voltage border of VL1
The lower limit on second group of voltage border of VL2
The lower limit on VL3 tertiary voltage border
The lower limit on VLn n voltage border
The Bit_vco control bit
800-828,1000-1028,1200-1228,1400-1428 step
Embodiment
Please with reference to Fig. 2, Fig. 2 system has the sketch map of the phase-locked loop 200 of low gain voltage controlled oscillator for one embodiment of the invention explanation.Phase-locked loop 200 comprises a phase/frequency detector 202, a charge pump 204, a low pass filter 206, an oscillator 208, a low gain voltage-controlled circuit 210 and one first frequency eliminator 212.Phase/frequency detector 202 is in order to poor according to the phase of a reference clock CREF and a frequency elimination running clock DCLK, and generation one detection pulsed D P wherein detects pulsed D P and the phase difference is linear scale.Charge pump 204 is to be coupled to phase/frequency detector 202, in order to according to detecting pulsed D P, produces one and detects voltage ADV; Low pass filter 206 is to be coupled to charge pump 204, in order to according to detecting voltage ADV, produces oscillator control voltage VCTR; Oscillator 208 is to be coupled to low pass filter 206, in order to according to oscillator control voltage VCTR, produces a running clock CLK; Low gain voltage-controlled circuit 210 is to be coupled to low pass filter 206 and oscillator 208, in order to basis at least two group voltage borders (VL1-VH1, VL2-VH2) running clock of regulation and control oscillator 208; Reaching first frequency eliminator 212 is to be coupled to oscillator 208 and phase/frequency detector 202, in order to the running clock CLK frequency elimination to oscillator 208, to produce frequency elimination running clock DCLK and to be sent to phase/frequency detector 202.
Please with reference to Fig. 2 and Fig. 3 A, Fig. 3 A system explanation low gain voltage-controlled circuit 210 pins the sketch map of the running clock of oscillator 208 according to first group of voltage border VH1-VL1.As shown in Figure 2, low gain voltage-controlled circuit 210 comprises a comparator 2102 and a controller 2104, and comparator 2102 is to be coupled to low pass filter 206.Shown in Fig. 3 A, comparator 2102 is done comparison with the predetermined value Vm of first group of voltage border VH1-VL1 and oscillator control voltage VCTR earlier, and this moment, the control bit Bit_vco of oscillator 208 equaled 0.But the present invention is not limited to oscillator 208 begins starting of oscillation from low frequency, and oscillator 208 also can begin starting of oscillation from high frequency, the frequency of oscillation of pinning oscillator 208 by the control bit Bit_vco of adjustment oscillator again.Oscillator control voltage VCTR equals the frequency of oscillation that 0 low gain curve progressively increases oscillator 208 along Bit_vco; During greater than the upper limit VH1 (circle 1 of Fig. 3 A) on first group of voltage border, comparator 2102 produces a comparative result CR up to oscillator control voltage VCTR.Controller 2104 is to be coupled to comparator 2102, in order to according to comparative result CR, changes the control bit Bit_vco of oscillator 208, and therefore, this moment, the control bit Bit_vco of oscillator equaled 1.208 on oscillator is according to control bit Bit_vco, the running clock of adjustment oscillator.Oscillator control voltage VCTR equals the frequency of oscillation that 1 low gain curve progressively increases oscillator 208 along Bit_vco then; During greater than the upper limit VH1 (circle 2 of Fig. 3 A) on first group of voltage border, comparator 2102 produces comparative result CR again up to oscillator control voltage VCTR.So, repeat said process, be lockable up to the frequency of oscillation of oscillator 208, and oscillator control voltage VCTR drops on (circle 3 of Fig. 3 A) within first group of voltage border VH1-VL1 scope.
Shown in Fig. 3 A, oscillator control voltage VCTR (circle 3) is though drop within first group of voltage border VH1-VL1 scope, and the upper limit VH1 that leaves first group of voltage border is very near.And oscillator control voltage VCTR might be because the inner noise in temperature or phase-locked loop moves to outside first group of voltage border VH1-VL1 scope.When stablized phase-locked loop 200, when the pairing control bit Bit_vco of the running clock of oscillator 208 changed suddenly, phase-locked loop 200 needed locking again, can cause the system can't normal operation.
After so the frequency of oscillation of oscillator 208 is lockable through a time of delay; Comparator 2102 can be controlled voltage VCTR with oscillator with second group of narrower voltage border VH2-VL2 and do comparison; But the present invention also can not need pass through time of delay, and comparator 2102 is done comparison with narrower second group of voltage border VH2-VL2 and oscillator control voltage VCTR again.Please with reference to Fig. 3 B, Fig. 3 B system explanation low gain voltage-controlled circuit 210 pins the sketch map of the running clock of oscillator 208 according to second group of voltage border VH2-VL2.Therefore, shown in Fig. 3 B, oscillator control voltage VCTR can drop on the position of circle 4 at last, and it is far away that first group of voltage border VH1-VL1 of distance compared in the position of the position of circle 4 and circle 3.But the present invention is not limited to have only two groups of voltage border VH1-VL1, VH2-VL2, as long as low gain voltage-controlled circuit 210 has at least two voltage borders, all falls into category of the present invention.In addition; After oscillator control voltage VCTR can drop on the position stability of circle 4 at last; Through a time of delay; Relax second group of voltage border VH2-VL2 and get back to first group of voltage border VH1-VL1, but the present invention also can not need pass through time of delay, relax second group of voltage border VH2-VL2 and get back to first group of voltage border VH1-VL1.
Please with reference to Fig. 4 A and Fig. 4 B, Fig. 4 A and Fig. 4 B system are two kinds of sketch mapes of realizing the circuit framework of low gain voltage-controlled circuit 210.Shown in Fig. 4 A, comparator 2102 is with electric resistance partial pressure decision voltage border, and voltage border upper limit comparator 21022 and voltage border lower limit comparator 21024 produce comparative result CRH and CRL and give controller 2104 again according to the voltage border.Shown in Fig. 4 B, comparator 2102 is with different current ratio decision voltages border, and voltage border upper limit comparator 21022 and voltage border lower limit comparator 21024 produce comparative result CRH and CRL and give controller 2104 again according to the voltage border.In addition, voltage border upper limit comparator 21022 is all the comparator with sluggish space with voltage border lower limit comparator 21024.
Please with reference to Fig. 5, Fig. 5 system has the sketch map of the phase-locked loop 500 of low gain voltage controlled oscillator for one embodiment of the invention explanation.The difference of phase-locked loop 500 and phase-locked loop 200 is that the low gain voltage-controlled circuit 510 of phase-locked loop 500 comprises a delay circuit 5106 in addition, and VCTR gets into comparator 2102 in order to delay generator control voltage.Delay circuit 5106 is the reaction time of slowing down phase-locked loop 500, lets phase-locked loop 500 be unlikely tetchiness.Its of phase-locked loop 500 is all identical with phase-locked loop 200 in operating principle, repeats no more at this.
Please with reference to Fig. 6, Fig. 6 system has the sketch map of the phase-locked loop 600 of low gain voltage controlled oscillator for one embodiment of the invention explanation.The difference of phase-locked loop 600 and phase-locked loop 200 is that phase-locked loop 600 comprises one second frequency eliminator 614 in addition, in order to an input clock ICLK frequency reducing, to produce reference clock CREF to phase frequency/detector 202.Its of phase-locked loop 600 is all identical with phase-locked loop 200 in operating principle, repeats no more at this.
Please with reference to Fig. 7, Fig. 7 system has the sketch map of the phase-locked loop 700 of low gain voltage controlled oscillator for one embodiment of the invention explanation.The difference of phase-locked loop 700 and phase-locked loop 200 is that the low gain voltage-controlled circuit 710 that phase-locked loop 700 comprises one second frequency eliminator 714 and phase-locked loop 700 in addition comprises a delay circuit 7106 in addition.Its of phase-locked loop 700 is all identical with phase-locked loop 200 in operating principle, repeats no more at this.
Please with reference to Fig. 8 A and Fig. 8 B, Fig. 8 A and Fig. 8 B are the flow chart of the control method of another embodiment of the present invention explanation low gain voltage controlled oscillator.The method system of Fig. 8 A and Fig. 8 B utilizes phase-locked loop 200 explanations of Fig. 2, and detailed step is following:
Step 800: beginning;
Step 802: the control bit Bit_vco that sets oscillator 208 is zero and oscillator control voltage VCTR is predetermined value Vm;
Step 804: through DT time of delay, whether the comparator 2102 comparison oscillators control voltage VCTR in the low gain voltage-controlled circuit 210 rises to the upper limit VH1 on first group of voltage border; If carry out step 806; If, do not skip to step 810;
Step 806: controller 2104 adds one with control bit Bit_vco;
Step 808: after control bit Bit_vco added one, through time of delay DT again comparison oscillator control voltage VCTR whether rise to the upper limit VH1 on first group of voltage border; If, rebound step 806; If, carry out step 810;
Step 810: comparator 2102 judges whether oscillator control voltage VCTR is less than or equal to the lower limit VL1 on first group of voltage border; If skip to step 814; If, carry out step 812;
Step 812: through after time of delay, comparator 2102 comparison oscillators control voltage VCTR and second group of voltage border VH2-VL2 skip to step 816;
Step 814: stop comparison oscillator control voltage VCTR and first group of voltage border VH1-VL1, skip to step 828;
Step 816: whether the comparator 2102 comparison oscillators control voltage VCTR in the low gain voltage-controlled circuit 210 rises to the upper limit VH2 on second group of voltage border; If carry out step 818; If, do not skip to step 822;
Step 818: controller 2104 adds one with control bit Bit_vco;
Step 820: after control bit Bit_vco added one, through time of delay DT again comparison oscillator control voltage VCTR whether rise to the upper limit VH2 on second group of voltage border; If, rebound step 818; If, carry out step 822;
Step 822: comparator 2102 judges whether oscillator control voltage VCTR is less than or equal to the lower limit VL2 on second group of voltage border; If skip to step 826; If, carry out step 824;
Step 824: through after time of delay, change second group of voltage border VH2-VL2 to the first group voltage border VH1-VL1, skip to step 828;
Step 826: stop comparison oscillator control voltage VCTR and second group of voltage border VH2-VL2, rebound step 824;
Step 828: finish.
Please with reference to Fig. 9 A and Fig. 9 B; Fig. 9 A system explains that according to the method for Fig. 8 A and Fig. 8 B low gain voltage-controlled circuit 210 is according to first group of voltage border VH1-VL1 and second group of voltage border VH2-VL2; Adjustment control bit Bit_vco; With the sketch map of the running clock that pins oscillator 208, Fig. 9 B ties up to the sketch map of key diagram 9A on the time shaft.Shown in Fig. 9 A, equal zero and a period of time at control bit Bit_vco, oscillator control voltage VCTR can surpass first group of voltage border VH1 (circle 2,4).Equal at 2 o'clock at control bit Bit_vco, oscillator control voltage VCTR is because running clock FLOCK and control bit Bit_vco that oscillator 208 desires are pinned equal two curve intersection and rest on circle 6.But the upper limit VH1 on first group of voltage border of circle 6 pairing oscillator control voltage VCTR distances is very near, therefore, sees through step 812, comparator 2102 comparison oscillators control voltage VCTR and second group of voltage border VH2-VL2.Shown in Fig. 9 A, circle 6 pairing oscillator control voltage VCTR are greater than the upper limit VH2 on second group of voltage border, so control bit Bit_vco adds one (this moment, control bit Bit_vco equaled three).At last, oscillator control voltage VCTR is because running clock FLOCK and control bit Bit_vco that oscillator 208 desires are pinned equal three curve intersection and rest on circle 8.Shown in Fig. 9 A, the upper limit VH1 on first group of voltage border of circle 8 pairing oscillator control voltage VCTR distances is far away.In step 826; Stop behind comparison oscillator control voltage VCTR and the second group of voltage border through time of delay; Change second group of voltage border VH2-VL2 to the first group voltage border VH1-VL1; That is relax the voltage border, but the present invention also can not need pass through time of delay, relaxes second group of voltage border VH2-VL2 and gets back to first group of voltage border VH1-VL1.In addition; The present invention also can not need through time of delay comparator 2102 comparison oscillators control voltage VCTR and second group of voltage border VH2-VL2 in step 812, and also can not need to change through a time of delay second group of voltage border VH2-VL2 to the first group voltage border VH1-VL1 in step 824.
Please with reference to Figure 10 A and Figure 10 B, Figure 10 A and Figure 10 B are the flow chart of the control method of another embodiment of the present invention explanation low gain voltage controlled oscillator.The method system of Figure 10 A and Figure 10 B utilizes phase-locked loop 200 explanations of Fig. 2, and detailed step is following:
Step 1000: beginning;
Step 1002: the control bit Bit_vco that sets oscillator 208 is that N and oscillator control voltage VCTR are predetermined value Vm;
Step 1004: through DT time of delay, the lower limit VL1 whether the comparator 2102 comparison oscillators control voltage VCTR in the low gain voltage-controlled circuit 210 reduces to first group of voltage border; If carry out step 1006; If, do not skip to step 1010;
Step 1006: controller 2104 subtracts one with control bit Bit_vco;
Step 1008: after control bit Bit_vco subtracted one, through the time of delay of the comparison oscillator control voltage VCTR lower limit VL1 that whether reduces to first group of voltage border again; If, rebound step 1006; If, carry out step 1010;
Step 1010: comparator 2102 judges that oscillator control voltage VCTR is whether more than or equal to the upper limit VH1 on first group of voltage border; If skip to step 1014; If, carry out step 1012;
Step 1012: through after time of delay, comparator 2102 comparison oscillators control voltage VCTR and second group of voltage border VH2-VL2 skip to step 1016;
Step 1014: stop comparison oscillator control voltage VCTR and first group of voltage border VH1-VL1, skip to step 1028;
Step 1016: the lower limit VL2 whether the comparator 2102 comparison oscillators control voltage VCTR in the low gain voltage-controlled circuit 210 reduces to second group of voltage border; If carry out step 1018; If, do not skip to step 1022;
Step 1018: controller 2104 subtracts one with control bit Bit_vco;
Step 1020: after control bit Bit_vco subtracted one, through the DT time of delay comparison oscillator control voltage VCTR lower limit VL2 that whether reduces to second group of voltage border again; If, rebound step 1018; If, carry out step 1022;
Step 1022: comparator 2102 judges that oscillator control voltage VCTR is whether more than or equal to the upper limit VH2 on second group of voltage border; If skip to step 1026; If, carry out step 1024;
Step 1024: through after time of delay, change second group of voltage border VH2-VL2 to the first group voltage border VH1-VL1, skip to step 1028;
Step 1026: stop comparison oscillator control voltage VCTR and second group of voltage border VH2-VL2, rebound step 1024;
Step 1028: finish.
Please with reference to Figure 11 A and Figure 11 B; Figure 11 A system explains that according to the method for Figure 10 A and Figure 10 B low gain voltage-controlled circuit 210 is according to first group of voltage border VH1-VL1 and second group of voltage border VH2-VL2; Adjustment control bit Bit_vco; With the sketch map of the running clock that pins oscillator 208, Figure 11 B ties up to the sketch map of key diagram 11A on the time shaft.Shown in Figure 11 A; Equal seven and at 6 o'clock at control bit Bit_vco; Oscillator control voltage VCTR can surpass first group of voltage border VL1 (circle 2,4), begins from minion but the present invention is not limited to control bit Bit_vco, and it only is in order to clearly demonstrate the present invention that control bit Bit_vco begins from minion.Equal at 5 o'clock at control bit Bit_vco, oscillator control voltage VCTR is because running clock FLOCK and control bit Bit_vco that oscillator 208 desires are pinned equal five curve intersection and rest on circle 6.But the lower limit VL1 on first group of voltage border of circle 6 pairing oscillator control voltage VCTR distances is very near, therefore, sees through step 1012, comparator 2102 comparison oscillators control voltage VCTR and second group of voltage border VH2-VL2.Shown in Figure 11 A, circle 6 pairing oscillator control voltage VCTR are less than the lower limit VL1 on second group of voltage border, so control bit Bit_vco subtracts one (this moment, control bit Bit_vco equaled four).At last, oscillator control voltage VCTR is because running clock FLOCK and control bit Bit_vco that oscillator 208 desires are pinned equal four curve intersection and rest on circle 8.Shown in Figure 11 A, the lower limit VL1 on first group of voltage border of circle 8 pairing oscillator control voltage VCTR distances is far away.In step 1026; Stop time of delay behind comparison oscillator control voltage VCTR and the second group of voltage border; Change second group of voltage border VH2-VL2 to the first group voltage border VH1-VL1; That is relax the voltage border, but the present invention also can not need pass through time of delay, relaxes second group of voltage border VH2-VL2 and gets back to first group of voltage border VH1-VL1.In addition; The present invention also can not need through time of delay comparator 2102 comparison oscillators control voltage VCTR and second group of voltage border VH2-VL2 in step 1012, and also can not need to change through a time of delay second group of voltage border VH2-VL2 to the first group voltage border VH1-VL1 in step 1024.
Please with reference to Figure 12 A and Figure 12 B, Figure 12 A and Figure 12 B are the flow chart of the control method of another embodiment of the present invention explanation low gain voltage controlled oscillator.The method system of Figure 12 A and Figure 12 B utilizes phase-locked loop 200 explanations of Fig. 2, and detailed step is following:
Step 1200: beginning;
Step 1202: the control bit Bit_vco that sets oscillator 208 is zero and oscillator control voltage VCTR is predetermined value Vm;
Step 1204: through DT time of delay, the lower limit VL1 whether the comparator 2102 comparison oscillators control voltage VCTR in the low gain voltage-controlled circuit 210 reduces to first group of voltage border; If carry out step 1206; If, do not skip to step 1210;
Step 1206: controller 2104 adds one with control bit Bit_vco;
Step 1208: after control bit Bit_vco added one, through the time of delay of the comparison oscillator control voltage VCTR upper limit VL1 that whether reduces to first group of voltage border again; If, rebound step 1206; If, carry out step 1210;
Step 1210: comparator 2102 judges that oscillator control voltage VCTR is whether more than or equal to the upper limit VH1 on first group of voltage border; If skip to step 1214; If, carry out step 1212;
Step 1212: through after time of delay, comparator 2102 comparison oscillators control voltage VCTR and second group of voltage border VH2-VL2 skip to step 1216;
Step 1214: stop comparison oscillator control voltage VCTR and first group of voltage border VH1-VL1, skip to step 1228;
Step 1216: the lower limit VL2 whether the comparator 2102 comparison oscillators control voltage VCTR in the low gain voltage-controlled circuit 210 reduces to second group of voltage border; If carry out step 1218; If, do not skip to step 1222;
Step 1218: controller 2104 adds one with control bit Bit_vco;
Step 1220: after control bit Bit_vco added one, through the time of delay of the comparison oscillator control voltage VCTR upper limit VL2 that whether reduces to second group of voltage border again; If, rebound step 1218; If, carry out step 1222;
Step 1222: comparator 2102 judges that oscillator control voltage VCTR is whether more than or equal to the upper limit VH2 on second group of voltage border; If skip to step 1226; If, carry out step 1224;
Step 1224: through after time of delay, change second group of voltage border VH2-VL2 to the first group voltage border VH1-VL1, skip to step 1228;
Step 1226: stop comparison oscillator control voltage VCTR and second group of voltage border VH2-VL2, rebound step 1224;
Step 1228: finish.
Please with reference to Figure 13 A and Figure 13 B; Figure 13 A system explains that according to the method for Figure 12 A and Figure 12 B low gain voltage-controlled circuit 210 is according to first group of voltage border VH1-VL1 and second group of voltage border VH2-VL2; Adjustment control bit Bit_vco; With the sketch map of the running clock that pins oscillator 208, Figure 13 B ties up to the sketch map of key diagram 13A on the time shaft.Shown in Figure 13 A, equal zero and a period of time at control bit Bit_vco, oscillator control voltage VCTR can surpass first group of voltage border VL1 (circle 2,4).Equal at 2 o'clock at control bit Bit_vco, oscillator control voltage VCTR is because running clock FLOCK and control bit Bit_vco that oscillator 208 desires are pinned equal two curve intersection and rest on circle 6.But the lower limit VL1 on first group of voltage border of circle 6 pairing oscillator control voltage VCTR distances is very near, therefore, sees through step 1212, comparator 2102 comparison oscillators control voltage VCTR and second group of voltage border VH2-VL2.Shown in Figure 13 A, circle 6 pairing oscillator control voltage VCTR are less than the lower limit VL2 on second group of voltage border, so control bit Bit_vco adds one (this moment, control bit Bit_vco equaled three).At last, oscillator control voltage VCTR is because running clock FLOCK and control bit Bit_vco that oscillator 208 desires are pinned equal three curve intersection and rest on circle 8.Shown in Figure 13 A, the lower limit VL1 on first group of voltage border of circle 8 pairing oscillator control voltage VCTR distances is far away.In step 1226; Stop time of delay behind comparison oscillator control voltage VCTR and the second group of voltage border; Change second group of voltage border VH2-VL2 to the first group voltage border VH1-VL1; That is relax the voltage border, but the present invention also can not need pass through time of delay, relaxes second group of voltage border VH2-VL2 and gets back to first group of voltage border VH1-VL1.In addition; The present invention also can not need through time of delay comparator 2102 comparison oscillators control voltage VCTR and second group of voltage border VH2-VL2 in step 1212, and also can not need to change through a time of delay second group of voltage border VH2-VL2 to the first group voltage border VH1-VL1 in step 1224.
Please with reference to Figure 14 A and Figure 14 B, Figure 14 A and Figure 14 B are the flow chart of the control method of another embodiment of the present invention explanation low gain voltage controlled oscillator.The method system of Figure 14 A and Figure 14 B utilizes phase-locked loop 200 explanations of Fig. 2, and detailed step is following:
Step 1400: beginning;
Step 1402: the control bit Bit_vco that sets oscillator 208 is that N and oscillator control voltage VCTR are predetermined value Vm;
Step 1404: through DT time of delay, whether the comparator 2102 comparison oscillators control voltage VCTR in the low gain voltage-controlled circuit 210 rises to the upper limit VH1 on first group of voltage border; If carry out step 1406; If, do not skip to step 1410;
Step 1406: controller 2104 subtracts one with control bit Bit_vco;
Step 1408: after control bit Bit_vco subtracted one, through time of delay again comparison oscillator control voltage VCTR whether rise to the upper limit VH1 on first group of voltage border; If, rebound step 1406; If, carry out step 1410;
Step 1410: comparator 2102 judges whether oscillator control voltage VCTR is less than or equal to the lower limit VL1 on first group of voltage border; If skip to step 1414; If, carry out step 1412;
Step 1412: through after time of delay, comparator 2102 comparison oscillators control voltage VCTR and second group of voltage border VH2-VL2 skip to step 1416;
Step 1414: stop comparison oscillator control voltage VCTR and first group of voltage border VH1-VL1, skip to step 1428;
Step 1416: whether the comparator 2102 comparison oscillators control voltage VCTR in the low gain voltage-controlled circuit 210 rises to the upper limit VH2 on second group of voltage border; If carry out step 1418; If, do not skip to step 1422;
Step 1418: controller 2104 subtracts one with control bit Bit_vco;
Step 1420: after control bit Bit_vco subtracted one, through time of delay again comparison oscillator control voltage VCTR whether rise to the upper limit VH2 on second group of voltage border; If, rebound step 1418; If, carry out step 1422;
Step 1422: comparator 2102 judges whether oscillator control voltage VCTR is less than or equal to the lower limit VL2 on second group of voltage border; If skip to step 1426; If, carry out step 1424;
Step 1424: through after time of delay, change second group of voltage border VH2-VL2 to the first group voltage border VH1-VL1, skip to step 1428;
Step 1426: stop comparison oscillator control voltage VCTR and second group of voltage border VH2-VL2, rebound step 1424;
Step 1428: finish.
Please with reference to Figure 15 A and Figure 15 B; Figure 15 A system explains that according to the method for Figure 14 A and Figure 14 B low gain voltage-controlled circuit 210 is according to first group of voltage border VH1-VL1 and second group of voltage border VH2-VL2; Adjustment control bit Bit_vco; With the sketch map of the running clock that pins oscillator 208, Figure 15 B ties up to the sketch map of key diagram 15A on the time shaft.Shown in Figure 15 A; Equal seven and at 6 o'clock at control bit Bit_vco; Oscillator control voltage VCTR can surpass first group of voltage border VL1 (circle 2,4), begins from minion but the present invention is not limited to control bit Bit_vco, and it only is in order to clearly demonstrate the present invention that control bit Bit_vco begins from minion.Equal at 5 o'clock at control bit Bit_vco, oscillator control voltage VCTR is because running clock FLOCK and control bit Bit_vco that oscillator 208 desires are pinned equal five curve intersection and rest on circle 6.But the upper limit VH1 on first group of voltage border of circle 6 pairing oscillator control voltage VCTR distances is very near, therefore, sees through step 1412, comparator 2102 comparison oscillators control voltage VCTR and second group of voltage border VH2-VL2.Shown in Figure 15 A, circle 6 pairing oscillator control voltage VCTR are greater than the upper limit VH2 on second group of voltage border, so control bit Bit_vco subtracts one (this moment, control bit Bit_vco equaled four).At last, oscillator control voltage VCTR is because running clock FLOCK and control bit Bit_vco that oscillator 208 desires are pinned equal four curve intersection and rest on circle 8.Shown in Figure 15 A, the lower limit VL1 on first group of voltage border of circle 8 pairing oscillator control voltage VCTR distances is far away.In step 1426; Stop time of delay behind comparison oscillator control voltage VCTR and the second group of voltage border; Change second group of voltage border VH2-VL2 to the first group voltage border VH1-VL1; That is relax the voltage border, but the present invention also can not need pass through time of delay, relaxes second group of voltage border VH2-VL2 and gets back to first group of voltage border VH1-VL1.In addition; The present invention also can not need through time of delay comparator 2102 comparison oscillators control voltage VCTR and second group of voltage border VH2-VL2 in step 1412, and also can not need to change through a time of delay second group of voltage border VH2-VL2 to the first group voltage border VH1-VL1 in step 1424.
In sum; Provided by the present invention have the phase-locked loop of low gain voltage controlled oscillator and a control method of low gain voltage controlled oscillator; System utilizes at least two group voltage borders; Let and control voltage, can be adjusted by the running clock of second group of voltage border and the pinning of oscillator desire again according to the oscillator that running clock determined of first group of voltage border and the pinning of oscillator desire, thereby away from first group of voltage border.And after the running clock that oscillator control voltage is pinned by second group of voltage border and oscillator desire adjusted, optionally second group of voltage border being relaxed was first group of voltage border.So, will make that the phase-locked loop is more stable, and not influenced by the inner noise in temperature or phase-locked loop.
The above is merely the present invention's preferred embodiment, and all equalizations of being done according to claim scope of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (11)
1. the phase-locked loop with low gain voltage controlled oscillator is characterized in that, described phase-locked loop comprises:
One phase/frequency detector in order to poor according to the phase of a reference clock and a frequency elimination running clock, produce one and detects pulse;
One charge pump is coupled to described phase/frequency detector, in order to according to described detection pulse, produces one and detects voltage;
One low pass filter is coupled to described charge pump, in order to according to described detection voltage, produces a control voltage;
One oscillator is coupled to described low pass filter, in order to produce a running clock according to described control voltage;
One low gain voltage-controlled circuit; Be coupled to described low pass filter and described oscillator; In order to basis at least two group voltage borders; To regulate and control the running clock of described oscillator, wherein utilize one first group of voltage border to fix tentatively described running clock, with one second group of less voltage border of scope described running clock is adjusted to more stable scope again; And
One first frequency eliminator is coupled to described oscillator and described phase/frequency detector, in order to described running clock frequency elimination, to produce described frequency elimination running clock and to be sent to described phase/frequency detector.
2. phase-locked loop as claimed in claim 1 is characterized in that, described low gain voltage-controlled circuit comprises:
One comparator is coupled to described low pass filter, in order to more described oscillator control voltage and described at least two group voltage borders, to produce a comparative result; And
One controller is coupled to described comparator, and in order to according to described comparative result, the control bit that changes described oscillator is to regulate and control the running clock of described oscillator.
3. phase-locked loop as claimed in claim 2 is characterized in that, described low gain voltage-controlled circuit comprises a delay circuit in addition, gets into described comparator in order to postpone described oscillator control voltage.
4. phase-locked loop as claimed in claim 1 is characterized in that, other comprises one second frequency eliminator, is coupled to described phase/frequency detector, in order to an input clock frequency reducing, to produce described reference clock to described phase/frequency detector.
5. the control method of a low gain voltage controlled oscillator is applied to it is characterized in that in the phase-locked loop that described method comprises:
The control bit of setting an oscillator is that a preset position and oscillator control voltage are a predetermined value;
Whether more described oscillator control voltage exceeds the scope on one first group of voltage border;
If described oscillator control voltage exceeds the scope on described first group of voltage border; The control bit that described oscillator is preset is adjusted a stratum, repeats the scope whether more described oscillator control of step voltage exceeds described first group of voltage border again;
If described oscillator control voltage does not exceed the scope on described first group of voltage border, one second group of voltage border is changed on described first group of voltage border;
Whether more described oscillator control voltage exceeds the scope on described second group of voltage border;
If described oscillator control voltage exceeds the scope on described second group of voltage border; The control bit at described oscillator place is adjusted a stratum, repeat the scope whether more described oscillator control of step voltage exceeds described second group of voltage border again; And
If described oscillator control voltage does not exceed the scope on described second group of voltage border, fix the control bit at described oscillator place, and described first group of voltage border recalled on described second group of voltage border;
Wherein said first group of voltage bounds is greater than described second group of voltage border.
6. control method as claimed in claim 5; It is characterized in that the scope whether described oscillator control voltage exceeds one first group of voltage border and described oscillator are controlled the scope whether voltage exceed described second group of voltage border and more comprised:
If described oscillator control voltage is greater than the upper limit on described first group of voltage border, the control bit that described oscillator is preset increases a stratum;
If described oscillator control voltage stops more described oscillator control voltage and described first group of voltage border less than the lower limit on described first group of voltage border;
If described oscillator control voltage is greater than the upper limit on described second group of voltage border, the control bit that described oscillator is preset increases a stratum; And
If described oscillator control voltage is less than the lower limit on described second group of voltage border; Stop more described oscillator control voltage and described second group of voltage border; Fix the control bit at described oscillator place, and described first group of voltage border recalled on described second group of voltage border.
7. control method as claimed in claim 5; It is characterized in that the scope whether described oscillator control voltage exceeds one first group of voltage border and described oscillator are controlled the scope whether voltage exceed described second group of voltage border and more comprised:
If described oscillator control voltage is less than the lower limit on described first group of voltage border, the control bit that described oscillator is preset downgrades a stratum;
If described oscillator control voltage stops more described oscillator control voltage and described first group of voltage border greater than the upper limit on described first group of voltage border;
If described oscillator control voltage is less than the lower limit on described second group of voltage border, the control bit that described oscillator is preset downgrades a stratum; And
If described oscillator control voltage is greater than the upper limit on described second group of voltage border; Stop more described oscillator control voltage and described second group of voltage border; Fix the control bit at described oscillator place, and described first group of voltage border recalled on described second group of voltage border.
8. control method as claimed in claim 5; It is characterized in that the scope whether described oscillator control voltage exceeds one first group of voltage border and described oscillator are controlled the scope whether voltage exceed described second group of voltage border and more comprised:
If described oscillator control voltage is greater than the upper limit on described first group of voltage border, the control bit that described oscillator is preset downgrades a stratum;
If described oscillator control voltage stops more described oscillator control voltage and described first group of voltage border less than the lower limit on described first group of voltage border;
If described oscillator control voltage is greater than the upper limit on described second group of voltage border, the control bit that described oscillator is preset downgrades a stratum; And
If described oscillator control voltage is less than the lower limit on described second group of voltage border; Stop more described oscillator control voltage and described second group of voltage border; Fix the control bit at described oscillator place, and described first group of voltage border recalled on described second group of voltage border.
9. control method as claimed in claim 5; It is characterized in that the scope whether described oscillator control voltage exceeds one first group of voltage border and described oscillator are controlled the scope whether voltage exceed described second group of voltage border and more comprised:
If described oscillator control voltage is less than the lower limit on described first group of voltage border, the control bit that described oscillator is preset increases a stratum;
If described oscillator control voltage stops more described oscillator control voltage and described first group of voltage border greater than the upper limit on described first group of voltage border;
If described oscillator control voltage is less than the lower limit on described second group of voltage border, the control bit that described oscillator is preset increases a stratum; And
If described oscillator control voltage is greater than the upper limit on described second group of voltage border; Stop more described oscillator control voltage and described second group of voltage border; Fix the control bit at described oscillator place, and described first group of voltage border recalled on described second group of voltage border.
10. control method as claimed in claim 5; It is characterized in that the control bit position that described oscillator is preset more comprises the scope that whether exceeds described voltage border through more described again oscillator control one first time of delay voltage after adjusting stratum's step.
11. control method as claimed in claim 5; It is characterized in that, described second group of voltage border recalled to more comprise before described first group of voltage border step through changing described second group of voltage border to described first group of voltage border one second time of delay again.
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| CN112234981A (en) * | 2019-07-15 | 2021-01-15 | 智原科技股份有限公司 | Data and clock recovery circuit |
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| CN1549960A (en) * | 2001-08-29 | 2004-11-24 | ģ���豸��˾ | Phase locked loop fast power up methods and apparatus |
| CN1860685A (en) * | 2003-10-23 | 2006-11-08 | 艾利森电话股份有限公司 | Multiband PLL arrangement and method of controlling such arrangement |
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| CN112234981A (en) * | 2019-07-15 | 2021-01-15 | 智原科技股份有限公司 | Data and clock recovery circuit |
| CN112234981B (en) * | 2019-07-15 | 2024-02-27 | 智原科技股份有限公司 | Data and clock recovery circuit |
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