TW589799B - Charge-pump phase-locked loop circuit with charge calibration - Google Patents

Abstract

A charge-pump phase-locked loop (CP-PLL) circuit with charge calibration. The CP-PLL circuit keeps the phase of an output clock signal constant in a ""locked"" condition, and includes a charge-pump circuit and a calibration circuit. The charge-pump circuit provides a charge-pump output current. The charge-pump circuit also includes a transistor configured to fine tune the charge-pump output current based on a calibrate voltage signal to eliminate a net charge delivered from the charge-pump output current. The calibration circuit senses the net charge and generates the calibrate voltage signal having a value in proportion to an amount of the net charge. Under control of the calibrate voltage signal, the charge-pump circuit cooperating with the transistor regulates the net charge to become exactly zero, thereby maintaining the phase of the output clock signal locked onto the phase of the reference clock signal.

Description

589799 V. Description of the invention (1) The technical field to which the invention belongs The present invention relates to a circuit for a phase locked loop (phase lockeci ιοορ, abbreviated as PLL), particularly a charge-charge pump (charge- pump) PLL circuit. Prior art Generally speaking, electronics, computer systems, and components all have extremely important timing requirements', so that the periodic clock signal generated must be accurately synchronized with the reference clock signal. Phase locked loop (Phase llocked loop, abbreviated as PLL) is a widely used circuit that can precisely control the frequency of its output signal to achieve synchronization with the frequency of the received or input signal. Various applications of the PLL circuit include, but are not limited to, frequency synthesizers, multipliers, dividers, single and multiple clock signal generators, clock signal recovery circuits, and wireless communication devices. … The block diagram in Figure 1 is a typical charge pump PLL circuit (hereinafter referred to as the CP-PLL circuit). The CP-PLL circuit 100 consists of a phase detector 110, a charge pump circuit i 2 (), a loop filter 130, and a voltage-controlled oscillator (v〇ltage — c〇nt; 〇11: d OSC1 1 lator (referred to as VC0) 1 40 and frequency divider 15. The cp-p circuit 100 receives a reference clock signal CLKref with a frequency of Fref and generates an output clock signal CLKout of a frequency Fout, wherein the output clock signal CLK is synchronized in phase with the reference clock signal CLKrei. Reference clock signal CLK ° ut ^ Phase detection and signal comparison. Cross, root red fruit, phase detector 11 0 generate charging signal up and discharge signal to flutter ~ charge pump circuit 1 2 0 supply current to the loop wave filter丨 3 〇 or from circuit a

589799 V. Description of the invention (2) = 7 devices to adjust = circuit. . Wheel CLKQUt, or as shown in Figure 丨, feedback output clock signal output. Although the frequency of the signal generated by the CP-PLL circuit 100, the frequency converter, and the frequency converter 140 is divided by N: two 150, the dust control vibration does not require a frequency divider. . In a certain application, it is possible to make a lightning: v Ho pumping f 2 〇 generates a current 1CP and then cries on the loop filter 1 3 0 Γ t two currents icp are based on the output of the phase detector 110 and Chen Xunfu Come and decide. When the rising edge of the CLKre ^ fl signal leads the rising edge of the CLK'_ signal, the charge pump circuit 120 increases the current Icp to form a larger voltage Vc on the loop gastric filter 130, thus causing voltage-controlled oscillation The device 140 raises the frequency of the CLKout signal; conversely, when the CLKw signal lags behind CLK, the _ signal: the charge pump circuit 120 will reduce the current Icp to form a smaller voltage vc on the loop filter 13 and reduce the voltage-controlled oscillator 140 CLK_ signal frequency j Once the feedback signal frequency F, 〇ut locks the reference clock signal frequency ", that is, the phases of both CLKref Λ and CLK'Qut signals have been aligned, then the voltage Vc will not be adjusted and The output frequency remains fixed. At this time, the state of the cp_pLL circuit 100 is called "Phase Lock." The charge pump circuit 120 internally generates the charging current and the discharging current in response to the up and DN signals. Therefore, the current b is the charging current and the discharging. The sum of the currents. If the CP-PLL circuit is 100, it is phase locked "and the output frequency is 1 ?. “No need to change again” In an ideal situation, the charge and discharge currents would cancel each other out without producing 0608-8537twf (nl); VIU02-0009; mflin.ptd page 7 589799

The net output current Icp 〇 However, the characteristics of the system itself will cause the charging current: Discharge 2: The components and the element fruit, this charging and 1 electric current disproportionate will lead to residual; = = 130, and The step-by-step bow 丨 raises the (m⑻ phenomenon) on the voltage-controlled vibrator 140. In addition to the leakage phenomenon of electrical inductive jitter, it is also a charge accumulation, and the residual source of the m-wave filter in the loop, so that The PLL circuit 100 cannot precisely lock the frequency. It is an urgent need for a circuit of a charge spring phase-locked loop to overcome the prior art. SUMMARY OF THE INVENTION The object of the present invention is to provide a charge correction function to eliminate a fixed fixed output frequency. To achieve the above-mentioned object, the present invention has a circuit that has a function of charge correction and its package. The charge pump circuit provides a charge fruit phase that can track a reference clock signal and an adjustment device. It senses the net charge and adjusts it. The device is used to sense the net charge sensed by the sensing device and includes a regulating device which eliminates the net charge according to the calibration current. The charge pump circuit which operates in conjunction with the calibration device will lock the net charge pump in the phase-locked loop. Circuit, with charge, so that the phase-locked loop can maintain its charge pump circuit and charge pump circuit, and correct the electric current to make an output clock signal To sense the charge pump current to generate the correction voltage signal, the value of which is proportional to the amount. The charge pump circuit is under the control of the positive voltage signal to fine-tune the charge voltage signal. Is zero,

589799 V. Description of the invention (4) Keeping the output clock In the embodiment of the circuit of the present invention, which has and corrects the phase of the circuit Λ 5 tiger, the charge correction is used to continue the lock for disclosure. The phase energy of the clock signal of the first charge pump circuit The tracking-current mirror-output-charge pump circuit is composed of a first charging circuit and a first transistor. The first charge current, its current forms a string of one charge, the second charge of the above-mentioned bit-locked two charge crystal micro-charge sensing number, and the total current in the correction of the first net clock signal implementer current 9, the sum. The first pump circuit of the first current reference circuit adjusts the second circuit root when the first electrical reference is made and adjusts the phase of the voltage signal and the first phase of the discharge. The first charge pump is based on the correction circuit that a transistor can carry. The first includes the second electricity to provide a second charge pump current, and the phases of the clock signals form a series. The charge pump current continues to lock the second net potential under the control of the first and positive voltage signals. The current mirror current is a voltage signal trimmer. The net charge is pumped by an electric charge pump and is phase locked. The most basic is to eliminate a net electricity feedback to the ‘first adjustment to the reference time’, which is a kind of circuit package that provides the first reference time circuit, the charging circuit, the IJ ’s first charge, the clock signal, and the phase of the charge pump lock. The pump circuit of the phase loop causes the current to phase the clock signal. The first first discharging current mirror current mirror circuit provides a first providing a first discharging electric current and a first discharging current and a first charging current mirror circuit to a first charging current, so as to eliminate the current situation of the first electric charge pump circuit. Well, the school first reports the first and second clock signals and charge sensing to simulate the generation of the correction and the second charge-charge pump in the second clock of the lock-out wheel to generate a second electric voltage signal. Electricity is zero, so the phase of the sign. Circuit. In the case of the first phase, the phase of the signal is crystallized with the first and second electric charges. Electric voltage communication Pump circuit. Each will keep the output

〇6〇8-8537twf (nl); viu〇2.〇〇〇09; mfli 589799

In order to make the above-mentioned following of the present invention a preferred embodiment: the purpose, features, and advantages can be more clearly understood, and in conjunction with the accompanying drawings, for detailed description, refer to FIG. 2, the present invention & f 1 CP-PLL) circuit 200 spoons; Scooter phase-locked loop (hereafter referred to as the Gorey circuit ^ αΛ detector 210, speech device M2, electric charge 2ΓΓ electric: skin. 230, voltage-controlled vibrator 24 °, Divider 25. 乂 and positive circuit 20 2 «CP-PLL circuit 20 () receiving frequency is .... clock signal CLKref to generate frequency AF ^ ^. ± Beifeng is the reference% of Fref output clock signal CLK _In: output == LKK〇un, + output signal CLK 'of IF 250. ^ and ^ test wave M Γ on the two phase difference to generate the charging pulse UP and discharge pulse \. Electric pump circuit 220 is charged by The current mirror (current circuit 222 and discharge current mirror circuit 224) is used to provide a charging current of 1? 'While the discharge current mirror circuit 224 is an electric mine. Among them, the output current of the charge pump circuit 220 is 1π -: I second-rate "sum. ^ _Pulse and off pulse, the electric circuit 220 generates thunder γ ^ · ^ γτι / m // ;, lIcp 而Let the phase of the CLKmn signal track the phase: the loop filter 230 applies the input current ^ = wave voltage and outputs it to the voltage-controlled oscillator 240 for use as a frequency-controlled iron bottle ί ° Κ, voltage-controlled oscillator 24 0 Based on the Vc signal, a rainy day clock signal CLKout is generated. In addition, the frequency divider 2 50 is used to divide the frequency FQut of the signal by a predetermined division ratio. By phase detection Christine 210, electric pump circuit 220, loop filter 23o, voltage controlled oscillator 24o, and frequency divider 2 50 to form a CP-PLL circuit are existing technologies. Here we will

589799 V. Description of Invention (6) No more detailed discussion. With continued reference to Figure 2, the cp-pu circuit 200 also includes a correction circuit. The correction circuit is composed of a sensing device 204 and an adjusting device 206. Sensing, setting 2 0 4 is used to sense the net charge △ Q carried by the current Icp, and the adjusting device, and mesh, 1 ^ is used to generate the correction voltage signal Vgu by β, the value of which is equal to that of the sensing device 204 = The number of charges Δ q is proportional. In addition, as shown in FIG. 2, the adjusting device 212 in the electric pump circuit 220 includes a series connection with the charging current mirror circuit 2. The adjusting device m adjusts the current Ip according to the% signal, and adjusts the net charge AQ by 52. Make it exactly zero. In this way, the circuit 200 of the present invention is very suitable for maintaining the phase of the output clock signal accurately to the phase of the reference clock signal. FIG. 3 shows a preferred embodiment of the present invention according to FIG. 2, in which the same symbols in FIG. 2 represent similar elements. For the sake of brevity, 210, the description is given. Finco test 3 'correction circuit 202 is composed of a phase detector 20, an electric pump circuit 220, and a charge sensing circuit 26. Xianghuanxin 210 * The two input terminals are coupled together to receive the same and produce ^ electric pulse wave / two ^ pulse wave DN 'simultaneously at the frequency of the CLKref signal, and the electric charge circuit 22 ′ corresponds to the liver, pulse wave and 〇 and 楗The supply current I CP is used to simulate a 'J-circuit 22' in a phase-locked situation. And 220 'behavior and output characteristics = let the electricity: ,, the two are best to have the same configuration and process, sample, according to the bit detectors 210 and 210' are also based on the same configuration disk, the sense of charge The load ΔJ of the measuring circuit m according to the current Icp is good. Electricity

CP

w M and current I Page 11 〇608-8537twf (nl); VIU02-0009; mflin.ptd 589799 V. Description of the invention (7) ---------: The net charge AQ is carried to generate the correction voltage signal ^ "And the% signal is fed back to the charge pump circuit 220 and the charge pump circuit 22o. Under the control of (a signal 'the electric pump circuit 220 and the charge pump circuit 22o, so the net electricity Ho △ Q, △ Q is adjusted to exactly zero. Next, the present invention is further explained to highlight its characteristics. As shown in FIG. 3, the charge pump circuit 22 0 includes a charging current mirror circuit 222 and a discharge motor mirror circuit 2 24 'switch. The devices 31 'and S2' are connected to the phase detector 210 'and controlled by UP, pulse, and DN, respectively. The switching devices s 1 > and s 2 can be realized by transistors. Charge sensing The circuit 2 6 〇 includes an operational amplifier 2 62 having an output terminal 26 2c and two input terminals 26 2 & 2 6 2b. According to the present invention, the aforementioned regulating device represents a semiconductor transistor, which is described here. Refers to the transistor, whether N-type or p-type metal-oxide-semiconductor (MOS) transistor has a gate, sink And source, because the m0s transistor is generally a device of%, in fact, the reference to the drain and source can only be determined when a voltage is applied to these electrodes. Therefore, the source and sink referred to in this article "Pole" should be interpreted from a broad scope. In accordance with the principles taught by the present invention, the skilled person should be able to understand that other transistor technologies are used to implement the transistor device not shown in the figure. In this implementation, the transistor τ, the electric condenser circuit 220 'is connected in series, and the transistor is connected to a voltage source. Vdd, the drain of the transistor τ is connected to the current mirror circuit 222, and the gate of the transistor τ' is connected to Control node 2 28 of the charge pump circuit 22, ^ Continue to refer to FIG. 3, the output terminal 2 62 of the operational amplifier 26 2 (: is coupled to the control node 228 of the pump circuit 2 2 0 'to provide% With the signal, the input terminal 2 62 a with operational amplification of 262 is coupled to the common contact of the switching device 31 and S2.

0608-8537twf (nl); VIU02-0009; mflin.ptd Page 12 589799

The output terminal 22G ′ is also used to provide current ~. The two pump circuits 1 2 and 9 2 include a switch 2 coupled to the phase detector 21 0 and are turned on or off under the control of the pulse and off pulse respectively. In addition, a transistor τ is connected in series with the charge pump circuit 22. In this embodiment, the source of the transistor τ is connected to the voltage source Vdd, the drain of the transistor τ is connected to the current mirror circuit 22, and the transistor is The gate is connected to the control node 228 of the charge pump circuit 22 0; the output terminal of the operational amplifier 262 "is also switched = the control node 22 8 of the charge I circuit 22G to provide a% signal, and the other input terminal of the operational amplifier 262 262 b is coupled to the switching device si and “common contact 1”, that is, the charge pump circuit 22o is used to provide the current output terminal 0. In this implementation, the porosity generated by the phase detector 21〇 (21〇,) The phase difference between the factory) and DN (DN,) pulse signals is roughly equal to the phase difference between the input signals. During the period when the UP pulse is applied to the switching device S1, the switching device si is therefore turned on and the charging current l provided by the current mirror circuit 22 2 flows into the loop filter 2 3 0; otherwise, the DN pulse is applied to the switching device s During the period 2, the switching device S2 is therefore turned on and the discharge current IN provided by the current mirror circuit 224 flows out of the loop filter 2 3 0. The output current ICP of the charge pump circuit 2 2 0 is the sum of the charging current Ip and the discharging current IN, that is, L = Ip + (— In). In order to avoid the problem of the dead zone, the UP and DN pulses generated by phase detection ^ 21〇 must have a minimum width (duration) to ensure that the charge system circuit 2 2 0 can have sufficient time to start, and the dead zone It basically reflects a range of phase difference, and the phase detector cannot generate enough pulse width in this range to start the charge pump circuit. In the correction circuit 202,

589799

It is best to use a similar method as described above. 5. Description of the invention (9) The phase detector 2 1 0 ′ operates, so Γ and the charge pump circuit 22 0 ’CP = I’P + (-I’N). The loop filter 230 in the second figure is represented by a first-order filter including resistors. Based on the principle of the listener & α ，, those skilled in the art should be able to understand ^ day First-order chirpers for the teaching examples. According to the invention, the UP pulse of the DP will cause the storage of the charging current Ip to be equivalent to ϋ to ^, and the pulse of the width τN will cause the discharge current In y to be charged. ; Electricity is equivalent to the charge of InTn. Ideally, when the PLL circuit is in phase-locked condition, the phase current IP should be equal to the discharge current UUP pulse width \ should be equal to the charge τN, but it is not so perfect in reality. The synthesized current ^ will produce = I ^ Tp + (-INTN) The net charge AQ is left on the loop filter 23o to form a residual field. The charge pump circuit 22 0 ′ is used to provide the net charge AQ to simulate the net charge ΔQ on the filter 2 30, where Δq, = I, τ, + Bu I ,,, According to the present invention, the charge pump circuits 220 and 220, and the cup P are specially designed and the ancient j NN ′ ′ can be taken to have the same characteristics. The operational amplifier 26 0 senses the net charge AQ on its input terminal 26 2a,

The net charge △ Q on its input terminal 2 6 2 b, if the net charge △ q, once and zero, the operational amplifier 26 0 will increase the correction voltage signal Vcal, and the variable signal will be returned to the transistor T and T ′. At the same time, the charging current 丨 and CAL P 丄 p are reduced, 'fine fine-tune the net power △ Q and △ Q'; on the contrary, if the number of net power lines Δ q is less than zero, the operational amplifier 260 will reduce the correction voltage signal, The smaller vCAL signal is fed back to the transistor τ and τ, which will cause the current Ip and I′P to increase at the same time; in this way, the net charge ^^ and AQ will eventually disappear.

589799

" Divide and open A to zero. In the middle, because the operational amplifier 260 is arranged as "negative feedback", Shi Er's households will use the potentials of the two input terminals of the operational amplifier 2 60 to chase each other. There exists between the input terminals "仏 and 2625. "Short circuit", "ugly road" means that all voltages appearing on input terminal 262a are combined from ί f-input terminal 2625. Therefore, when the net charge △ 〇, i zero ^ / Yin Dianhe △ Q also Will follow to eliminate. Therefore, there will be no charge on the loop filter 23 (), and the output clock signal frequency can be maintained, and the output clock CLK0ut is synchronized with the reference clock signal CLKref in phase without jitter. Anyone skilled in this art should know: arrange 6 charge current $ circuit 222 or 222 ', discharge current mirror circuit 224 or 224, or their group α to form a series connection with the transistor to eliminate the net remaining on the loop filter 2 3 0 The charge AQ is also considered to be implemented under the principles taught by the present invention. Now refer to Figure 4, which is the first variant of Figure 2, as shown in the figure 'regulating device 2 1 2' and discharge current. The mirror circuits 2 2 4 are connected in series, and the rest of the structure is the same as the functional block diagram of FIG. 2. The adjusting device 2 丨 2 adjusts the current Ιν according to the VCAL signal value, thereby fine-tuning the net charge Δ 卩 to exactly zero. In a similar manner as previously described, the CP-PLL circuit 200 can eliminate the charge remaining on the loop filter 230 as much as possible to maintain a stable state. … Figure 5 is the second variant of Figure 2. As shown in the figure, the regulating device 2 1 2 and the charging current mirror circuit 2 2 2 form a series 'in addition, the regulating device 2 1 2' and discharge The current mirror circuit 2 2 4 forms a series connection, and it is particularly special: the adjustment device 206 also generates another correction voltage signal V, cal, and its value and sensing device

0608-8537twf (nl); VIU02-0009; mflin.ptd page 15 589799 5. Description of the invention (11) The amount of net charge sensed by the device 204 is proportional. Anyone skilled in this art should understand that the adjustment devices 212 and 212, both of which are made by the same correction voltage η ', are also considered to be implemented under the principles taught by the present invention. The function block diagram in Figure 2 is the same. Adjust the H signal Δ cal signal value to adjust the current 1p, on the other hand, adjust the $ \ LI ΐ and the signal value to adjust the current 1n, so fine-tune the net charge to 々, which keeps the output frequency fixed. In addition, when outputting, the phase of the signal CLU reference clock signal CLKj can be exactly the same as that of the real time: = exposed as 1, but it is only for this embodiment, anyone familiar with this: art :::::: It is defined by the scope of the appended patent application ^ Protection of the present invention page 16 0608-8537twf (nl); ViU02-0009; mflin.ptd 589799 The diagram is briefly explained. The first diagram is the phase lock circuit of the electric circuit of the prior art. The blocks are not intended. Figure 2 is a functional block diagram of the charge pump phase-locked loop with charge correction function of the present invention; Figure 3 is a block diagram of the preferred embodiment of Figure 2 of the present invention; Figure 4 is the present invention Figure 2 its first variant Functional block diagrams; and Figure 5 is a functional block diagram of the second variant of Figure 2 of the present invention. Symbol description 1 0 0 ~ typical charge pump phase-locked loop 1 1 0 ~ phase detector 1 2 0 ~ Charge pump circuit 1 3 0 ~ loop filter 140 ~ voltage controlled oscillator (VCO) 1 50 0 ~ frequency divider 2 0 0 ~ charge pump phase-locked loop circuit 202 ~ correction circuit 2 0 4 ~ sensing device of the present invention 2 0 6 ~ Adjustment device 2 1 0, 2 1 0 '~ Phase detector 2 1 2, 2 1 2' ~ Adjustment device 2 2 0, 2 2 0 '~ Charge pump circuit 222, 222' ~ Charge current mirror circuit 224, 224 '~ discharge current mirror circuit

0608-8537twf (nl); VIU02-0009; mf1in.ptd Page 17 589799 Brief description of the diagram 2 2 6, 2 2 6 '~ Common contact 2 2 8, 2 2 8' ~ Control node 2 3 0 ~ Loop Filter 24 0 ~ Voltage controlled oscillator (VCO) 2 5 0 ~ Divider 2 6 0 ~ Charge sensing circuit 2 6 2 ~ Operational amplifier T, T '~ Transistor SI, S2 ~ Switching device SI', S2 '~ Switching device UP, UP' ~ Charging pulse DN, DN '~ Discharging pulse

Ip, I 'p ~ charging current IN, I' N ~ discharging current

Icp, 1 ′ cp ~ charge pump current C L ~ output clock signal C L Kw ~ reference clock signal CLK’m ~ divider output signal R ~ resistor C ~ capacitor

Vdd ~ voltage source

0608-8537twf (nl); VIU02-0009; mflin.ptd Page 18

Claims (1)

Sixth, the scope of the patent application is an electric charge pump charge pump phase-locked circuit, which uses the phase of the clock signal to track the circuit including at least the micro-charge value and its zero, the second signal of the borrowed signal, its current discharge, And the charge 3. Road, its connection, and the current, is zero. Adjust the power and correct the power in a sense and adjust the sensor, and maintain the phase with the correction power. As mentioned in the application, the current of the discharge pump is as described in the application and the micro-first adjustment of the pump current path, at least measuring the device, the entire device, and the patented range charge pump when the output of the first voltage regulating signal is sensed. The electric circuit, the current mirror, the charging patent range, the first adjustment of the first adjustment of the above electric circuit to provide two = two at least include: reference time # ″ charge pump current and let one output time device, = Cheng Huanzhi Phase, the charge pump is used to eliminate; two: the correction voltage and the current contained in the pump current are included in the net include:, for sensing and + for production ":; charge; the * to the Net; a correction voltage signal is proportional to the number of its cracks; the charge pump circuit that controls the D operation in the absence of a clock signal, adjusts the net charge to exactly the phase of ~ and continues to lock the reference clock: 1 The electric charge mine ts of the Λ charge is the phase-locked loop of the charging circuit — the charging current mirror circuit and the circuit are used to provide-the sum of the charging current and the discharge current and the discharge current. Device The electricity of this electric / 7-pump phase-locked loop correction voltage 2 The electric current mirror circuit forms a series of charge pump thunder and six-point values to adjust the above-mentioned charge 7 The net charge carried by the motor is just right 589799 6. Application for patent scope 4. The circuit of the charge pump phase-locked circuit as described in item 3 of the scope of patent application, wherein the above-mentioned charge pump circuit further includes a second adjustment device formed with the above-mentioned discharge current mirror circuit In series, and adjust the discharge current according to the value of the first correction voltage signal, thereby fine-tuning the net charge carried by the charge pump current to exactly zero. 5. The circuit of the charge pump phase-locked circuit according to item 3 of the scope of the patent application, wherein the charge pump circuit further includes a second adjustment device, and the second adjustment device is connected in series with the discharge current mirror circuit, wherein the adjustment device A second correction voltage signal is also generated, the value of which is proportional to the amount of the net charge sensed by the sensing device, the first adjustment device adjusts the charging current according to the value of the first correction voltage signal, and the The second adjusting device adjusts the discharge current according to the value of the second correction voltage signal, so as to fine-tune the net charge carried by the charge pump current to exactly zero. 6. The circuit of the phase locked loop of the charge pump according to item 2 of the scope of the patent application, wherein the first adjustment device is connected in series with the discharge current mirror circuit, and the discharge current is adjusted according to the value of the first correction voltage signal, Thereby, the net charge carried by the charge pump current is adjusted to exactly zero. 7. The circuit of the charge pump phase-locked loop as described in item 6 of the scope of patent application, wherein the charge pump circuit further includes at least a second adjusting device, the second adjusting device is in series with the charging current mirror circuit 5 and according to The value of the first correction voltage signal adjusts the charging current, thereby fine-tuning the net charge carried by the charge pump current to exactly zero. 0608-8537twf (nl); VIU02-0009; mf1 in.ptd page 20 589799 6. Application for patent scope 8. The circuit of the charge pump phase-locked loop described in item 1 of the scope of patent application, further includes at least: a frequency division A device for dividing the frequency of the above-mentioned output clock signal by a predetermined division ratio; a voltage-controlled oscillator for generating the above-mentioned output clock signal having a variable frequency according to a frequency-controlled voltage signal;-a loop filter For filtering the input charge pump current to generate a filtered voltage, and outputting the filtered voltage to the voltage-controlled oscillator for the frequency control voltage signal; and a phase detector for detecting the output signal of the frequency divider And a phase difference between the reference clock signal to generate a charging pulse and a discharging pulse, wherein the charge pump circuit generates the electric current according to the charging pulse and the discharging pulse. 9. A circuit of a charge pump phase locked loop, comprising at least: a first charge pump circuit for providing a first charge pump current so that a phase of an output clock signal can track a phase of a reference clock signal, the charge pump The circuit includes at least: a first charging current mirror circuit for providing a first charging current; a first discharging current mirror circuit for providing a first discharging current; and a first transistor and the first charging A current mirror circuit is formed in series, and the first charging current is fine-tuned according to a first correction voltage signal to eliminate a first net charge carried by the first charge pump current; 0608-8537twf (nl); VIU02-0009; mflin.ptd Page 21 The sum of the first charging current and the first 'the first electric discharge current; ° 7 pumping ^ is the correction circuit: at least: ~ Chang Yilai simulates a cypress drop 7 circuit to provide a second charge pump electric drop β 1 f and the shape of Γ zeng form a charge pump current when the output is known, and The phase-locked inertia and the phase of ~~ lock the phase of the reference clock signal; the electric sensing circuit, Tian ,, t The second charge pump current is used according to the first-first voltage signal, and ride well # 弟 —The net electric charge is used to generate the first correction electric current and the second electric charge circuit. Only the unjust pressure signal is fed back to the first transistor, and the first thunderbolt is used as the first thunderbolt. The He Guo circuit and the first transistor are operated together to control the control voltage of the first paint ^ R ^ brother ^ correction voltage signal to zero, so as to maintain the value of 打 = the second net charge is adjusted to just hit The phase of the output clock signal. The UI phase continues to lock the reference clock 10. For example, the circuit of the 9th phase of the scope of the patent application of the Chou Jiaming patent, wherein the electrical circuit of the phase-locked loop of the second charge pump circuit and the second discharge current mirror / contains a second charging current The mirror provides-the first: i! The second discharge current mirror circuit uses a discharge current, and the second charge pump current is the sum of the first charge current and the second discharge current. 1 1 · The circuit of the charge pump phase-locked loop as described in item 10 of the scope of the patent application, wherein the second charge pump circuit further includes a second transistor, 々, --------- ^^ _ The second electric circuit is connected in series with the second charging current mirror circuit according to the aforementioned body, and the second charging is adjusted by fine-tuning the first correction voltage signal. Current, | i is zero °. The second net charge carried by the second charge pump current to the positive ^ j 2 path, wherein the second electric charge of the charge pump phase-locked loop described in item 10 of the patent application range ^ the second charge pump circuit is more “I contains a second transistor” according to the above-mentioned body and the second discharge current mirror circuit is connected in series, and the second discharge current is adjusted by trimming the upper and lower: correction voltage signals to obtain zero. The above-mentioned second net electric charge carried by the second electric charge pump current is positive to zero. ------... ▼ One n% Kezhen Zhengshi Road, the complex charge-locked loop described in item 11 of the scope of the patent application, the "ΐ;"-the charge pump circuit at least contains-the third electricity! Said / the second above The game described above is that the first discharge current mirror circuit is connected in series, and the crystal is connected to the above-mentioned at least one fourth transistor, the fourth: the correction voltage gas: = the current mirror circuit is connected in series according to the above 1 Fine-tune i ϊ Π? Above the first and the second discharge voltage ΐ-the secret above, the first order 2 il carried by the first charge pump current, the second net power / the first charge pump current Why is electricity ^ 14. Electricity as described in item 10 of the scope of patent application; exactly zero. The above-mentioned second charge-based circuit further includes at least the _ lock circuit of the electric circuit and the second discharge current mirror circuit = : Transistor, "According to the above-mentioned and the second net charge, the upper loop is connected in series, and it generates a second correction voltage signal. The second transistor senses electricity and a positive voltage signal to adjust the second discharge voltage = The second book of two M imitation above III !! _ 面 L _______ ^ 1111 0608-8537twf (nl); VIU02-0009; mflin.ptd page 23 charge pump 15 'its third third crystal and the first one correct the positive voltage to fine-tune the second 16 one output charge pump current; The above mentioned second #. If the scope of the patent application, item u, is exactly zero. : The above-mentioned charge-based circuit item returns less electricity. The transistor of the phase-locked loop and the above-mentioned first discharge = 3 a second transistor. The second charge fruit circuit at least includes a circuit in series, and the second Discharge current mirror 2: transistor, the fourth electricity and the above-mentioned second net electric charge, are connected in series. Among them, according to the upper voltage signal, the third and second :: He sensing circuit also generates-No. Adjust the above-mentioned second brother four-transistor according to the second school $ first-charge pump current carried by the second and second current 'borrowed Ho pump current carried by the above m > first / r electric ho and up, a charge pump lock The phase loop's lightning / electricity is exactly zero. The first charge pump circuit is used to pick up electricity: one, the phase from the first to the clock signal can track one: the two—the electric pump current so that the circuit contains at least: 4 the phase of the day-keeping clock signal, the first charging current A mirror circuit for providing a first charging current; and a first-discharging current mirror circuit for providing a first-discharging current r, a first transistor, and the first discharging current mirror circuit forming a string I ^ first correction Voltage signal to fine-tune the first discharge current to eliminate one of the first net charge carried by the first charge pump current; wherein the first charge pump current is the sum of the first charge current and the first discharge current ; 0608-8537twf (nl); VIU02-0009; mflin.ptd Page 24 A correction circuit includes at least: a second charge pump circuit for providing a second charge pump current shape, the first charge pump current in a phase-locked situation, and the phase-locked condition The phase of the clock signal locks the phase of the reference clock signal;. # A charge sensing circuit is configured to generate the first correction voltage ^ A ′ according to the first net charge and one of the second net charges carried by the two lotus currents and return the first correction voltage signal back To the first transistor and the second charge pump circuit; wherein the second charge pump circuit and the first charge pump circuit operating in cooperation with the first transistor are under the control of the first correction voltage signal ^ Don't adjust the first net charge and the second net charge to exactly zero 'to maintain the phase of the output clock signal and continue to lock the phase of the signal. Z, the loss of 4 is known, wherein the second charge pump circuit includes at least a second discharge current mirror circuit, the second charge 2 current 鸯 the second charge current, and the second discharge thunder cold Ϊ k mirror electricity Hibernian circuit and rose electric current, 0608-8537twf (nl); ViU02-0009; mflin > ptd page 25 is used to provide-the second mirror current to provide a second discharge current, and the second = mirror circuit then a charge current and the second discharge The sum of the currents.仃 7 The current is the circuit described in item 17 of the scope of the patent application, wherein the second charge circuit includes at least one phase loop circuit, = two transistors and the second discharge current mirror circuit: two The transistor adjusts 1 series' and 589799 according to the above-corrected voltage signal. To fine tune the above to zero. The above-mentioned second net electric charge carried by the two charge pump currents is exactly 19 · As described in the charge-pump phase-locked loop described in item 17 of the scope of patent application ^, wherein the second charge-pump circuit more rarely includes a second electric charge The crystal is connected in series with the second charging current mirror circuit, and the # -correcting voltage tfl is used to adjust the above-mentioned number: the charging current,: f, which is carried by the second charge pump current. The above-mentioned second net charge is zero. ^ Good. • The charge pump phase-locked loop f as described in item 17 of the sigma patent range, wherein the second charge pump circuit further includes at least a second electric circuit: the first transistor and the second charging current mirror. The circuit repeats the following: the first charge and the second net charge described above, and the charge: the measurement generates a first-corrected voltage signal, and the second transistor is based on the second charge. Road ί to adjust the above-mentioned second charging current, so as to fine-tune the second description; the power of the pump is adjusted to the above-mentioned second net electric charge to be exactly zero. second