CN102446924A - Nonvolatile memory unit structure and forming method thereof - Google Patents
Nonvolatile memory unit structure and forming method thereof Download PDFInfo
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- CN102446924A CN102446924A CN2011103143427A CN201110314342A CN102446924A CN 102446924 A CN102446924 A CN 102446924A CN 2011103143427 A CN2011103143427 A CN 2011103143427A CN 201110314342 A CN201110314342 A CN 201110314342A CN 102446924 A CN102446924 A CN 102446924A
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Abstract
The invention provides a nonvolatile memory unit structure, wherein a grid electrode is arranged on the surface of a semiconductor silicon wafer, the grid electrode is provided with a side wall, and the side wall is made of a low-k dielectric material. Compared with the prior art, the nonvolatile memory unit structure provided by the invention has the advantages that: a coupling interference problem of a nonvolatile memory is automatically reduced, therefore related additional circuits of IRO (Interfering Reduction Operation) are saved, a coupling interference reducing method is effectively simplified, a memory circuit design can be effectively simplified, and the integration level and the memory reading-writing rate are improved.
Description
Technical field
The present invention relates to field of semiconductor manufacture, the method that relates in particular to a kind of nonvolatile storage location structure and form this cellular construction.
Background technology
Because the existence of non-volatile memory unit floating boom or electric charge capture layer; When non-volatile memory unit when constantly the distance between scaled and per two word lines becomes too close; Can produce the coupled interference problem; The threshold voltage shift that causes memory unit component, the significant problem that this will face in high-order node such as the IC products technology below the 45nm.
Chinese patent CN101483065A has disclosed a kind of method and non-volatility memorizer thereof of operational store, wherein before the operation of routine or general program, carry out coupled interference reduce operation (Interfering Reduction Operation, IRO).Concrete grammar is before non-volatile memory unit is carried out sequencing; In advance memory cell is charged; The Partial charge iunjected charge is caught layer; Thereby reduce or compensation coupled interference effect, make the action pane that corresponding device threshold voltage distributed when down-stream background storage unit read " 1 " and " 0 " increase effect.In the document of above-mentioned disclosure,, be unfavorable for the raising and the memory read/write faster of integrated level though coupled interference problem that can effective less nonvolatile memory makes memory circuitry more complicated.
Chinese patent CN102034874A has disclosed a kind of non-volatility memorizer; Its structure comprises a Semiconductor substrate; The current channel zone that in Semiconductor substrate, forms; The drain region that a side in said current channel zone forms in said Semiconductor substrate with first kind of doping type, the source region that the non-drain region side in said current channel zone forms in said Semiconductor substrate, the ionization by collision zone that is used to produce ionizing collision that between said current channel zone and said source region, forms with second kind of doping type; Cover the ground floor gate dielectric layer that said current channel zone forms; The floating gate region with conductivity as charge-storage node that on said ground floor gate dielectric layer, forms covers the second layer gate dielectric layer that said floating gate region forms, the control grid that forms on the said second layer gate dielectric layer.
Chinese patent CN1770455A has disclosed a kind of non-volatility memorizer, is made up of dielectric layer, tunneling dielectric layer and source/drain region between substrate, a plurality of gate stack structure, clearance wall, a plurality of control grid, a plurality of floating grid, grid.Each gate stack structure is selection gate dielectric, selection grid and cap layer in regular turn from substrate.Clearance wall is positioned at the gate stack structure sidewall.The control grid is positioned in the substrate, fills up the gap between the gate stack structure, and is connected to each other together.Floating grid is between gate stack structure, and between control grid and substrate.Dielectric layer is between control grid and floating grid between grid.Tunneling dielectric layer is between floating grid and substrate.Source/drain region lays respectively in the substrate of outermost two gate stack structures, one side.
The spacer material of present non-volatile device still rests on traditional side wall technology, promptly adopts SiO
2Perhaps Si
3N
4Perhaps its combination is as spacer material.And SiO
2Relative dielectric constant be 3.9, Si
3N
4Relative dielectric constant SiO especially
2Twice.When non-volatile memory unit when constantly the distance between scaled and per two word lines becomes too close, the coupled interference problem will be more and more serious.
Summary of the invention
The present invention is directed to the coupled interference problem that exists in the present non-volatility memorizer; A kind of new coupled interference minimizing method is proposed; Make the coupling effect between adjacent word line weaken; Thereby effectively simplified the coupled interference minimizing, and effectively simplified the memory circuitry design, improved integrated level and memory read writing speed.
To achieve these goals, a kind of nonvolatile storage location structure is provided, is provided with grid on the semi-conductor silicon chip surface, said grid is provided with side wall, and said side wall is the low-K dielectric material.
In the above-mentioned memory unit that provides, described grid comprises tunnel oxide, floating grid layer, electric charge barrier layer and control grid layer from the bottom up or comprises tunnel oxide, electric charge capture layer, electric charge barrier layer and control grid layer.
In the above-mentioned memory unit that provides, described low-K dielectric material is the SiO behind the carbon dope
2, Si
3N
4In one or more mixtures.
Another object of the present invention is to provide the method that forms the said memory unit of claim 1; On semi-conductor silicon chip, form grid; Deposition low-K dielectric material on grid and semiconductor silicon plate; Have the low-K dielectric layer than low-k thereby carry out carbon doping formation in the deposition process, etching is removed unnecessary low-K dielectric layer and is formed grid curb wall.
In the above-mentioned method that provides, described grid is the sandwich construction grid.Grid on semi-conductor silicon chip, deposits tunnel oxide, floating grid layer, electric charge barrier layer and control grid layer through priority and the etching redundance forms.Grid equally also can be through successively depositing tunnel oxide, electric charge capture layer, electric charge barrier layer and control grid layer and the etching redundance forms on semi-conductor silicon chip.
In the above-mentioned method that provides, described low-K dielectric material is the SiO of carbon dope
2, Si
3N
4In one or more mixtures.
Nonvolatile storage location structure provided by the invention is compared with existing; Automatically reduce the coupled interference problem of nonvolatile memory; Thereby saved the relevant adjunct circuit of IRO; Effectively simplify coupled interference minimizing method, can effectively simplify the memory circuitry design, improved integrated level and memory read writing speed.
Description of drawings
Fig. 1 is the sketch map of nonvolatile storage location structure of the present invention.
Embodiment
The present invention provides a kind of nonvolatile storage location structure, and this cellular construction is included in the semi-conductor silicon chip surface and is provided with grid, and said grid is provided with side wall, and said side wall is the low-K dielectric material.
The main flow non-volatility memorizer has the floating gate type of employing device architecture at present, and the trap charge capturing of employing type device architecture is also arranged.Their operation principle is basic identical: through in the source, leakage, grid add that suitable voltage is programmed and erase operation, in floating boom/capture layer, injects or pull out electric charge, can change the threshold voltage of device, thereby realize stored logic " 1 " or " 0 ".Charge stored in floating boom/capture layer promptly has non-volatile because the protection of peripheral insulator is difficult for losing.
The piled grids that grid is made up of floating grid (floating gate) and control grid (control gate) in the floating gate type nonvolatile memory; Electric charge barrier layer places between floating boom and the control gate, and tunnel oxide is between floating boom and device channel.Control grid connective word line (word line), floating boom is used for stored charge.Modal is to adopt polysilicon as floating boom, and the control grid is used for control and writes/read operation.And for trap charge capturing type non-volatility memorizer spare; Substitute floating grid with electric charge capture layer (charge trapping layer), adopt silicon nitride as electric charge capture layer like SONOS (Silicon-Oxide-Nitride-Oxide-Semiconductor) device.
Because the existence of non-volatile memory unit floating boom or electric charge capture layer; When non-volatile memory unit when constantly the distance between scaled and per two word lines becomes too close; Can produce the coupled interference problem; The threshold voltage shift that causes memory unit component, in high-order node such as the IC products technology below the 45nm problem special obviously.
Further specify the present invention through embodiment below, so that better understand the content of the invention, but following embodiment does not limit protection scope of the present invention.
Embodiment 1
As shown in Figure 1, on semi-conductor silicon chip, deposit tunnel oxide 5, floating grid layer 4, electric charge barrier layer 3 and control grid layer 2 and etching redundance successively and form the sandwich construction grid.Deposition one Si on grid and semiconductor silicon plate
3N
4The layer, in the deposition process to Si
3N
4Layer carries out carbon and mixes, and has the Si than low-k thereby form
3N
4Layer, etching is removed the Si of unnecessary low-k
3N
4Layer, thus grid curb wall formed.
Embodiment 2
As shown in Figure 1, on semi-conductor silicon chip, deposit tunnel oxide 5, floating grid layer 4, electric charge barrier layer 3 and control grid layer 2 and etching redundance successively and form the sandwich construction grid.Deposition one SiO on grid and semiconductor silicon plate
2And Si
3N
4The layer, in the deposition process to SiO
2And Si
3N
4Layer carries out carbon and mixes, and has the SiO than low-k thereby form
2And Si
3N
4Layer, etching is removed the SiO of unnecessary low-k
2And Si
3N
4Layer, thus grid curb wall formed.
Embodiment 3
Present embodiment is on the basis of embodiment 1, deposition tunnel oxide 5, electric charge capture layer, electric charge barrier layer 3 and control grid layer 2 and etching redundance on semi-conductor silicon chip and form the sandwich construction grid.The side wall that forms is the SiO behind the carbon dope
2Material.
The nonvolatile storage location structure that the present invention proposes, is carried out carbon simultaneously and is mixed in the process of deposit spacer material layer to the coupled interference problem of nonvolatile memory, thereby reduces the dielectric constant of spacer material greatly, like SiO
2After the carbon doping, relative dielectric constant can drop to below 2.7.Adopt the side wall of the material preparation non-volatile memory unit of low-k, make that the coupling effect between adjacent word line weakens, thereby effectively simplified coupled interference minimizing method.
More than specific embodiment of the present invention is described in detail, but it is just as example, the present invention is not restricted to the specific embodiment of above description.To those skilled in the art, any equivalent modifications that the present invention is carried out with substitute also all among category of the present invention.Therefore, not breaking away from impartial conversion and the modification of being done under the spirit and scope of the present invention, all should contain within the scope of the invention.
Claims (8)
1. a nonvolatile storage location structure is characterized in that, is provided with grid on the semi-conductor silicon chip surface, and said grid is provided with side wall, and said side wall is the low-K dielectric material.
2. according to the said memory unit of claim 1, it is characterized in that said grid comprises tunnel oxide, floating grid layer, electric charge barrier layer and control grid layer from the bottom up.
3. according to the said memory unit of claim 1, it is characterized in that said grid comprises tunnel oxide, electric charge capture layer, electric charge barrier layer and control grid layer from the bottom up.
4. according to the said memory unit of claim 1, it is characterized in that said low-K dielectric material is the SiO behind the carbon dope
2, Si
3N
4In one or more mixtures.
5. method that forms the said memory unit of claim 1; Be characterised in that; On semi-conductor silicon chip, form grid; Deposition low-K dielectric material on grid and semiconductor silicon plate has the low-K dielectric layer than low-k thereby carry out carbon doping formation in the deposition process, and etching is removed unnecessary low-K dielectric layer and formed grid curb wall.
6. method according to claim 5 is characterized in that, said grid on semi-conductor silicon chip, deposits tunnel oxide, floating grid layer, electric charge barrier layer and control grid layer through priority and the etching redundance forms.
7. method according to claim 5 is characterized in that, said grid on semi-conductor silicon chip, deposits tunnel oxide, electric charge capture layer, electric charge barrier layer and control grid layer through priority and the etching redundance forms.
8. according to the described method of claim 5, it is characterized in that said low-K dielectric material is the SiO of carbon dope
2, Si
3N
4In one or more mixtures.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011103143427A CN102446924A (en) | 2011-10-17 | 2011-10-17 | Nonvolatile memory unit structure and forming method thereof |
| US13/339,422 US20130065385A1 (en) | 2011-09-08 | 2011-12-29 | Method for preparing spacer to reduce coupling interference in mosfet |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011103143427A CN102446924A (en) | 2011-10-17 | 2011-10-17 | Nonvolatile memory unit structure and forming method thereof |
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| CN102446924A true CN102446924A (en) | 2012-05-09 |
Family
ID=46009272
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|---|---|---|---|
| CN2011103143427A Pending CN102446924A (en) | 2011-09-08 | 2011-10-17 | Nonvolatile memory unit structure and forming method thereof |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1822330A (en) * | 2005-01-10 | 2006-08-23 | 应用材料公司 | Method for producing gate stack sidewall spacers |
| KR100672934B1 (en) * | 2003-09-25 | 2007-01-23 | 삼성전자주식회사 | Semiconductor devices having low-k dielectric |
| CN1917234A (en) * | 2005-08-16 | 2007-02-21 | 旺宏电子股份有限公司 | Low-k spacer structure for flash memory |
-
2011
- 2011-10-17 CN CN2011103143427A patent/CN102446924A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100672934B1 (en) * | 2003-09-25 | 2007-01-23 | 삼성전자주식회사 | Semiconductor devices having low-k dielectric |
| CN1822330A (en) * | 2005-01-10 | 2006-08-23 | 应用材料公司 | Method for producing gate stack sidewall spacers |
| CN1917234A (en) * | 2005-08-16 | 2007-02-21 | 旺宏电子股份有限公司 | Low-k spacer structure for flash memory |
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Application publication date: 20120509 |