CN102446891B - Manufacturing method of metal-oxide-metal capacitor - Google Patents
Manufacturing method of metal-oxide-metal capacitor Download PDFInfo
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- CN102446891B CN102446891B CN201110307976.XA CN201110307976A CN102446891B CN 102446891 B CN102446891 B CN 102446891B CN 201110307976 A CN201110307976 A CN 201110307976A CN 102446891 B CN102446891 B CN 102446891B
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Abstract
The invention relates to a high-performance metal-oxide-metal capacitor and a manufacturing method thereof. The purpose that a film with two kinds of k values exists in the same metal dielectric layer is realized by selectively photoetching the metal dielectric layer, a non-MOM (Metal-Oxide-Metal) region is filled with a low-k medium, and an MOM region is filled with a high-k medium, therefore the high-performance metal-oxide-metal capacitor is realized, the chip area is saved, and the cost is reduced; meanwhile, the high-performance metal-oxide-metal capacitor and the manufacturing method thereof are adaptive to the traditional process.
Description
Technical field
The present invention relates to a kind of MOM (metal-oxide-metal) electric capacity and preparation method thereof, belong to integrated circuit manufacture, relate in particular to a kind of high-performance metal-oxide-metal capacitor and preparation method thereof.
Background technology
Along with constantly dwindling of cmos device size, the dielectric constant k of the interconnected dielectric medium used of its back segment also constantly reduces, people also, constantly finding new dielectric material, have developed into FSG, SiOC from initial simple silicon dioxide, until the ultralow k film of 45nm node porous once.
Structural representation with reference to the genus-oxide-metal capacitance of figure 1 and prior art illustrated in fig. 2, wherein, in order better to describe, Fig. 1 has divided copper-connection region 1 and metal-oxide-metal capacitor region 1, Fig. 2 is the sectional view at A-A ' line place in Fig. 1, can find, in copper-connection region 1 and metal-oxide-metal capacitor region 2, what all adopt is low K value film 3.
Current technical development is, along with the reduction of film k value, in interconnection, the capacitor C of integrated formed objects just needs larger area (C ∝ K), and the waste of area has just increased the cost of manufacture of chip.
Therefore, provide a kind of and can effectively improve metal-oxide-metal capacitor performance, interconnection structure adopts the structure of low K film just to seem particularly important simultaneously.
Summary of the invention
The object of the invention is is to realize high k and low k film with photoetching optionally, thereby realizes high-performance MOM on high k film, and can keep the superiority of the low k of conventional interconnect.
The present invention discloses a kind of high-performance metal-oxide-metal capacitor, wherein, comprising:
Be formed on the first dielectric layer film on the first etching barrier layer, described the first dielectric layer film comprises the first high K value region and the first low K value region, on described the first dielectric layer film, is coated with the first low-K dielectric layer film;
Be formed on the second dielectric layer film on the second etching barrier layer, described the second dielectric layer film comprises the second high K value region and the second low K value region, on described the second dielectric layer film, is coated with the second low-K dielectric layer film;
Described the second etching barrier layer covers described the first low-K dielectric layer film, and described the second high K value region is positioned at the vertical top in described the first high K value region, and described the second low K value region is positioned at the vertical top in described the first low K value region;
Described the first low-K dielectric layer film that is arranged in described the first high K value region and top, the first low K value region is respectively arranged with metal filled some lower groove, described the second low-K dielectric layer film that is arranged in the second high K value region and top, the second low K value region is respectively arranged with metal filled some upper groove, at least corresponding lower groove of groove in the vertical direction on each;
The contact hole that vertically runs through the second low-K dielectric layer film, the second dielectric layer film and the second etching barrier layer, each contact hole overlaps with the upper groove in the vertical direction of second top, low K value region respectively, and contact is positioned at the vertically lower groove of below of described contact hole.
Above-mentioned high-performance metal-oxide-metal capacitor, wherein, the material in described the first high K value region is USG, FSG, BD, a kind of in BD1 or BDII, the material in described the first low-K dielectric layer film and described the first low K value region is USG, FSG, BD, in BD1 or BDII than low a kind of of described the first high K value region K value.
Above-mentioned high-performance metal-oxide-metal capacitor, wherein, described the first high K value region is identical with the material in the second high K value region, described the first low K value region is identical with the material in the second low K value region, and described the first low-K dielectric layer film is identical with the material of the second low-K dielectric layer film.
Above-mentioned high-performance metal-oxide-metal capacitor, wherein, described the first dielectric layer film is identical with described the second dielectric layer film thickness, and described the first low-K dielectric layer film is identical with the thickness of the second low-K dielectric layer film.
Above-mentioned high-performance metal-oxide-metal capacitor, wherein, described the first dielectric layer film and described the second dielectric layer film thickness span are
described the first low-K dielectric layer film and the second low-K dielectric layer film thickness span are
According to another aspect of the present invention, also disclose a kind of manufacture method of high-performance metal-oxide-metal capacitor, wherein, comprise the steps:
One wafer that is deposited with the first etching barrier layer is provided;
Deposit the first dielectric layer film on described the first etching barrier layer, described the first dielectric layer film comprises the first high K value region and the first low K value region;
Deposit the first low-K dielectric layer film covers described the first dielectric layer film;
Be arranged in described the first low-K dielectric layer film above the first high K value region and the first low K value region some lower groove of etching fill metal respectively;
The first low-K dielectric layer film described in chemical-mechanical planarization;
Deposit the second etching barrier layer covers described the first low-K dielectric layer film;
Deposit the second dielectric layer film on described the second etching barrier layer, described the second dielectric layer film comprises the second high K value region and the second low K value region, described the second high K value region is positioned at the vertical top in described the first high K value region, and described the second low K value region is positioned at the vertical top in described the first low K value region;
Deposit the second low-K dielectric layer film covers described the second dielectric layer film;
Be arranged in described the second low-K dielectric layer film above the second high K value region and the second low K value region respectively etching some on groove, a groove in the vertical direction lower groove of correspondence at least each on;
Etching contact hole in the second low K value region of described the second dielectric layer film, described contact hole overlaps with the upper groove in the vertical direction in a second low K value region, and contact is positioned at its vertically lower groove of below;
On described, in groove and described contact hole, fill metal;
The second low-K dielectric layer film described in chemical-mechanical planarization.
Above-mentioned manufacture method, wherein, the process of the making of described the first dielectric layer film comprises the steps:
Deposit the one K value dielectric material covers described the first etching barrier layer;
Etching is removed the described K value dielectric material of part, and etching terminates in described the first etching barrier layer, is positioned at the first etching barrier layer exposure that a K value dielectric material is removed part below;
Deposit the 2nd K value dielectric material covers the part of a described K value dielectric material and described the first etching barrier layer exposure;
The 2nd K value dielectric material and a described K value dielectric material described in chemical-mechanical planarization, expose a described K value dielectric material.
Above-mentioned manufacture method, wherein, the process of the making of described the second dielectric layer film comprises the steps:
Deposit the one K value dielectric material covers described the second etching barrier layer;
Etching is removed the described K value dielectric material of part, and etching terminates in described the second etching barrier layer, is positioned at the first etching barrier layer exposure that a K value dielectric material is removed part below;
Deposit the 2nd K value dielectric material covers the part of a described K value dielectric material and described the first etching barrier layer exposure;
The 2nd K value dielectric material and a described K value dielectric material described in chemical-mechanical planarization, expose a described K value dielectric material.
Above-mentioned manufacture method, wherein, a described K value dielectric material is USG, FSG, BD, a kind of in BD1 or BDII, described the 2nd K value dielectric material is USG, FSG, BD, in BD1 or BDII than low a kind of of a described K value dielectric material K value.
Above-mentioned manufacture method, wherein, described the first dielectric layer film is identical with described the second dielectric layer film thickness, and described the first low-K dielectric layer film is identical with the thickness of the second low-K dielectric layer film.
Above-mentioned manufacture method, wherein, described the first dielectric layer film and described the second dielectric layer film thickness span are
described the first low-K dielectric layer film and the second low-K dielectric layer film thickness span are
The present invention is carried out photoetching etching to metal dielectric layer and is realized and in same layer metal dielectric layer, have two kinds of k value films by selective, non-MOM region is filled with low k dielectric, make MOM region adopt high K dielectric, realized high performance metal-oxide-metal capacitor, save chip area, reduced cost.
Accompanying drawing explanation
By reading the detailed description of non-limiting example being done with reference to the following drawings, it is more obvious that the present invention and feature thereof, profile and advantage will become.In whole accompanying drawings, identical mark is indicated identical part.Deliberately proportionally do not draw accompanying drawing, focus on illustrating purport of the present invention.In the accompanying drawings, for cheer and bright, part parts have been amplified.
Fig. 1 is the vertical view of the metal-oxide-metal capacitor of prior art;
Fig. 2 is the sectional view at A-A ' line place in Fig. 1;
Fig. 3 shows according to of the present invention, a kind of structural representation of high-performance metal-oxide-metal capacitor;
Fig. 4 a to Fig. 4 d shows according to of the present invention, each step of the manufacture method of the first dielectric layer film in a kind of high-performance metal-oxide-metal capacitor; And
Fig. 5 a to Fig. 5 c shows and on the first dielectric layer film, makes first each step of low-K dielectric layer film.
Embodiment
Below in conjunction with the drawings and the specific embodiments, the present invention is further elaborated.Embodiment described herein is only for explaining the present invention, the protection range being not intended to limit the present invention.
With reference to shown in figure 3 according to of the present invention, a kind of structural representation of high-performance metal-oxide-metal capacitor, in order to improve the performance of electric capacity, in copper-connection region 1 and MOM (metal-oxide-metal) region, 2 adopt different dielectric materials.Particularly, electric capacity of the present invention comprises:
Be formed on the first dielectric layer film 201 on the first etching barrier layer 101, described the first dielectric layer film 201 comprises the 211 and first low K value region 221, the first high K value region, on described the first dielectric layer film 201, be coated with the first low-K dielectric layer film 203, preferably, the first low-K dielectric layer film 203 is identical with the material in the first low K value region 221;
Be formed on the second dielectric layer film 202 on the second etching barrier layer 102, described the second dielectric layer film comprises the 212 and second low K value region 222, the second high K value region, on described the second dielectric layer film 202, be coated with the second low-K dielectric layer film 204, preferably, the second low-K dielectric layer film 204 is identical with the material in the second low K value region 222;
Described the second etching barrier layer 102 covers described the first low-K dielectric layer film 203, described the second high K value region 212 is positioned at the vertical top in described the first high K value region 211, and described the second low K value region 222 is positioned at the vertical top in described the first low K value region 221;
Described the first low-K dielectric layer film 203 that is arranged in 221 tops, the 211 and first low K value region, the first high K value region is respectively arranged with metal filled some lower groove 301, in the 212 and second low K value region 222, the second high K value region of described the second dielectric layer film 202, be respectively arranged with metal filled some upper groove 302, at least corresponding lower groove 301 of groove 302 in the vertical directions on each;
The contact hole 303 that vertically runs through the second dielectric layer film 202 and the second etching barrier layer 102, each contact hole 303 overlaps in (with reference to figure 3) respectively at upper groove 302 in the vertical directions of 222 tops, a second low K value region, and contact is positioned at the vertically lower groove 301 of below of described contact hole 303.
Particularly, in high-performance metal-oxide-metal capacitor of the present invention, the material in described the first high K value region 211 is USG, FSG, BD, a kind of in BD1 or BDII, the material in described the first low-K dielectric layer film 203 and described the first low K value region 221 is USG, FSG, BD, in BD1 or BDII than low a kind of of described the first high K value region 211K value.
More specifically, described the first high K value region 211 is identical with the material in the second high K value region 212, described the first low K value region 221 is identical with the material in the second low K value region 222, described the first low-K dielectric layer film 203 is identical with the material of the second low-K dielectric layer film 204, preferably, the material in described the first low-K dielectric layer film 203, the 221 and second low K value region 222, the low K value of the second low-K dielectric layer film 204, first region all adopts same.
In a specific embodiment, described the first dielectric layer film 201 is identical with described the second dielectric layer film 202 thickness, described the first low-K dielectric layer film 203 identical with the thickness of the second low-K dielectric layer film 204.
Preferably, described the first dielectric layer film 201 and described the second dielectric layer film 202 Thickness scopes are
described the first low-K dielectric layer film 203 and the second low-K dielectric layer film 204 Thickness scopes are
The present invention is selective to be carried out photoetching etching to metal dielectric layer and realizes and in same layer metal dielectric layer, have two kinds of k value films, and non-MOM region is filled with low k dielectric.Below realization of the present invention is elaborated, wherein, for prior art processes such as etching, chemical-mechanical planarizations, do not describe in detail, the technique that how to adopt photoresist to carry out etching is not emphasis of the present invention, and those skilled in the art can be in conjunction with processing step described in existing techniques in realizing.With reference to figure 3, and in conjunction with Fig. 4 a to Fig. 4 d and Fig. 5 a to Fig. 5 c, the performing step of the inventive method is:
First, provide a wafer that is deposited with the first etching barrier layer 101;
Then deposit the first dielectric layer film 201 on described the first etching barrier layer 101, described the first dielectric layer film comprises the 211 and first low K value region 221, the first high K value region;
Deposit the first low-K dielectric layer film 203 covers described the first dielectric layer film 201;
Then be arranged in the first low-K dielectric layer film 203 above the 211 and first low K value region 221, the first high K value region some lower groove 301 of etching fill metal respectively;
The first low-K dielectric layer film 203 described in chemical-mechanical planarization again;
Then deposit the second etching barrier layer 102 covers described the first low-K dielectric layer film 203;
Deposit the second dielectric layer film 202 on described the second etching barrier layer 102 again, described the second dielectric layer film 202 comprises the 212 and second low K value region 222, the second high K value region, described the second high K value region 212 is positioned at the vertical top in described the first high K value region 211, and described the second low K value region 222 is positioned at the vertical top in described the first low K value region 221;
Deposit the second low-K dielectric layer film 204 covers described the second dielectric layer film 202;
Then be arranged in described the second low-K dielectric layer film 204 above the 212 and second low K value region 222, the second high K value region distinguish etchings some on groove 301, a groove 302 in the vertical directions lower groove 301 of correspondence at least on each;
Etching contact hole 303 in the second low K value region 222 of described the second dielectric layer film 202, described contact hole 303 overlaps with upper groove 302 in the vertical directions of 222 tops, a second low K value region, and contact is positioned at its vertically lower groove 301 of below;
On described, in groove 302 and described contact hole 303, fill metal;
Finally, the second low-K dielectric layer film 204 described in chemical-mechanical planarization, has just obtained structure as shown in Figure 3.
Again in conjunction with showing according to of the present invention with reference to figure 4a to Fig. 4 f, each step of a kind of high-performance metal-oxide-metal capacitor manufacture method, Fig. 4 a to Fig. 4 f shows the manufacture method of the individual layer dielectric layer film in high-performance metal-oxide-metal capacitor of the present invention, and the another thin making of one dielectric layer can realize with reference to figure 4a to Fig. 4 f.
Described the first dielectric layer film 201 deposit comprise the steps:
First, as shown in Fig. 4 a, deposit the one K value dielectric material 401 covers described the first etching barrier layer 101;
Etching is removed the described K value dielectric material 401 of part again, and etching terminates in described the first etching barrier layer 101, is positioned at the first etching barrier layer 101 exposures that a K value dielectric material 401 is removed part below;
Deposit the 2nd K value dielectric material 402 covers the part of a described K value dielectric material 401 and described the first etching barrier layer 101 exposures;
The 2nd K value dielectric material 402 and a described K value dielectric material 401 described in last chemical-mechanical planarization, expose a described K value dielectric material;
On described the 2nd K value dielectric material 402 and a described K value dielectric material 401, etching forms some lower groove 301 and fills metal respectively;
The 2nd K value dielectric material 402 and a described K value dielectric material 401 described in machinery planarization.
Like this, just obtained having the first dielectric layer film 201 of different K values areas of dielectric, in a preference, the one K value dielectric material 401 adopts K value than the little material of K value of the 2nd K value dielectric material 402, like this, 1 use the one K value dielectric material 401 in copper-connection region is as dielectric medium, then at MOM region 2 use the 2nd K value dielectric material 402 as dielectric medium.
At one, change in example, the one K value dielectric material 401 adopts K value than the large material of K value of the 2nd K value dielectric material 402, with reference to figure 3, the one K value dielectric materials 401, just form the first high K value region 211, the two K value dielectric materials 402 and just formed the first low K value region 221.
Further, described the second dielectric layer film 202 deposit comprise the steps:
Deposit the one K value dielectric material 401 covers described the second etching barrier layer 102;
Etching is removed the described K value dielectric material 401 of part, and etching terminates in described the second etching barrier layer 102, is positioned at the first etching barrier layer 102 exposures that a K value dielectric material 401 is removed part below;
Deposit the 2nd K value dielectric material 402 covers the part of a described K value dielectric material 401 and described the first etching barrier layer 102 exposures;
The 2nd K value dielectric material 402 and a described K value dielectric material 401 described in chemical-mechanical planarization, expose a described K value dielectric material 401;
On described the 2nd K value dielectric material 402 and a described K value dielectric material 401 respectively etching form some on groove 302;
Etching contact hole 303 in described the 2nd K value dielectric material 402 and described K value dielectric material 401 material that K value is lower between the two, on described contact hole 303 and, groove 302 in the vertical directions are overlapping, and described contact hole 303 bottom contacts one are positioned at its vertically lower groove 301 of below;
On described, in groove 302 and described contact hole 303, fill metal;
The 2nd K value dielectric material 402 and a described K value dielectric material 401 described in machinery planarization.
With reference to figure 5a to Fig. 5 c, below describe the course of processing of the first low-K dielectric layer film 203 on the first dielectric layer film 201 in detail, as Fig. 5 a, elder generation's deposit first low-K dielectric layer film 203 on the first dielectric layer film 201 being formed by the 2nd K value dielectric material 402 and a K value dielectric material 401, then some lower groove 301 of etching on the first low-K dielectric layer film 203, etching terminates on the first dielectric layer film 201, wherein, part lower groove 301 is positioned at the vertical top of the 2nd K value dielectric material 402, part lower groove 301 is positioned at the vertical top of a K value dielectric material 401.Then carry out metal filled processing step, generally fill copper to complete copper interconnection structure.Similarly, those skilled in the art can realize the course of processing of the second low-K dielectric layer film 204 on the second dielectric layer film 202 in conjunction with prior art, do not repeat them here.
Preferably, a described K value dielectric material 401 is USG, FSG, BD, a kind of in BD1 or BDII, described the 2nd K value dielectric material 402 is USG, FSG, BD, in BD1 or BDII than low a kind of of a described K value dielectric material 401K value.
In a specific embodiment, described the first dielectric layer film 201 is identical with described the second dielectric layer film 202 thickness, and described the first low-K dielectric layer film 203 is identical with the thickness of the second low-K dielectric layer film 204.
Further, described the first dielectric layer film 201 and described the second dielectric layer film thickness 202 spans are
described the first low-K dielectric layer film 203 and the second low-K dielectric layer film 204 Thickness scopes are
Those skilled in the art can realize described variation example in conjunction with prior art and above-described embodiment, and such variation example does not affect flesh and blood of the present invention, does not repeat them here.
Above preferred embodiment of the present invention is described.It will be appreciated that, the present invention is not limited to above-mentioned specific implementations, and the equipment of wherein not describing in detail to the greatest extent and structure are construed as with the common mode in this area to be implemented; Any those of ordinary skill in the art, do not departing from technical solution of the present invention scope situation, all can utilize method and the technology contents of above-mentioned announcement to make many possible changes and modification to technical solution of the present invention, or being revised as the equivalent embodiment of equivalent variations, this does not affect flesh and blood of the present invention.Therefore, every content that does not depart from technical solution of the present invention,, all still belongs in the scope of technical solution of the present invention protection any simple modification made for any of the above embodiments, equivalent variations and modification according to technical spirit of the present invention.
Claims (6)
1. a manufacture method for metal-oxide-metal capacitor, is characterized in that, comprises the steps:
One wafer that is deposited with the first etching barrier layer is provided;
Deposit the first dielectric layer film on described the first etching barrier layer, described the first dielectric layer film comprises the first high K value region and the first low K value region;
Deposit the first low-K dielectric layer film covers described the first dielectric layer film;
Be arranged in described the first low-K dielectric layer film above the first high K value region and the first low K value region some lower groove of etching fill metal respectively;
The first low-K dielectric layer film described in chemical-mechanical planarization;
Deposit the second etching barrier layer covers described the first low-K dielectric layer film;
Deposit the second dielectric layer film on described the second etching barrier layer, described the second dielectric layer film comprises the second high K value region and the second low K value region, described the second high K value region is positioned at the vertical top in described the first high K value region, and described the second low K value region is positioned at the vertical top in described the first low K value region;
Deposit the second low-K dielectric layer film covers described the second dielectric layer film;
Be arranged in described the second low-K dielectric layer film above the second high K value region and the second low K value region respectively etching some on groove, a groove in the vertical direction lower groove of correspondence at least each on;
Etching contact hole in the second low K value region of described the second dielectric layer film, described contact hole overlaps with the upper groove in the vertical direction of second top, low K value region, and contact is positioned at its vertically lower groove of below;
On described, in groove and described contact hole, fill metal;
The second low-K dielectric layer film described in chemical-mechanical planarization.
2. manufacture method according to claim 1, is characterized in that, the process of the making of described the first dielectric layer film comprises the steps:
Deposit the one K value dielectric material covers described the first etching barrier layer;
Etching is removed the described K value dielectric material of part, and etching terminates in described the first etching barrier layer, is positioned at the first etching barrier layer exposure that a K value dielectric material is removed part below;
Deposit the 2nd K value dielectric material covers the part of a described K value dielectric material and described the first etching barrier layer exposure;
The 2nd K value dielectric material and a described K value dielectric material described in chemical-mechanical planarization, expose a described K value dielectric material.
3. manufacture method according to claim 1, is characterized in that, the process of the making of described the second dielectric layer film comprises the steps:
Deposit the one K value dielectric material covers described the second etching barrier layer;
Etching is removed the described K value dielectric material of part, and etching terminates in described the second etching barrier layer, is positioned at the first etching barrier layer exposure that a K value dielectric material is removed part below;
Deposit the 2nd K value dielectric material covers the part of a described K value dielectric material and described the first etching barrier layer exposure;
The 2nd K value dielectric material and a described K value dielectric material described in chemical-mechanical planarization, expose a described K value dielectric material.
4. according to the manufacture method described in claim 2 or 3, it is characterized in that, a described K value dielectric material is USG, FSG, BD, a kind of in BD1 or BDII, described the 2nd K value dielectric material is USG, FSG, BD, in BD1 or BDII than low a kind of of a described K value dielectric material K value.
5. manufacture method according to claim 1, is characterized in that, described the first dielectric layer film is identical with described the second dielectric layer film thickness, and described the first low-K dielectric layer film is identical with the thickness of the second low-K dielectric layer film.
6. manufacture method according to claim 5, is characterized in that, described the first dielectric layer film and described the second dielectric layer film thickness span are
described the first low-K dielectric layer film and the second low-K dielectric layer film thickness span are
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