CN102446891A - High-performance metal-oxide-metal capacitor and manufacturing method thereof - Google Patents

High-performance metal-oxide-metal capacitor and manufacturing method thereof Download PDF

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CN102446891A
CN102446891A CN201110307976XA CN201110307976A CN102446891A CN 102446891 A CN102446891 A CN 102446891A CN 201110307976X A CN201110307976X A CN 201110307976XA CN 201110307976 A CN201110307976 A CN 201110307976A CN 102446891 A CN102446891 A CN 102446891A
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low
dielectric
layer
region
film
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CN102446891B (en
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姬峰
张亮
李磊
胡友存
陈玉文
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上海华力微电子有限公司
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Abstract

The invention relates to a high-performance metal-oxide-metal capacitor and a manufacturing method thereof. The purpose that a film with two kinds of k values exists in the same metal dielectric layer is realized by selectively photoetching the metal dielectric layer, a non-MOM (Metal-Oxide-Metal) region is filled with a low-k medium, and an MOM region is filled with a high-k medium, therefore the high-performance metal-oxide-metal capacitor is realized, the chip area is saved, and the cost is reduced; meanwhile, the high-performance metal-oxide-metal capacitor and the manufacturing method thereof are adaptive to the traditional process.

Description

一种高性能金属-氧化物-金属电容及其制作方法 A high performance metal - oxide - metal capacitor and its manufacturing method

技术领域 FIELD

[0001] 本发明涉及一种MOM (metal-oxide-metal)电容及其制作方法,属于集成电路制造,尤其涉及一种高性能金属-氧化物-金属电容及其制作方法。 [0001] The present invention relates to a MOM (metal-oxide-metal) capacitor and a manufacturing method of manufacturing an integrated circuit belongs to, in particular, it relates to a high performance metal - oxide - metal capacitor and its manufacturing method.

背景技术 Background technique

[0002] 随着CMOS器件尺寸的不断缩小,其后段互联所用的介电质的介电常数k也不断降低,人们也在不断寻找新的介电质材料,从最初单纯的二氧化硅发展到了FSG、SiOC,直到45nm节点一下的多孔的超低k薄膜。 [0002] As device sizes continue to shrink CMOS, thereafter interconnecting dielectric sections used also continue to lower a dielectric constant k, people are constantly looking for new dielectric materials, pure silica from the initial development to FSG, SiOC, until about 45nm node porous ultra low-k film.

[0003] 参考图1和图2所示出的现有技术的属-氧化物-金属电容的结构示意图,其中, 为了更好的进行说明,图1划分了铜互连区域1和金属-氧化物-金属电容区域1,图2为图1中A-A'线处的截面图,可以发现,铜互连区域1和金属-氧化物-金属电容区域2中, 都采用的是低K值薄膜3。 Genus [0003] Referring to FIG. 1 and the prior art shown in FIG. 2 - oxide - a schematic structure of a metal capacitor, wherein, in order to better be described, FIG. 1 divided region 1 and the copper interconnect metal - oxide was - metal capacitor region 1, FIG. 1, FIG. 2 is a a-a 'cross-sectional view along line can be found, and a copper interconnect metal region 1 - oxide - 2, are used in the metal region is a capacitor low K 3 film.

[0004] 目前的技术发展是,随着薄膜k值的降低,在互连中集成相同大小的电容C就需要更大的面积(C OC K),面积的浪费就增加了芯片的制作成本。 [0004] The current technological development, the film with lower k values, integrated in the same size interconnection capacitance C requires larger area (C OC K), wasted area increases the production cost of the chip.

[0005] 因此,提供一种能够有效提高金属-氧化物-金属电容性能,同时互连结构采用低K薄膜的结构就显得尤为重要了。 [0005] Accordingly, there is provided a metal can improve - oxide - metal capacitor performance, while the structure of the interconnect structure using low-K film is particularly important.

发明内容 SUMMARY

[0006] 本发明的目的是是用选择性的光刻来实现高k和低k薄膜,从而在高k薄膜上实现高性能Μ0Μ,而能保持传统互连低k的优越性。 [0006] The object of the present invention is to realize a high selective photolithography k and low-k film, thereby achieving high performance in the high-k film Μ0Μ, while maintaining the advantages of conventional low-k interconnects.

[0007] 本发明公开一种高性能金属-氧化物-金属电容,其中,包括: [0007] The present invention discloses a high performance metal - oxide - metal capacitor, comprising:

形成在第一刻蚀阻挡层上的第一介电层薄膜,所述第一介电层薄膜包括第一高K值区域和第一低K值区域,所述第一介电层薄膜上覆盖有第一低K值介电层薄膜; A first dielectric thin film layer formed on the first etch stop layer, the first dielectric layer comprises a first high K thin film region and the first low-K regions, covering the first dielectric layer films a first low K dielectric layer of the film;

形成在第二刻蚀阻挡层上的第二介电层薄膜,所述第二介电层薄膜包括第二高K值区域和第二低K值区域,所述第二介电层薄膜上覆盖有第二低K值介电层薄膜; The second dielectric layer is a thin film formed on the second etch stop layer, said second dielectric layer comprises a second high K thin film region and the second low-K regions, covering said second dielectric layer films a second low K dielectric layer of the film;

所述第二刻蚀阻挡层覆盖所述第一低K值介电层薄膜,所述第二高K值区域位于所述第一高K值区域的竖直上方,所述第二低K值区域位于所述第一低K值区域的竖直上方; The second etch stop layer overlying the first layer of low K dielectric film, said second high K region located vertically above the first high K region, the second low K region located vertically above the region of the first low-K;

位于所述第一高K值区域和第一低K值区域上方的所述第一低K值介电层薄膜中分别设置有金属填充的若干下沟槽,位于第二高K值区域和第二低K值区域上方的所述第二低K 值介电层薄膜中分别设置有金属填充的若干上沟槽,每一个上沟槽在竖直方向上至少对应一个下沟槽; Located in the first region and the high K above the first region of the first low-K dielectric layer is a low K value are respectively provided with a metal film filling the trench number, located in the second region and the high K the region above the two second low-K dielectric layer is a low K value are respectively provided with a plurality of thin film metal-filled trench, the trench corresponding to each of the at least one groove in a vertical direction;

竖直贯穿第二低K值介电层薄膜、第二介电层薄膜和第二刻蚀阻挡层的接触孔,每一个接触孔分别与一个第二低K值区域上方的上沟槽在竖直方向上重合,并接触位于所述接触孔竖直下方的下沟槽。 Vertically through the second low K dielectric layer of the film, a second dielectric layer on the trench and the contact hole a second thin etch stop layer, each second contact holes respectively a low K value in the region above the vertical direction coincides with the straight, and positioned in contact with the lower vertical trench below the contact hole.

[0008] 上述的高性能金属-氧化物-金属电容,其中,所述第一高K值区域的材料为USG, FSG, BD, BDl或BDII中一种,所述第一低K值介电层薄膜以及所述第一低K值区域的材料为USG,FSG,BD, BDl或BDII中比所述第一高K值区域K值低的一种,。 [0008] The high-performance metal - oxide - metal capacitor, wherein the material of the first region is high K USG, FSG, BD, BDl BDII or in one of the first low K dielectric a thin film layer of a first material and said region of low K USG, FSG, BD, BDl BDII or lower than the first high K values ​​K region one of.

[0009] 上述的高性能金属-氧化物-金属电容,其中,所述第一高K值区域和第二高K值区域的材料相同,所述第一低K值区域和第二低K值区域的材料相同,所述第一低K值介电层薄膜和第二低K值介电层薄膜的材料相同。 [0009] The high-performance metal - oxide - metal capacitor, wherein the same material of the first region and the second high K high K region, the first region and the second low-K value low K region of the same material, the first low K dielectric layer of the film material and the second low K dielectric layer of the same film.

[0010] 上述的高性能金属-氧化物-金属电容,其中,所述第一介电层薄膜和所述第二介电层薄膜厚度相同,所述第一低K值介电层薄膜和第二低K值介电层薄膜的厚度相同。 [0010] The high-performance metal - oxide - metal capacitor, wherein said thin film first dielectric layer and said second dielectric layer is the same as the film thickness of the first low K dielectric layer of the film and same thickness of the titanium layer of low K dielectric films. [0011 ] 上述的高性能金属-氧化物-金属电容,其中,所述第一介电层薄膜和所述第二介电层薄膜厚度取值范围均为100(Γ10000Α,所述第一低K值介电层薄膜和第二低K值介电层薄膜厚度取值范围均为100(Γ10000Α。 [0011] The high-performance metal - oxide - metal capacitor, wherein said first dielectric layer and said second dielectric film layer of the film thickness ranges are 100 (Γ10000Α, the first low-K value film and the second dielectric layer low K dielectric layer of the film thickness ranges are 100 (Γ10000Α.

[0012] 根据本发明的另一个方面,还公开一种高性能金属-氧化物-金属电容的制作方法,其中,包括如下步骤: [0012] According to another aspect of the present invention, there is disclosed a high performance metal - oxide - metal capacitor manufacturing method, comprising the steps of:

提供一淀积有第一刻蚀阻挡层的晶圆; Providing a wafer deposited with a first etch stop layer;

在所述第一刻蚀阻挡层上淀积第一介电层薄膜,所述第一介电层薄膜包括第一高K值区域和第一低K值区域; Depositing a first dielectric thin film layer on the first etch stop layer, the first dielectric film comprises a first layer of high K region and the first region of low K;

淀积第一低K值介电层薄膜覆盖所述第一介电层薄膜; Depositing a first low K dielectric layer covering the first thin film dielectric layer;

在位于第一高K值区域和第一低K值区域上方的所述第一低K值介电层薄膜中分别刻蚀若干下沟槽并填充金属; Located above the first region and the high K value of the first region of the first low-K dielectric layer low K films are etched trenches and the plurality of fill metal;

化学机械平坦化所述第一低K值介电层薄膜; 淀积第二刻蚀阻挡层覆盖所述第一低K值介电层薄膜; A first chemical mechanical planarization of the low K dielectric layer of the film; etching the first deposition of the second low K dielectric layer covering the barrier layer of the film;

在所述第二刻蚀阻挡层上淀积第二介电层薄膜,所述第二介电层薄膜包括第二高K值区域和第二低K值区域,所述第二高K值区域位于所述第一高K值区域的竖直上方,所述第二低K值区域位于所述第一低K值区域的竖直上方; Depositing a second dielectric thin film layer on the third barrier layer, the second dielectric layer comprises a second high K thin film region and the second low K region, the second region of high K positioned vertically above the first high K region, the second region of the low K vertically above said first region of low K;

淀积第二低K值介电层薄膜覆盖所述第二介电层薄膜; Depositing a second layer of low K dielectric film covering the second dielectric layer of the film;

在位于第二高K值区域和第二低K值区域上方的所述第二低K值介电层薄膜中分别刻蚀若干上沟槽,每一个上沟槽在竖直方向上至少对应一个下沟槽; Located above the second region and the second high K region of the second low-K dielectric layer low K films are etched on a plurality of grooves, each groove corresponding to the at least one in the vertical direction lower trench;

在所述第二介电层薄膜的第二低K值区域中刻蚀接触孔,所述接触孔与一个第二低K 值区域中的上沟槽在竖直方向上重合,并接触位于其竖直下方的下沟槽; 在所述上沟槽和所述接触孔中填充金属; 化学机械平坦化所述第二低K值介电层薄膜。 In the second area of ​​the second low K dielectric layer thin film etched contact holes, the contact hole and a second low-K regions on the groove coincides in the vertical direction, and contacting in its vertically below the lower trench; filler metal in the trench and the contact hole; second chemical mechanical planarization of the low K dielectric layer of the film.

[0013] 上述的制作方法,其中,所述第一介电层薄膜的制作的过程包括如下步骤: 淀积第一K值介电材料覆盖所述第一刻蚀阻挡层; [0013] The above-described manufacturing method, wherein the dielectric layer forming a first thin film a process comprising the steps of: depositing a first K dielectric material covering the first etch stop layer;

刻蚀去除部分所述第一K值介电材料,刻蚀止于所述第一刻蚀阻挡层,位于第一K值介电材料去除部分下方的第一刻蚀阻挡层暴露; The first portion is removed by etching K dielectric material, etch stop at the first etch stop layer, located between the first K dielectric material is removed below the exposed portion of the first etch stop layer;

淀积第二K值介电材料覆盖所述第一K值介电材料和所述第一刻蚀阻挡层暴露的部 Depositing a second value K dielectric material overlying the first K dielectric material of the first etch stop layer and the exposed portion

分; Minute;

化学机械平坦化所述第二K值介电材料和所述第一K值介电材料,使所述第一K值介电材料暴露。 The second chemical mechanical planarization K dielectric material and the first K dielectric material, the first K dielectric material is exposed.

[0014] 上述的制作方法,其中,所述第二介电层薄膜的制作的过程包括如下步骤: 淀积第一K值介电材料覆盖所述第二刻蚀阻挡层;刻蚀去除部分所述第一K值介电材料,刻蚀止于所述第二刻蚀阻挡层,位于第一K值介电材料去除部分下方的第一刻蚀阻挡层暴露; [0014] The above-described manufacturing method, wherein said second dielectric layer is made of a thin film process comprising the steps of: depositing a first dielectric value K dielectric material covering said second etch stop layer; portion removed by etching said first K dielectric material, etch stop at the second etch stop layer, located between the first K dielectric material is removed below the exposed portion of the first etch stop layer;

淀积第二K值介电材料覆盖所述第一K值介电材料和所述第一刻蚀阻挡层暴露的部 Depositing a second value K dielectric material overlying the first K dielectric material of the first etch stop layer and the exposed portion

分; Minute;

化学机械平坦化所述第二K值介电材料和所述第一K值介电材料,使所述第一K值介电材料暴露。 The second chemical mechanical planarization K dielectric material and the first K dielectric material, the first K dielectric material is exposed.

[0015] 上述的制作方法,其中,所述第一K值介电材料为USG,FSG, BD, BDl或BDII中一种,所述第二K值介电材料为USG,FSG, BD, BDl或BDII中比所述第一K值介电材料K值低的一种。 [0015] The above-described manufacturing method, wherein said first dielectric material is K USG, FSG, BD, BDl or BDII of one, the second dielectric material is K USG, FSG, BD, BDl or the first low-K dielectric value K value than the material which BDII.

[0016] 上述的制作方法,其中,所述第一介电层薄膜和所述第二介电层薄膜厚度相同,所述第一低K值介电层薄膜和第二低K值介电层薄膜的厚度相同。 [0016] The above-described manufacturing method, wherein the first dielectric layer and said second dielectric film layer is the same as the film thickness of the first low K dielectric layer of the film and a second low K dielectric layer same thickness of the film.

[0017] 上述的制作方法,其中,所述第一介电层薄膜和所述第二介电层薄膜厚度取值范围均为100(Γ10000Α,所述第一低K值介电层薄膜和第二低K值介电层薄膜厚度取值范围均为1000〜10000Α。 [0017] The above-described manufacturing method, wherein the first dielectric layer and said second dielectric film layer of the film thickness ranges are 100 (Γ10000Α, the value of the first low-K dielectric layer and the second film two low K dielectric layer of the film thickness in the range both 1000~10000Α.

[0018] 本发明通过有选择性对金属介电层进行光刻蚀刻来实现在同一层金属介电层中存在两种k值薄膜,将非MOM区域用低k介质填充,使得MOM区域采用高K介质,实现了高性能的金属-氧化物-金属电容,节省了芯片面积,降低了成本。 [0018] The present invention is selective for the metal dielectric layer to achieve a photolithographic etching k value of the film in both the presence of a metal with a dielectric layer, a non-MOM region filled with a low-k dielectric, high area so MOM K dielectric to achieve high performance metal - oxide - metal capacitors, saves chip area and reduce costs.

附图说明 BRIEF DESCRIPTION

[0019] 通过阅读参照以下附图对非限制性实施例所作的详细描述,本发明及其特征、外形和优点将会变得更明显。 [0019] By reading the following detailed description of non-limiting embodiments of the drawings, the present invention and its features, shape, and advantages will become more apparent. 在全部附图中相同的标记指示相同的部分。 The same numerals indicate like parts throughout the drawings. 并未刻意按照比例绘制附图,重点在于示出本发明的主旨。 The drawings are deliberately not to scale, emphasis being placed upon illustrating the gist of the present invention. 在附图中,为清楚明了,放大了部分部件。 In the drawings, as apparent, enlarged partial section.

[0020] 图1为现有技术的金属-氧化物-金属电容的俯视图; 图2为图1中A-A'线处的截面图; [0020] FIG. 1 is a prior art metal - oxide - a top view of a metal capacitor; FIG. 2 is a sectional view 'line A-A in Figure 1;

图3示出了根据本发明的,一种高性能金属-氧化物-金属电容的结构示意图; 图如至图4d示出了根据本发明的,一种高性能金属-氧化物-金属电容中第一介电层薄膜的制作方法的各个步骤;以及 FIG 3 illustrates a high performance metal according to the invention - oxide - a schematic view of a metal capacitor structure; FIGS as to 4d illustrate the present invention, according to a high performance metal - oxide - metal capacitor the various steps of manufacturing method of a thin film of the first dielectric layer; and

图fe至图5c示出了在第一介电层薄膜上制作第一低K值介电层薄膜各个步骤。 FIGS fe through 5c illustrate making a first low K dielectric film on the first dielectric film each step.

具体实施方式 Detailed ways

[0021] 以下结合附图及具体实施方式对本发明进行进一步详细说明。 [0021] The present invention will be further described in detail in conjunction with accompanying drawings and specific embodiments. 此处所描述的具体实施方式仅用于解释本发明,并不用于限定本发明的保护范围。 Specific embodiments described herein are merely for explaining the present invention and are not intended to limit the present invention.

[0022] 参考图3所示的根据本发明的,一种高性能金属-氧化物-金属电容的结构示意图,为了提高电容的性能,在铜互连区域1和MOM (金属-氧化物-金属)区域2采用不同的介电材料。 [0022] shown in FIG. 3, a high performance according to the present invention the metal - oxide - a schematic view of a metal capacitor structure, in order to improve capacitor performance, in a copper interconnect area and the MOM (metal - oxide - metal ) region 2 different dielectric materials. 具体地,本发明的电容包括: In particular, the capacitor of the present invention comprises:

形成在第一刻蚀阻挡层101上的第一介电层薄膜201,所述第一介电层薄膜201包括第一高K值区域211和第一低K值区域221,所述第一介电层薄膜201上覆盖有第一低K值介电层薄膜203,优选地,第一低K值介电层薄膜203与第一低K值区域221的材料相同; 形成在第二刻蚀阻挡层102上的第二介电层薄膜202,所述第二介电层薄膜包括第二高K值区域212和第二低K值区域222,所述第二介电层薄膜202上覆盖有第二低K值介电层薄膜204,优选地,第二低K值介电层薄膜204与第二低K值区域222的材料相同; A first thin dielectric layer 201 formed on the first etch stop layer 101, the first dielectric film layer 201 comprises a first region 211 and a high K-value a first low K region 221, the first dielectric covering the upper thin film layer 201 has a first low K dielectric film 203, preferably of the same material, the first low K dielectric layer 203 and the first film region 221 of the low-K; forming a second etching stopper in the second dielectric layer 202 on the thin film layer 102, the second dielectric layer comprises a second high K film region 212 and the second low K value region 222, on the cover film 202 on the second dielectric layer two low K dielectric film layer 204, preferably the same material as the second low K dielectric film layer 204 and the second region 222 of the low-K;

所述第二刻蚀阻挡层102覆盖所述第一低K值介电层薄膜203,所述第二高K值区域212位于所述第一高K值区域211的竖直上方,所述第二低K值区域222位于所述第一低K 值区域221的竖直上方; The second etch barrier layer 102 covers the first low K dielectric film 203, the second high K-value of the first region 212 is located vertically above the region of high K value of 211, the second two low K region 222 is located vertically above the first region 221 of the low-K;

位于第一高K值区域211和第一低K值区域221上方的所述第一低K值介电层薄膜203中分别设置有金属填充的若干下沟槽301,所述第二介电层薄膜202的第二高K值区域212和第二低K值区域222中分别设置有金属填充的若干上沟槽302,每一个上沟槽302在竖直方向上至少对应一个下沟槽301 ; Located above the first region 211 and high K values ​​of a first region 221 of the low-K first low K dielectric film 203 are respectively provided with a plurality of lower metal filled trench 301, the second dielectric layer a second region of high K film 202 on the trench 212 and a second plurality of low-K regions 222 are provided with a metal filling 302 of each of the grooves 302 in the vertical direction corresponding to the at least one groove 301;

竖直贯穿第二介电层薄膜202和第二刻蚀阻挡层102的接触孔303,每一个接触孔303 分别于一个第二低K值区域222上方的上沟槽302在竖直方向上重合(参考图3),并接触位于所述接触孔303竖直下方的下沟槽301。 A vertical hole through the contact dielectric layer, a second film 202 and the second etch stop layer 102, 303, 303, respectively, each of the contact hole in a region above the second low K value 222 of trench 302 overlap in the vertical direction (refer to FIG. 3), and a contact 303 positioned vertically below the contact hole 301 in the trenches.

[0023] 具体地,本发明的高性能金属-氧化物-金属电容中,所述第一高K值区域211的材料为USG,FSG,BD,BD1或BDII中一种,所述第一低K值介电层薄膜203以及所述第一低K值区域221的材料为USG,FSG, BD, BDl或BDII中比所述第一高K值区域211K值低的一种。 [0023] Specifically, the present invention is the high performance metal - oxide - metal capacitor material, the first region 211 of the high K as USG, FSG, BD, BD1 BDII or in one of the first low K value dielectric material film 203 and the first layer of low-K region 221 of USG, FSG, BD, BDl BDII or lower than the first high K value of one kind of 211K region.

[0024] 更为具体地,所述第一高K值区域211和第二高K值区域212的材料相同,所述第一低K值区域221和第二低K值区域222的材料相同,所述第一低K值介电层薄膜203和第二低K值介电层薄膜204的材料相同,优选地,所述第一低K值介电层薄膜203、第二低K 值介电层薄膜204、第一低K值区域221以及第二低K值区域222的材料都采用同一种。 [0024] More specifically, the first region 211 and a high K material, a second region 212 of the high K identical, the first low-K material region 221 and the second region 222 of the low-K, the first low K dielectric film 203 and a second low K dielectric layer of the same film material 204, preferably, the first low K dielectric film 203, the second low K dielectric a thin film layer 204, a first low K material and a second region 221 region 222 of the low K value are used same.

[0025] 在一个具体实施例中,所述第一介电层薄膜201和所述第二介电层薄膜202厚度相同,所述第一低K值介电层薄膜203和第二低K值介电层薄膜的厚度相同204。 [0025] In one particular embodiment, the first dielectric film layer 201 and the second dielectric layer is the same as the thickness of film 202, the first low K dielectric film 203 and a second low K 204 the same thickness of the dielectric film layer.

[0026] 优选地,所述第一介电层薄膜201和所述第二介电层薄膜202厚度取值范围均为IOOO^IOOOOA,所述第一低K值介电层薄膜203和第二低K值介电层薄膜204厚度取值范围均为1000〜10000A。 [0026] Preferably, the first dielectric film layer 201 and the second dielectric film layer 202 a thickness in the range both IOOO ^ IOOOOA, the value of the first low-K film 203 and a second dielectric layer low K dielectric film layer 204 a thickness in the range both 1000~10000A.

[0027] 本发明有选择性对金属介电层进行光刻蚀刻来实现在同一层金属介电层中存在两种k值薄膜,将非MOM区域用低k介质填充。 [0027] The present invention is selective for the metal dielectric layer to achieve a photolithographic etching k value of the film in both the presence of a metal with a dielectric layer, a non-MOM area filled with low-k dielectrics. 以下对本发明的实现做详细说明,其中,对于刻蚀、化学机械平坦化等现有技术工艺不做详细叙述,如何采用光刻胶进行刻蚀的工艺不是本发明的重点,而且本领域技术人员可以结合现有技术实现所述工艺步骤。 The following detailed description of the implementation of the invention, wherein, for etching, chemical mechanical planarization process and other prior art is not described in detail, how to apply photoresist etching process is not the focus of the present invention, and that those skilled in the art It may be combined to achieve the process steps of the prior art. 参考图3, 并结合图如至图4d以及图fe至图5c,本发明方法的实现步骤为: Referring to FIG 3, in conjunction with FIGS. 4d as well as to FIGS fe to 5C, the steps of the method to achieve the present invention are:

首先,提供一淀积有第一刻蚀阻挡层101的晶圆; First, a first etch stop layer is deposited wafer 101;

然后在所述第一刻蚀阻挡层101上淀积第一介电层薄膜201,所述第一介电层薄膜包括第一高K值区域211和第一低K值区域221 ; Then the first etch stop layer 101 is deposited a first thin dielectric layer 201, the first dielectric layer comprises a first film region 211 and the high K value area 221 of the first low-K;

淀积第一低K值介电层薄膜203覆盖所述第一介电层薄膜201 ; 接着在位于第一高K值区域211和第一低K值区域221上方的第一低K值介电层薄膜203中分别刻蚀若干下沟槽301并填充金属; Depositing a first layer of low K dielectric film 203 covering the first dielectric film layer 201; then a first low K dielectric located above a first region 211 and the high K first region 221 of the low K layer film 203 are etched in the lower groove 301 and a plurality of filler metal;

再化学机械平坦化所述第一低K值介电层薄膜203 ; Then the first chemical mechanical planarization low K dielectric film 203;

然后淀积第二刻蚀阻挡层102覆盖所述第一低K值介电层薄膜203 ; And then depositing a second etch stop layer 102 covers the first low K dielectric film 203;

再在所述第二刻蚀阻挡层102上淀积第二介电层薄膜202,所述第二介电层薄膜202包括第二高K值区域212和第二低K值区域222,所述第二高K值区域212位于所述第一高K 值区域211的竖直上方,所述第二低K值区域222位于所述第一低K值区域221的竖直上方; And then deposited on the second etch stop layer 102 a second dielectric film 202, the second dielectric layer 202 comprises a second high-K film region 212 and the second low value K value region 222, the a second high K region 212 is located vertically above the first high K region 211, the second low K value region 222 is located vertically above the first region 221 of the low-K;

淀积第二低K值介电层薄膜204覆盖所述第二介电层薄膜202 ; 接着在位于第二高K值区域212和第二低K值区域222上方的所述第二低K值介电层薄膜204中分别刻蚀若干上沟槽301,每一个上沟槽302在竖直方向上至少对应一个下沟槽301 ; Depositing a second low K dielectric film layer 204 covers the second dielectric layer film 202; then located above said second high K region 212 and the second region 222 of the second low-K low K the dielectric film layer 204 are etched on the plurality of trenches 301, 302 corresponding to each of the at least one groove on the lower groove 301 in a vertical direction;

在所述第二介电层薄膜202的第二低K值区域222中刻蚀接触孔303,所述接触孔303 与一个第二低K值区域222上方的上沟槽302在竖直方向上重合,并接触位于其竖直下方的下沟槽301 ; In the second area of ​​the second low K dielectric layer 222 is etched film 202 a contact hole 303, the contact hole 303 and a second trench region above the low K 222 302 in the vertical direction overlap, and contacts the lower groove 301 is positioned below its vertical;

在所述上沟槽302和所述接触孔303中填充金属; Grooves 302 and the contact hole 303 is filled in the upper metal;

最后,化学机械平坦化所述第二低K值介电层薄膜204,就得到了如图3所示的结构。 Finally, chemical mechanical planarization of the second layer of low K dielectric film 204, a structure is obtained as shown in FIG.

[0028] 再结合参考图如至图4f示出了根据本发明的,一种高性能金属-氧化物-金属电容制作方法的各个步骤,图如至图4f示出了本发明的高性能金属-氧化物-金属电容中的单层介电层薄膜的制作方法,另一层介电层薄的制作可以参考图如至图4f实现。 [0028] Referring to FIG recombination as to 4f illustrate the present invention, a high-performance metal - oxide - metal capacitor respective steps of manufacturing method, and FIG. 4f as to illustrate the present invention, high performance metal - oxide - monolayer manufacturing method of thin film dielectric layer of a metal capacitor, another dielectric layer is thin can be made with reference to FIGS. 4f as implemented.

[0029] 所述第一介电层薄膜201的的淀积包括如下步骤: [0029] The thin film depositing a first dielectric layer 201 comprising the steps of:

首先,如图如所示,淀积第一K值介电材料401覆盖所述第一刻蚀阻挡层101 ; 再刻蚀去除部分所述第一K值介电材料401,刻蚀止于所述第一刻蚀阻挡层101,位于第一K值介电材料401去除部分下方的第一刻蚀阻挡层101暴露; First, as shown, is deposited a first K dielectric material 401 covering the first etch stop layer 101 such as; K then etching the portion of the first dielectric material 401 is removed, etching Halt said first etch stop layer 101, located between the first K dielectric material 401 below the removed portions of the first etch barrier layer 101 is exposed;

淀积第二K值介电材料402覆盖所述第一K值介电材料401和所述第一刻蚀阻挡层101暴露的部分; K depositing a second dielectric material 402 covering the first K dielectric material 401 and the first etch stop layer 101 in the exposed portion;

最后化学机械平坦化所述第二K值介电材料402和所述第一K值介电材料401,使所述第一K值介电材料暴露; Finally, the second chemical mechanical planarization K dielectric material 402 and the first K dielectric material 401, the first K dielectric material is exposed;

在所述第二K值介电材料402和所述第一K值介电材料401上分别刻蚀形成若干下沟槽301并填充金属; K in the second dielectric material 402 and the first K dielectric material 401 are etched to form the plurality of trenches 301 and a filler metal;

机械平坦化所述第二K值介电材料402和所述第一K值介电材料401。 Mechanically planarizing the second dielectric material 402 K and the first K dielectric material 401.

[0030] 这样,就得到了具有不同K值介质区域的第一介电层薄膜201,在一个优选例中, 第一K值介电材料401采用K值比第二K值介电材料402的K值小的材料,这样,铜互连区域1用第一K值介电材料401作为介电质,再在MOM区域2用第二K值介电材料402作为介电质。 [0030] Thus, the obtained thin film first dielectric layer 201 having a different value of K dielectric region is, in a preferred embodiment, a first dielectric material 401 K using K K value than the second dielectric material 402 small K value of the material, so that a copper interconnect area with a first value K dielectric material as the dielectric 401, and then in a second region 2 MOM K dielectric material 402 as the dielectric.

[0031] 在一个变化例中,第一K值介电材料401采用K值比第二K值介电材料402的K 值大的材料,参考图3,第一K值介电材料401就形成了第一高K值区域211,第二K值介电材料402就形成了第一低K值区域221。 [0031] In a variant embodiment, a first dielectric material 401 K using the K value is greater than a second value of K K dielectric material 402 is a material with reference to FIG. 3, the first K dielectric material 401 is formed high K first region 211, a second K dielectric material 402 is formed a first region 221 of low K value.

[0032] 进一步地,所述第二介电层薄膜202的的淀积包括如下步骤: 淀积第一K值介电材料401覆盖所述第二刻蚀阻挡层102 ; [0032] Further, the second dielectric layer 202 is deposited film comprising the steps of: depositing a first K dielectric material 401 covers the second etch stop layer 102;

刻蚀去除部分所述第一K值介电材料401,刻蚀止于所述第二刻蚀阻挡层102,位于第一K值介电材料401去除部分下方的第一刻蚀阻挡层102暴露; The first portion is removed by etching K dielectric material 401, second etch stop at the etch stop layer 102, located between the first K dielectric material of the first etch stop layer 401 is removed below the exposed portion 102 ;

淀积第二K值介电材料402覆盖所述第一K值介电材料401和所述第一刻蚀阻挡层102暴露的部分;化学机械平坦化所述第二K值介电材料402和所述第一K值介电材料401,使所述第一K值介电材料401暴露; K depositing a second dielectric material 402 covering the first K dielectric material 401 and the first etch stop layer 102 is exposed portion; chemical mechanical planarization of said second dielectric material 402 K and the first K dielectric material 401, the first K dielectric material 401 is exposed;

在所述第二K值介电材料402和所述第一K值介电材料401上分别刻蚀形成若干上沟槽302 ; They are etched to form a plurality of grooves 302 on the K value on the second dielectric material 402 and the first K dielectric material 401;

在所述第二K值介电材料402和所述第一K值介电材料401两者之间K值较低的材料中刻蚀接触孔303,所述接触孔303与一上沟槽302在竖直方向上重叠,所述接触孔303底端接触一位于其竖直下方的下沟槽301 ; K therebetween said second dielectric material 402 and the first dielectric material 401 K lower K value of the material in the contact hole 303 is etched, the contact hole 303 and a trench 302 overlap in the vertical direction, the contact hole 303 contacts a bottom end of the groove 301 thereon vertically downward;

在所述上沟槽302和所述接触孔303中填充金属; Grooves 302 and the contact hole 303 is filled in the upper metal;

机械平坦化所述第二K值介电材料402和所述第一K值介电材料401。 Mechanically planarizing the second dielectric material 402 K and the first K dielectric material 401.

[0033] 参考图fe至图5c,以下详细说明第一介电层薄膜201上的第一低K值介电层薄膜203的加工过程,如图fe,先在由第二K值介电材料402和第一K值介电材料401组成的第一介电层薄膜201上淀积第一低K值介电层薄膜203,然后在第一低K值介电层薄膜203 上刻蚀若干下沟槽301,刻蚀止于第一介电层薄膜201上,其中,部分下沟槽301位于第二K 值介电材料402的竖直上方,部分下沟槽301位于第一K值介电材料401的竖直上方。 [0033] Referring to FIGS fe FIG. 5C, the following detailed description of a first low K dielectric layer on the first thin dielectric layer 201 of the film processing 203, as shown in FIG fe, first by the second dielectric material K depositing a first 402 and a plurality of the low K dielectric film 203 on the first dielectric layer 201 of the first layer of the film K dielectric material 401 composed of, and then etching is performed on a first layer of low-K dielectric film 203 trench 301 is etched beyond the film on the first dielectric layer 201, wherein the lower portion of the trench 301 in the second K dielectric material 402 is vertically above the lower portion of the trench 301 is in the first dielectric value K 401 vertically above the material. 然后执行金属填充的工艺步骤,一般填充铜以完成铜互连结构。 Metal filling process and then perform steps generally filled with copper to complete the copper interconnect structure. 类似的,本领域技术人员结合现有技术可以实现第二介电层薄膜202上的第二低K值介电层薄膜204的加工过程,在此不予赘述。 Similarly, those skilled in the prior art may be implemented in conjunction with a second layer of low K dielectric film on the second dielectric layer 204 of the film 202 process, not described herein.

[0034] 优选地,所述第一K值介电材料401为USG,FSG, BD, BDl或BDII中一种,所述第二1(值介电材料402为旧6,?56,80,801或8011中比所述第一K值介电材料401K值低的一种。 [0034] Preferably, the first K dielectric material 401 USG, FSG, BD, BDl or BDII of one, the second one (dielectric material 402 to the old 6,? 56, 80, 801 or 8011 K value lower than the first dielectric material, a value of 401K.

[0035] 在一个具体实施例中,所述第一介电层薄膜201和所述第二介电层薄膜202厚度相同,所述第一低K值介电层薄膜203和第二低K值介电层薄膜204的厚度相同。 [0035] In one particular embodiment, the first dielectric film layer 201 and the second dielectric layer is the same as the thickness of film 202, the first low K dielectric film 203 and a second low K film of the same thickness as the dielectric layer 204.

[0036] 更进一步地,所述第一介电层薄膜201和所述第二介电层薄膜厚度202取值范围均为100(Γ10000Α,所述第一低K值介电层薄膜203和第二低K值介电层薄膜204厚度取值范围均为100(Tl0000A。 [0036] Still further, the first dielectric film layer 201 and the film thickness of the second dielectric layer are in the range 202 100 (Γ10000Α, the value of the first low-K dielectric film 203 and the second layer two low K dielectric layer of the film 204 thickness ranges are 100 (Tl0000A.

[0037] 本领域技术人员结合现有技术以及上述实施例可以实现所述变化例,这样的变化例并不影响本发明的实质内容,在此不予赘述。 [0037] Those skilled in the art in conjunction with the prior art and the above-described embodiments may implement variations, such variation does not affect the substance of the present invention, not described herein.

[0038] 以上对本发明的较佳实施例进行了描述。 [0038] The foregoing preferred embodiment of the present invention will be described. 需要理解的是,本发明并不局限于上述特定实施方式,其中未尽详细描述的设备和结构应该理解为用本领域中的普通方式予以实施;任何熟悉本领域的技术人员,在不脱离本发明技术方案范围情况下,都可利用上述揭示的方法和技术内容对本发明技术方案作出许多可能的变动和修饰,或修改为等同变化的等效实施例,这并不影响本发明的实质内容。 Is to be understood that the present invention is not limited to the specific embodiments, wherein the device structure and deficiencies detailed description should be understood to be implemented by those skilled in the normal way; any skilled in the art, without departing from the present the scope of the aspect of the invention, can use the above-described methods and technical content disclosed technical solution of the present invention made many possible variations and modifications, equivalent variations or modifications of equivalent embodiments, this does not affect the substance of the present invention. 因此,凡是未脱离本发明技术方案的内容,依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化及修饰,均仍属于本发明技术方案保护的范围内。 Thus, all without departing from the technical solutions of the present invention, any simple modification based on the technical essence of the present invention made of the above Example, equivalents, modifications and variations, provided they fall within the scope of protection of the present invention.

Claims (11)

1. 一种高性能金属-氧化物-金属电容,其特征在于,包括:形成在第一刻蚀阻挡层上的第一介电层薄膜,所述第一介电层薄膜包括第一高K值区域和第一低K值区域,所述第一介电层薄膜上覆盖有第一低K值介电层薄膜;形成在第二刻蚀阻挡层上的第二介电层薄膜,所述第二介电层薄膜包括第二高K值区域和第二低K值区域,所述第二介电层薄膜上覆盖有第二低K值介电层薄膜;所述第二刻蚀阻挡层覆盖所述第一低K值介电层薄膜,所述第二高K值区域位于所述第一高K值区域的竖直上方,所述第二低K值区域位于所述第一低K值区域的竖直上方;位于所述第一高K值区域和第一低K值区域上方的所述第一低K值介电层薄膜中分别设置有金属填充的若干下沟槽,位于第二高K值区域和第二低K值区域上方的所述第二低K 值介电层薄膜中分别设置有金属填充的若干上沟槽, A high-performance metal - oxide - metal capacitor, wherein, comprising: forming a first dielectric layer, etch stop film on the first layer, the first dielectric film comprises a first layer of high-K value region and the first region of low K, of the first dielectric layer covers the first thin film having low K dielectric layer of the film; a second dielectric layer formed on the film of the second etch stop layer, the a second dielectric layer comprises a second high K thin film region and the second low K region covered with the second low K dielectric layer on said second thin film dielectric layer; the second etch stop layer covering the first layer of low K dielectric film, said second high K region located vertically above the first high K region, the second region of the low-K value of the first low-K value of an area vertically above; the value in the first region and the high-K above the first region of the first low-K dielectric layer is a low K value are provided with a plurality of thin film metal filling the trench located on the two high K region and the second region above a second low-K dielectric layer is a low K value are respectively provided with a plurality of thin film metal-filled trench, 一个上沟槽在竖直方向上至少对应一个下沟槽;竖直贯穿第二低K值介电层薄膜、第二介电层薄膜和第二刻蚀阻挡层的接触孔,每一个接触孔分别与一个第二低K值区域上方的上沟槽在竖直方向上重合,并接触位于所述接触孔竖直下方的下沟槽。 A trench in a vertical direction corresponding to the at least one trench; vertically extending through the second low K dielectric layer of the film, the contact hole a second dielectric layer and the second etch stop layer films, each contact hole respectively upper trench region above a second low-K overlap in the vertical direction and positioned in contact with the lower vertical trench below the contact hole.
2.根据权利要求1所述的高性能金属-氧化物-金属电容,其特征在于,所述第一高K 值区域的材料为USG,FSG, BD, BDl或BDII中一种,所述第一低K值介电层薄膜以及所述第一低K值区域的材料为USG,FSG, BD, BDl或BDII中比所述第一高K值区域K值低的一种。 The high performance metal according to claim 1 - oxide - metal capacitor, wherein the material of the first region is a high K USG, FSG, BD, BDl or BDII in one of said first material is a low K dielectric film, and the first region is a low K value USG, FSG, BD, BDl BDII or lower than the first high K K value one kind of region.
3.根据权利要求2所述的高性能金属-氧化物-金属电容,其特征在于,所述第一高K 值区域和第二高K值区域的材料相同,所述第一低K值区域和第二低K值区域的材料相同, 所述第一低K值介电层薄膜和第二低K值介电层薄膜的材料相同。 The high performance metal according to claim 2 - oxide - metal capacitor, wherein the same material of the first region and the second high K high K region, the first region of low K low K material and a second region of the same, the same material of the first low K dielectric layer of the film and a second layer of low K dielectric films.
4.根据权利要求1或2所述的高性能金属-氧化物-金属电容,其特征在于,所述第一介电层薄膜和所述第二介电层薄膜厚度相同,所述第一低K值介电层薄膜和第二低K值介电层薄膜的厚度相同。 The high performance metal of claim 1 or claim 2 - oxide - metal capacitor, wherein said thin film first dielectric layer and said second dielectric layer is the same as the film thickness, the first low K value of the dielectric layer and the film thickness of the second low K dielectric layer of the same film.
5.根据权利要求4所述的高性能金属-氧化物-金属电容,其特征在于,所述第一介电层薄膜和所述第二介电层薄膜厚度取值范围均为100(Γ10000Α,所述第一低K值介电层薄膜和第二低K值介电层薄膜厚度取值范围均为100(Γ10000Α。 The high performance metal according to claim 4 - oxide - metal capacitor, wherein said first dielectric layer and said second dielectric film layer of the film thickness ranges are 100 (Γ10000Α, the first low K dielectric layer of the film and a second low K dielectric layer of the film thickness ranges are 100 (Γ10000Α.
6. 一种高性能金属-氧化物-金属电容的制作方法,其特征在于,包括如下步骤: 提供一淀积有第一刻蚀阻挡层的晶圆;在所述第一刻蚀阻挡层上淀积第一介电层薄膜,所述第一介电层薄膜包括第一高K值区域和第一低K值区域;淀积第一低K值介电层薄膜覆盖所述第一介电层薄膜;在位于第一高K值区域和第一低K值区域上方的所述第一低K值介电层薄膜中分别刻蚀若干下沟槽并填充金属;化学机械平坦化所述第一低K值介电层薄膜; 淀积第二刻蚀阻挡层覆盖所述第一低K值介电层薄膜;在所述第二刻蚀阻挡层上淀积第二介电层薄膜,所述第二介电层薄膜包括第二高K值区域和第二低K值区域,所述第二高K值区域位于所述第一高K值区域的竖直上方,所述第二低K值区域位于所述第一低K值区域的竖直上方;淀积第二低K值介电层薄膜覆盖所述第二介电层薄膜;在位 A high-performance metal - oxide - metal capacitor manufacturing method, characterized by comprising the steps of: providing a wafer deposited with a first etch stop layer; on the first etch stop layer depositing a first dielectric thin film layer, the first dielectric layer comprises a first high K thin film region and the first region of low K; depositing covering the first low K dielectric layer of a first dielectric film a thin film layer; located above the first region and the high K value of the first region of the first low-K dielectric layer low K films are etched trenches and the plurality of fill metal; said first chemical mechanical planarization a low K dielectric layer of the film; a second etch stop layer overlying the first deposited low K dielectric layer of the film; a second dielectric layer deposited on said second thin film etch stop layer, the said second dielectric layer comprises a second high K thin film region and the second low K region, the second high K region is located vertically above the first high K region, the second low K value region located vertically above the region of the first low-K; depositing a second layer of low K dielectric film covering the second dielectric layer films; reign 于第二高K值区域和第二低K值区域上方的所述第二低K值介电层薄膜中分别刻蚀若干上沟槽,每一个上沟槽在竖直方向上至少对应一个下沟槽;在所述第二介电层薄膜的第二低K值区域中刻蚀接触孔,所述接触孔与一个第二低K 值区域上方的上沟槽在竖直方向上重合,并接触位于其竖直下方的下沟槽; 在所述上沟槽和所述接触孔中填充金属; 化学机械平坦化所述第二低K值介电层薄膜。 To the second region and the high K above the second region of the second low-K dielectric layer of low K film is etched respectively on a plurality of grooves, each groove corresponding to the at least one of a vertical direction trench; etching the contact hole in the second area of ​​the second low-K dielectric layer thin film, the contact hole on a second trench region above the low-K overlap in the vertical direction, and located in the trench in contact with the bottom of its vertical; filler metal in the trench and the contact hole; second chemical mechanical planarization of the low K dielectric layer of the film.
7.根据权利要求6所述的制作方法,其特征在于,所述第一介电层薄膜的制作的过程包括如下步骤:淀积第一K值介电材料覆盖所述第一刻蚀阻挡层; 刻蚀去除部分所述第一K值介电材料,刻蚀止于所述第一刻蚀阻挡层,位于第一K值介电材料去除部分下方的第一刻蚀阻挡层暴露;淀积第二K值介电材料覆盖所述第一K值介电材料和所述第一刻蚀阻挡层暴露的部分;化学机械平坦化所述第二K值介电材料和所述第一K值介电材料,使所述第一K值介电材料暴露。 7. The manufacturing method according to claim 6, characterized in that the process of making the film of the first dielectric layer comprises the steps of: depositing a first value K dielectric material overlying the first dielectric etch stop layer ; removing the etching portion of the first K dielectric material, etch stop at the first etch stop layer, located between the first K dielectric material of the first etch stop layer is removed beneath the exposed portions; depositing a second value K dielectric material overlying the first K dielectric material of the first etch stop layer and the exposed portion; the second chemical mechanical planarization K dielectric material and the first value K dielectric material, the first K dielectric material is exposed.
8.根据权利要求6所述的制作方法,其特征在于,所述第二介电层薄膜的制作的过程包括如下步骤:淀积第一K值介电材料覆盖所述第二刻蚀阻挡层; 刻蚀去除部分所述第一K值介电材料,刻蚀止于所述第二刻蚀阻挡层,位于第一K值介电材料去除部分下方的第一刻蚀阻挡层暴露;淀积第二K值介电材料覆盖所述第一K值介电材料和所述第一刻蚀阻挡层暴露的部分;化学机械平坦化所述第二K值介电材料和所述第一K值介电材料,使所述第一K值介电材料暴露。 8. The manufacturing method according to claim 6, characterized in that the process of making the film of the second dielectric layer comprises the steps of: depositing a first dielectric value K dielectric material covering said second etch stop layer ; removing the etching portion of the first K dielectric material, etch stop at the second etch stop layer, located between the first K dielectric material of the first etch stop layer is removed beneath the exposed portions; depositing a second value K dielectric material overlying the first K dielectric material of the first etch stop layer and the exposed portion; the second chemical mechanical planarization K dielectric material and the first value K dielectric material, the first K dielectric material is exposed.
9.根据权利要求7或8所述的制作方法,其特征在于,所述第一 K值介电材料为USG, FSG,BD,BDl或BDII中一种,所述第二K值介电材料为USG, FSG,BD,BDl或BDII中比所述第一K值介电材料K值低的一种。 9. The manufacturing method of claim 7 or claim 8, wherein said first dielectric material is K USG, FSG, BD, BDl or BDII of one, the second dielectric material K of USG, FSG, BD, BDl or BDII first low K dielectric value than the K value of a material.
10.根据权利要求6所述的制作方法,其特征在于,所述第一介电层薄膜和所述第二介电层薄膜厚度相同,所述第一低K值介电层薄膜和第二低K值介电层薄膜的厚度相同。 10. The manufacturing method according to claim 6, wherein said first dielectric layer and said second dielectric film layer is the same as the film thickness of the first low K dielectric layer and a second film the same thickness as low K dielectric films.
11.根据权利要求10所述的制作方法,其特征在于,所述第一介电层薄膜和所述第二介电层薄膜厚度取值范围均为100(Γ10000Α,所述第一低K值介电层薄膜和第二低K值介电层薄膜厚度取值范围均为100(Γ10000Α。 11. The manufacturing method according to claim 10, wherein said first dielectric layer and said second dielectric film layer of the film thickness ranges are 100 (Γ10000Α, the first low K The dielectric layer of the film and the film thickness in the range of the second low K dielectric layers are 100 (Γ10000Α.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102446893A (en) * 2011-10-12 2012-05-09 上海华力微电子有限公司 High-performance metal-oxide-metal capacitor and manufacturing method thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6617206B1 (en) * 2000-06-07 2003-09-09 Micron Technology, Inc. Method of forming a capacitor structure
US20060207965A1 (en) * 2002-07-05 2006-09-21 Chartered Semiconductor Manufacturing Ltd. Method to form both high and low-k materials over the same dielectric region, and their application in mixed mode circuits

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6617206B1 (en) * 2000-06-07 2003-09-09 Micron Technology, Inc. Method of forming a capacitor structure
US20060207965A1 (en) * 2002-07-05 2006-09-21 Chartered Semiconductor Manufacturing Ltd. Method to form both high and low-k materials over the same dielectric region, and their application in mixed mode circuits

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102446893A (en) * 2011-10-12 2012-05-09 上海华力微电子有限公司 High-performance metal-oxide-metal capacitor and manufacturing method thereof

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