CN102420110B - Method for improving metal-insulation-metal (MIM) capacitance density in semiconductor device and device - Google Patents
Method for improving metal-insulation-metal (MIM) capacitance density in semiconductor device and device Download PDFInfo
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- CN102420110B CN102420110B CN 201110194148 CN201110194148A CN102420110B CN 102420110 B CN102420110 B CN 102420110B CN 201110194148 CN201110194148 CN 201110194148 CN 201110194148 A CN201110194148 A CN 201110194148A CN 102420110 B CN102420110 B CN 102420110B
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Abstract
The invention discloses a method for improving metal-insulation-metal (MIM) capacitance density in a semiconductor device and a semiconductor device containing high-density MIM capacitance. The method comprises the following steps that: an appearance layer is arranged on a stop layer of a substrate, the appearance layer is etched, so the appearance layer is provided with a plurality of grooves, and a capacitance substrate covering the appearance layer is in a appearance shape to increase the area of the capacitance substrate and to further increase the capacitance density. Due to the adoption of the method, compared with the prior art, the area of a wafer is not increased, and a strong compatibility can be realized compared with the traditional technique.
Description
Technical field
The present invention relates to capacitance structure that integrated circuit comprises and manufacturing field thereof, in particular to a kind of method and device thereof that improves MIM capacitance density in semiconductor device.
Background technology
The continuous innovation of semiconductor integrated circuit manufacturing process technology makes integrated level more and more higher, when realizing device as much as possible in as far as possible little zone, also requires to obtain high as far as possible performance.
Wherein, capacitor is the important composition unit in integrated circuit, is widely used in memory, microwave, and radio frequency, smart card is in the chips such as high pressure and filtering.Along with the minimizing of chip size, and to the high demand that large capacitive character the subject of knowledge and the object of knowledge proposes, how obtaining highdensity electric capacity under limited area becomes a problem that haves a great attraction.
Traditional capacitance structure is, structure single-layer capacitor as shown in Figure 1, the capacity plate antenna model of metal-insulator-metal.Wherein, Fig. 1 mainly shows the first metal layer 201, insulating barrier 301 and the second metal level 202 and forms an electric capacity, and for example a kind of at present typical capacitor arrangement is the sandwich structure by copper metal layer-silicon nitride dielectric layer-Tan metal level.The selection of metal level has multiple material optional, as copper, and aluminium, tantalum, titanium and alloy thereof etc.And insulating barrier also has the material of multiple differing dielectric constant optional.
In order to obtain higher unit area capacitance density, the method that present prior art adopts usually has following three kinds: adopting more, the dielectric material of high-k improves capacitance density; Or minimizing medium thickness; Or the increase area improves electric capacity.
But, because at present available dielectric material is limited, wherein can be combined with still less with existing technique on the one hand, the room for promotion of therefore using high dielectric constant material instead is limited; Again because along with thickness of dielectric layers reduces, corresponding puncture voltage also can reduce, so this method is of limited application on the other hand; And the pattern that the third scheme is the utilization fluctuating increases the capacity substrate area on unit are, but this technique can reduce mismatch parameter, thereby reduces the electric property of mim structure.
Therefore, adopt the scheme of prior art can not well obtain higher unit area capacitance density.Providing a kind of and can effectively improve the MIM(metal-insulator-metal) new construction of capacitance density just seems particularly important.
Summary of the invention
The objective of the invention is to solve the defective that can not realize well in prior art that capacitance density improves, avoid as improving the increase manufacturing cost of electric capacity.
According to an aspect of the present invention, the present invention discloses MIM(metal-insulator-metal in a kind of raising semiconductor device) method of capacitance density, wherein, comprise the following steps:
Be provided with metal interconnecting wires and be connected to the metal joint of metal interconnecting wires in a dielectric base, deposit one deck the first barrier layer in this substrate, the first barrier layer covers on metal interconnecting wires and metal joint simultaneously;
Deposit one deck pattern layer covers on described the first barrier layer;
Described pattern layer is carried out etching, and form a plurality of grooves in the pattern layer, pattern layer and metal joint are not had in vertical direction overlapping;
The deposit the first metal layer covers described pattern layer, and the zone that is exposed due to the etch topography layer on the first barrier layer is also covered by the first metal layer, and the first metal layer also covers on the bottom and sidewall of groove simultaneously;
Deposit the first insulating barrier covers on described the first metal layer;
Deposit the second metal level covers on described the first insulating barrier;
Near the second metal level the second metal level and the first insulating barrier and metal joint overlapping part in vertical direction and the first insulating barrier zone are carried out etching, make the second metal level and the first insulating barrier and metal joint not have in vertical direction overlapping;
Continue afterwards etching is carried out near the first metal layer zone the first metal layer and metal joint overlapping part in vertical direction, the first metal layer and metal joint are not had in vertical direction overlapping, and the extended structure that is not covered by the second metal level and the first insulating barrier that forms that the first metal layer comprises;
Deposit the second insulating barrier covers described the second metal level, the extended structure that the first metal layer comprises is also covered by the second insulating barrier, the zone that is exposed due to etching first metal layer on the first barrier layer is also covered by the second insulating barrier, and the second insulating barrier also is filled in sidewall and the bottom is coated with in the described groove of the first metal layer, the first insulating barrier, the second metal level successively;
Etching the second insulating barrier, formation runs through the second insulating barrier and contacts respectively the through hole of the second metal level, extended structure, the step that also comprises simultaneously etching the second insulating barrier and the first barrier layer forms the through hole that runs through the second insulating barrier and the first barrier layer and contacting metal joint;
Fill metal material in through hole.
Above-mentioned method wherein, forms the method for the through hole that contacts respectively the second metal level, extended structure, metal joint, comprises the following steps:
Etching the second insulating barrier, formation is positioned at a plurality of first kind grooves at the second insulating barrier top, and in the bottom of first kind groove, the second insulating barrier is carried out etching, to form the through hole of contact the second metal level in the second insulating barrier of at least one first kind beneath trenches, to form the through hole of contact extended structure in the second insulating barrier of at least one first kind beneath trenches;
Etching is carried out to the second insulating barrier and the first barrier layer in bottom at least one first kind groove, to form the through hole of contacting metal joint in the second insulating barrier of at least one first kind beneath trenches and the first barrier layer;
And fill in through hole in the process of metal material, also be filled with metal material in first kind groove, further carry out cmp to covering metal material unnecessary on the second insulating barrier afterwards.
Above-mentioned method, wherein, after forming the step of the through hole that contacts respectively the second metal level, extended structure, metal joint, further comprising the steps of:
Carry out etching at the top of the second insulating barrier and form a plurality of first kind grooves be positioned at the second insulating barrier top, and at least one first kind groove and the through hole that contacts the second metal level overlapping and connection in vertical direction, at least one first kind groove and the through hole that contacts extended structure are overlapping and be communicated with in vertical direction, and the through hole of at least one first kind groove and contacting metal joint is overlapping and be communicated with in vertical direction;
And fill in through hole in the process of metal material, also be filled with metal material in first kind groove, further carry out cmp to covering metal material unnecessary on the second insulating barrier afterwards.
Above-mentioned method, wherein, described pattern layer is metal material layer.
Above-mentioned method, wherein, described pattern layer is dielectric materials layer.
Above-mentioned method, wherein, the Thickness scope of described pattern layer is 300 dust to 4000 dusts.
Above-mentioned method, wherein, the material of described the first insulating barrier is silicon dioxide, silicon nitride, a kind of in the smooth or alundum (Al2O3) of three oxidations two.
Above-mentioned method, wherein, the Thickness scope of described the first insulating barrier is 150 dust to 700 dusts.
Above-mentioned method, wherein, the material of described the second insulating barrier is the silex glass of unadulterated Si oxide or doped with fluorine.
Above-mentioned method, wherein, described pattern layer and described first, second metal level adopt physical vaporous deposition to make.
Above-mentioned method, wherein, described the first insulating barrier and described the second insulating barrier adopt chemical vapour deposition technique to make.
According to another aspect of the present invention, a kind of high density MIM(metal-insulator-metal that comprises is also disclosed) semiconductor device of electric capacity, wherein, comprising:
The metal interconnecting wires that arranges in a dielectric base and be connected to the metal joint of metal interconnecting wires, and be deposited on this suprabasil one deck the first barrier layer, the first barrier layer covers on metal interconnecting wires and metal joint simultaneously;
Be formed on the pattern layer on the first barrier layer, form a plurality of grooves in the pattern layer;
Cover the first metal layer on the pattern layer, the subregion of the close pattern layer on the first barrier layer is also covered by the first metal layer, and the first metal layer also covers on the bottom and sidewall of described groove simultaneously;
Cover successively the first insulating barrier and the second metal level on the first metal layer, and the extended structure that the first metal layer comprises is not covered by the second metal level and the first insulating barrier;
Wherein, pattern layer, first, second metal level and the first insulating barrier and metal joint do not have overlapping in vertical direction;
Cover the second insulating barrier on described the second metal level, the extended structure that the first metal layer comprises is also covered by the second insulating barrier, simultaneously the first barrier layer is not covered by the second insulating barrier by the zone that the first metal layer and pattern layer are covered yet, and the second insulating barrier also is filled in sidewall and the bottom is coated with in the described groove of the first metal layer, the first insulating barrier, the second metal level successively;
Be formed on a plurality of first kind grooves at the second insulating barrier top, and at least one first kind groove and the through hole that contacts the second metal level overlapping and connection in vertical direction, at least one first kind groove and the through hole that contacts extended structure are overlapping and be communicated with in vertical direction, and the through hole of at least one first kind groove and contacting metal joint is overlapping and be communicated with in vertical direction;
And be filled in metal material in first kind groove and through hole.
The above-mentioned high density MIM(metal-insulator-metal that comprises) semiconductor device of electric capacity, wherein, described pattern layer is metal material layer.
The above-mentioned high density MIM(metal-insulator-metal that comprises) semiconductor device of electric capacity, wherein, described pattern layer is dielectric materials layer.
The above-mentioned high density MIM(metal-insulator-metal that comprises) semiconductor device of electric capacity, wherein, the Thickness scope of described pattern layer is 300 dust to 4000 dusts.
The above-mentioned high density MIM(metal-insulator-metal that comprises) semiconductor device of electric capacity, wherein, the material of described the first insulating barrier is silicon dioxide, silicon nitride, a kind of in the smooth or alundum (Al2O3) of three oxidations two.
The above-mentioned high density MIM(metal-insulator-metal that comprises) semiconductor device of electric capacity, wherein, the Thickness scope of described the first insulating barrier is 150 dust to 700 dusts.
The above-mentioned high density MIM(metal-insulator-metal that comprises) semiconductor device of electric capacity, wherein, the material of described the second insulating barrier is the silex glass of unadulterated Si oxide or doped with fluorine.
Relative prior art, the capacitance structure of the capacity substrate on plane formation, had the capacity substrate of pattern shape to replace by the present invention originally, increased the capacity substrate area, thereby increased capacitance density.
Utilize capacitance structure of the present invention and method, the capacitance density in can very effective raising unit are can improve capacitance density, of the present inventionly helpfully is:
1. the shared chip area of new construction does not increase;
2. with traditional handicraft, very strong compatibility is arranged.
Description of drawings
By reading the detailed description of non-limiting example being done with reference to the following drawings, it is more obvious that the present invention and feature thereof, profile and advantage will become.Mark identical in whole accompanying drawings is indicated identical part.Deliberately proportionally do not draw accompanying drawing, focus on illustrating purport of the present invention.In the accompanying drawings, for cheer and bright, the part parts have been amplified.
Fig. 1 shows according to prior art, a kind of traditional MIM(metal-insulator-metal) structural representation of electric capacity;
Fig. 2 shows according to of the present invention, the structural representation in a kind of method that improves MIM capacitance density in semiconductor device behind deposit the first barrier layer;
Fig. 3 shows according to of the present invention, the structural representation in a kind of method that improves MIM capacitance density in semiconductor device behind deposit the first barrier layer;
Fig. 4 shows according to of the present invention, the structural representation in a kind of method that improves MIM capacitance density in semiconductor device after the deposit the first metal layer;
Fig. 5 shows according to of the present invention, the structural representation in a kind of method that improves MIM capacitance density in semiconductor device after deposit the first insulating barrier;
Fig. 6 shows according to of the present invention, the structural representation in a kind of method that improves MIM capacitance density in semiconductor device after deposit the second metal level;
Fig. 7 shows according to of the present invention, the structural representation in a kind of method that improves MIM capacitance density in semiconductor device after etching the second metal level, the first insulating barrier and the first metal layer;
Fig. 8 shows according to of the present invention, in a kind of method that improves MIM capacitance density in semiconductor device after deposit the second insulating barrier etching form structural representation after groove and through hole; And
Fig. 9 shows according to of the present invention, fills the structural representation after metal in a kind of method that improves MIM capacitance density in semiconductor device in through hole.
Embodiment
Below in conjunction with the drawings and the specific embodiments, the present invention is further elaborated.Embodiment described herein only is used for explaining the present invention, the protection range that is not intended to limit the present invention.
Structural representation when carrying out referring to figs. 2 to a plurality of steps of the method according to this invention shown in Figure 9 successively.Wherein, structure chart shown in Figure 9 is a kind of high density MIM(metal-insulator-metal that comprises) semiconductor device of electric capacity.
As shown in Figure 2, in one embodiment, MIM(metal-insulator-metal in a kind of raising semiconductor device provided by the present invention) in the method for capacitance density, dielectric base 1 is usually as a certain interlayer dielectric layer (ILD) in semiconductor device, normally be provided with the metal interconnecting wires that does not illustrate in dielectric base 1, in Fig. 2, the shown metal joint that is connected to metal interconnecting wires 2 can be a part of fragment of metal interconnection wire, and it is for the ease of follow-up narration explanation that metal joint 2 is listed separately.Elder generation deposit one deck first barrier layer 3 in this substrate 1, barrier layer 3 is generally etching barrier layer (for example SiN), and the first barrier layer 3 covers on metal interconnecting wires and metal joint 2 simultaneously.In Fig. 2, deposit one deck pattern layer 4 covers on described the first barrier layer 3 again, pattern layer 4 can be both that metal material layer can be also dielectric materials layer, and pattern layer 4 can adopt physical vaporous deposition to make, and the Thickness scope of pattern layer is between 300 dust to 4000 dusts.
Shown in Figure 3, pattern layer 4 is carried out etching, for example apply one deck photoresistance (not shown) to pattern layer 4, photoresistance is carried out photoetching process, form the opening in photoresistance, by opening, pattern layer 4 is carried out etching, the present invention is follow-up also relates to a lot of etch step, those skilled in the art can be in conjunction with existing techniques in realizing, so this specification repeats no more the detailed process of etch step.
In said process, mainly to form a plurality of groove 4A in pattern layer 4, and etching is carried out in pattern layer 4 zone to pattern layer 4 and metal joint 2 overlapping part 4'(in vertical direction as shown in Figure 2), so that pattern layer 4 does not have overlapping with metal joint 2 in vertical direction, in a specific embodiment, described pattern layer 4 for example can adopt: aluminium copper, smooth, nitrogenize is smooth or titanium nitride in any one metal material, those skilled in the art also can adopt other materials to substitute in conjunction with prior art, do not repeat them here.
as required, the width of each groove 4A can be different, but the width that guarantees subsequent process steps further groove 4A is enough, making in each groove 4A can deposited metal, insulating barrier and metallic copper, on the other hand, etch topography layer 4 forms in the process of groove 4A, can be etched to as shown in Figure 3 the first barrier layer 3, the groove 4A's that forms like this is darker, for the step of follow-up deposit other materials provides more space, in one changes example, the degree of depth of groove 4A also can be processed as required, do not contact the first barrier layer 3 when namely pattern layer 4 being carried out etching.
Then with reference to figure 4, in Fig. 4, indicated in a plurality of groove 4A(Fig. 4 and indicated) between the projection of remaining pattern layer after over etching, wherein, the first projection 401, the second projection 402 and the 3rd projection 403 all do not overlap with metal joint 2 in the vertical directions.Deposit the first metal layer 5 covers described pattern layer, wherein, the regional 3A(that is exposed due to etch topography layer 4 on the first barrier layer 3 is with reference to figure 3, do not indicate in Fig. 4), also covered by the first metal layer 5, the first metal layer also covers on the bottom and sidewall of groove simultaneously, as shown in the figure, the first metal layer 5 covers on the rear remaining pattern layer that is etched, and on the top of the first projection 401, the second projection 402 and the 3rd projection 403 and sidewall, one deck the first metal layer 5 is arranged all.
See again Fig. 5, in Fig. 5, amplified the distance of the first projection 401 and the second projection 402, make every one deck structure show more clearly, follow above-mentioned step, deposit this moment the first insulating barrier 6 covers on described the first metal layer 5, this is prior art, does not repeat them here.In a specific embodiment, the material of the first insulating barrier 6 of the present invention is silicon dioxide, and further, the first insulating barrier 6 also can be used silicon nitride, and the smooth or alundum (Al2O3) of three oxidations two replaces.Preferably, the THICKNESS CONTROL of the first insulating barrier 6 makes the thinner thickness of having of the first insulating barrier 6 in the scope of 150 dust to 700 dusts.
Step afterwards as shown in Figure 6, deposit the second metal level 7 covers on described the first insulating barrier 6.Like this, the second metal level 7, the first insulating barrier 6 and the first metal layer 5 have just formed sandwich structure, capacitance structure compared to existing technology, can find with reference to figure 6, in identical chip area, the capacitance density that in the present invention, the second metal level 7, the first insulating barrier 6 and the first metal layer 5 consist of is higher.
Then, again near the second metal level 7 the second metal level 7 and the first insulating barrier 6 and metal joint 2 overlapping part in vertical direction and the zone of the first insulating barrier 6 are carried out etching, make the second metal level 7 and the first insulating barrier 6 not have in vertical direction overlapping with metal joint 2, as shown in Figure 7, in one embodiment, the edge of the second metal level 7 and the first insulating barrier 6 is completed in same etch step.
Continue afterwards etching is carried out near the zone of the first metal layer 5 the first metal layer 5 and metal joint 2 overlapping part in vertical direction, the first metal layer 5 and metal joint 2 are not had in vertical direction overlapping, and the extended structure 501 that is not covered by the second metal level 7 and the first insulating barrier 6 that forms that the first metal layer 5 comprises.
Deposit the second insulating barrier 8 covers described the second metal level 7, the extended structure 501 that the first metal layer 5 comprises is also covered by the second insulating barrier 8, the zone that is exposed due to etching first metal layer 5 on the first barrier layer 3 is also covered by the second insulating barrier 8, and the second insulating barrier 8 also is filled in sidewall and the bottom is coated with in the described groove 4A of the first metal layer 5, the first insulating barrier 6, the second metal level 7 successively.
Again with reference to figure 8, etching the second insulating barrier 8, formation runs through the second insulating barrier 8 and contacts respectively the through hole of the second metal level 7, extended structure 501, the step that also comprises simultaneously etching the second insulating barrier 8 and the first barrier layer 3 forms the through hole that runs through the second insulating barrier 6 and the first barrier layer 3 and contacting metal joint 2.As shown in Figure 8, through hole 801 contacting metal joints 2, through hole 802 contact the first metal layers 5, through hole 803 contact the second metal levels 7.
At last, fill metal material 9 in above-mentioned through hole, complete the step that metal connects, as shown in Figure 9, just obtained the high density MIM(metal-insulator-metal that comprises of the present invention) semiconductor device of electric capacity, wherein, metal material 9 adopts copper usually, in the process of filling, first in through hole successively deposit form copper barrier layer and Seed Layer (not shown), then carry out copper and electroplate, grind to remove unnecessary part metals copper.
Further, with reference to figure 8 and Fig. 9, in a specific embodiment, the method for forming the through hole that contacts respectively the second metal level 7, extended structure 501, metal joint 2 comprises the following steps:
etching the second insulating barrier 8, a plurality of first kind groove 811(that formation is positioned at the second insulating barrier 8 tops as shown in Figure 8), and in the bottom of first kind groove 811, the second insulating barrier 8 is carried out etching, through hole (with reference to the through hole 803 in figure 8) with the second interior formation contact of insulating barrier 8 the second metal level 7 below at least one first kind groove 811, through hole (with reference to the through hole 802 in figure 8) with the second interior formation contact of insulating barrier 8 extended structure 501 below at least one first kind groove 811, etching is carried out to the second insulating barrier 8 and the first barrier layer 3 in bottom at least one first kind groove 811, through hole (with reference to the through hole 801 in figure 8) with the second insulating barrier 8 below at least one first kind groove 811 and the first barrier layer 3 interior formation contacting metal joint 2.
More specifically, fill in through hole in the process of metal material 9, also be filled with metal material 9 in first kind groove 811, further carry out cmp to covering metal material unnecessary on the second insulating barrier 9 afterwards.
Change in example at another, after forming the step of the through hole that contacts respectively the second metal level, extended structure, metal joint, further comprising the steps of:
Carry out etching at the top of the second insulating barrier 8 and form a plurality of first kind grooves 811 be positioned at the second insulating barrier 8 tops, and at least one first kind groove 811 and the through hole that contacts the second metal level 7 overlapping and connection in vertical direction, at least one first kind groove 811 and the through hole that contacts extended structure 501 are overlapping and be communicated with in vertical direction, and the through hole of at least one first kind groove 811 and contacting metal joint 2 is overlapping and be communicated with in vertical direction.
More specifically, fill in through hole in the process of metal material 9, also be filled with metal material 9 in first kind groove 811, further carry out cmp to covering metal material unnecessary on the second insulating barrier 9 afterwards.
In above-described embodiment, the material of the second insulating barrier adopts the silex glass of unadulterated Si oxide or doped with fluorine, makes the second insulating barrier have good insulating properties.
In a specific embodiment, described pattern layer 4 and described the first metal layer 5, the second metal level 7 all adopt physical vaporous deposition to make.
And described the first insulating barrier 6 and described the second insulating barrier 8 adopt chemical vapour deposition technique to make.Grasp for those skilled in the art due to the technology of physical vaporous deposition (PVD) and chemical vapour deposition technique (CVD), do not repeat them here.
With reference to the through hole 803 in figure 8, the bottom of described through hole 803 contacts the second metal level 7 again, and the vertical lower of through hole 803 does not have pattern layer 4, and at this moment, the position of through hole 803 is above a groove 4A; In one changed example, the position of through hole 803 was positioned at pattern layer 4 the be etched top of residue projection, and for example in Fig. 8, through hole 803 can be changed to the top that is positioned at the first projection 401.
In one changes example, with structure shown in Figure 6 as a reference, to described the second metal level 7 and the first insulating barrier 6 carry out etching the time, apply one deck photoresistance, for example on photoresist to the second metal level 7, photoresistance is carried out photoetching process, form the opening in photoresistance, by opening, the second metal level 7 is carried out etching, remove in Fig. 6, the second metal level 7 and the first insulating barrier 6 are in the zone between above the first projection 401 above metal joint 2.This situation is suitable to be specially adapted to when the first projection 401 in the vertical directions and metal joint 2 when close, only remove at second metal level 7 and first insulating barrier 6 of the first projection 401 near metal joint 2 one sides, extended structure 501 just can have enough length to be used for realizing follow-up electrical connection.
As shown in Figure 9, make semiconductor having completed the method according to this invention, just obtained comprising high density MIM(metal-insulator-metal) semiconductor device of electric capacity.Particularly, comprising:
The metal interconnecting wires (not shown in Fig. 9) that arranges in a dielectric base 1 and be connected to the metal joint 2 of metal interconnecting wires, and be deposited on these 3, the first barrier layers, suprabasil one deck the first barrier layer and cover simultaneously on metal interconnecting wires and metal joint 2;
Be formed on the pattern layer 4 on the first barrier layer 3, form a plurality of groove 4A in pattern layer 4;
The subregion that covers the close pattern layer 4 on the first metal layer 5, the first barrier layers 3 on pattern layer 4 is also covered by the first metal layer 5, and the first metal layer 5 also covers on the bottom and sidewall of described groove 4A simultaneously,
Cover successively the first insulating barrier 6 and the second metal level 7 on the first metal layer 5, and the extended structure 501 that the first metal layer 5 comprises is not covered by the second metal level 7 and the first insulating barrier 6;
Wherein, pattern layer 4, the first metal layer 5, the second metal level 7 and the first insulating barrier 6 do not have overlapping with metal joint 2 in vertical direction;
Cover the second insulating barrier 8 on described the second metal level 8, the extended structure 501 that the first metal layer 5 comprises is also covered by the second insulating barrier 8, simultaneously the first barrier layer 3 is not covered by the second insulating barrier 8 by the first metal layer 5 and zone that pattern layer 4 covered yet, and the second insulating barrier 8 also is filled in sidewall and the bottom is coated with in the described groove 4A of the first metal layer 5, the first insulating barrier 6, the second metal level 7 successively;
Be formed on a plurality of first kind grooves 811 at the second insulating barrier top, and at least one first kind groove 811 and the through hole 803 that contacts the second metal level 7 overlapping and connection in vertical direction, at least one first kind groove 811 and the through hole 802 that contacts extended structure 501 are overlapping and be communicated with in vertical direction, and the through hole 801 of at least one first kind groove 811 and contacting metal joint 2 is overlapping and be communicated with in vertical direction;
And be filled in metal material 9 in first kind groove 811 and through hole.
In a specific embodiment, described pattern layer 4 is metal material layer, particularly, the material of pattern layer 4 with aluminium copper, smooth, nitrogenize is smooth or titanium nitride in any one.
In one changes example, pattern layer 4 is dielectric materials layer, different from above-described embodiment is, the pattern layer 4 that adopts metal material and the infrabasal plate that covers the first metal layer 5 on pattern layer 4 and jointly consisted of electric capacity, and when adopting the pattern layer 4 of dielectric material, only have the first metal layer 5 as the infrabasal plate of electric capacity.When using method of the present invention to make semiconductor, can select according to specific needs the material of pattern layer 4.
For the density that makes electric capacity is greatly improved, the Thickness scope of described pattern layer 4 is 300 dust to 4000 dusts.
Further, the material of the first metal layer 5 can select smooth or nitrogenize is smooth, when the material of pattern layer 4 and the first metal layer 5 is identical, pattern layer 5 and the first metal layer 5 are integrated, being equivalent to the first metal layer 5 is exactly that lower surface is smooth, upper surface has a plurality of groove shapes, and its effect is exactly the infrabasal plate thickening of capacitance structure.
In the capacitance structure that the first metal layer 5, the first insulating barrier 6 and the second metal level 7 form, the material of described the first insulating barrier 6 is silicon dioxide, silicon nitride, and a kind of in the smooth or alundum (Al2O3) of three oxidations two is to guarantee the insulation characterisitic of the first insulating barrier 6.
Further, the Thickness scope of the first insulating barrier 6 is 150 dust to 700 dusts.
In one embodiment, the material of the second insulating barrier 8 in the present invention adopts the silex glass of unadulterated Si oxide or doped with fluorine.
Compare the capacitance structure of the capacity substrate formation on plane originally, had the capacity substrate of pattern shape to replace by the present invention, increased the capacity substrate area, thereby increased capacitance density.
It should be appreciated by those skilled in the art that those skilled in the art can realize described variation example in conjunction with prior art and above-described embodiment, such variation example does not affect flesh and blood of the present invention, does not repeat them here.
Above preferred embodiment of the present invention is described.It will be appreciated that, the present invention is not limited to above-mentioned specific implementations, and the equipment of wherein not describing in detail to the greatest extent and structure are construed as with the common mode in this area to be implemented; Any those of ordinary skill in the art, do not breaking away from technical solution of the present invention scope situation, all can utilize method and the technology contents of above-mentioned announcement to make many possible changes and modification to technical solution of the present invention, or being revised as the equivalent embodiment of equivalent variations, this does not affect flesh and blood of the present invention.Therefore, every content that does not break away from technical solution of the present invention, all still belongs in the scope of technical solution of the present invention protection any simple modification made for any of the above embodiments, equivalent variations and modification according to technical spirit of the present invention.
Claims (18)
1. a method that improves metal-insulating layer-metal capacitor density in semiconductor device, is characterized in that, comprises the following steps:
Be provided with metal interconnecting wires and be connected to the metal joint of metal interconnecting wires in a dielectric base, deposit one deck the first barrier layer in this substrate, the first barrier layer covers on metal interconnecting wires and metal joint simultaneously;
Deposit one deck pattern layer covers on described the first barrier layer;
Described pattern layer is carried out etching, and form a plurality of grooves in the pattern layer, pattern layer and metal joint are not had in vertical direction overlapping;
The deposit the first metal layer covers described pattern layer, and the zone that is exposed due to the etch topography layer on the first barrier layer is also covered by the first metal layer, and the first metal layer also covers on the bottom and sidewall of groove simultaneously;
Deposit the first insulating barrier covers on described the first metal layer;
Deposit the second metal level covers on described the first insulating barrier;
Near the second metal level the second metal level and the first insulating barrier and metal joint overlapping part in vertical direction and the first insulating barrier zone are carried out etching, make the second metal level and the first insulating barrier and metal joint not have in vertical direction overlapping;
Continue afterwards etching is carried out near the first metal layer zone the first metal layer and metal joint overlapping part in vertical direction, the first metal layer and metal joint are not had in vertical direction overlapping, and the extended structure that is not covered by the second metal level and the first insulating barrier that forms that the first metal layer comprises;
Deposit the second insulating barrier covers described the second metal level, the extended structure that the first metal layer comprises is also covered by the second insulating barrier, the zone that is exposed due to etching first metal layer on the first barrier layer is also covered by the second insulating barrier, and the second insulating barrier also is filled in sidewall and the bottom is coated with in the described groove of the first metal layer, the first insulating barrier, the second metal level successively;
Etching the second insulating barrier, formation runs through the second insulating barrier and contacts respectively the through hole of the second metal level, extended structure, the step that also comprises simultaneously etching the second insulating barrier and the first barrier layer forms the through hole that runs through the second insulating barrier and the first barrier layer and contacting metal joint;
Fill metal material in through hole.
2. the method for claim 1, is characterized in that, forms the method for the through hole that contacts respectively the second metal level, extended structure, metal joint, comprises the following steps:
Etching the second insulating barrier, formation is positioned at a plurality of first kind grooves at the second insulating barrier top, and in the bottom of first kind groove, the second insulating barrier is carried out etching, to form the through hole of contact the second metal level in the second insulating barrier of at least one first kind beneath trenches, to form the through hole of contact extended structure in the second insulating barrier of at least one first kind beneath trenches;
Etching is carried out to the second insulating barrier and the first barrier layer in bottom at least one first kind groove, to form the through hole of contacting metal joint in the second insulating barrier of at least one first kind beneath trenches and the first barrier layer;
And fill in through hole in the process of metal material, also be filled with metal material in first kind groove, further carry out cmp to covering metal material unnecessary on the second insulating barrier afterwards.
3. the method for claim 1, is characterized in that, and is after forming the step of the through hole that contacts respectively the second metal level, extended structure, metal joint, further comprising the steps of:
Carry out etching at the top of the second insulating barrier and form a plurality of first kind grooves be positioned at the second insulating barrier top, and at least one first kind groove and the through hole that contacts the second metal level overlapping and connection in vertical direction, at least one first kind groove and the through hole that contacts extended structure are overlapping and be communicated with in vertical direction, and the through hole of at least one first kind groove and contacting metal joint is overlapping and be communicated with in vertical direction;
And fill in through hole in the process of metal material, also be filled with metal material in first kind groove, further carry out cmp to covering metal material unnecessary on the second insulating barrier afterwards.
4. the method for claim 1, is characterized in that, described pattern layer is metal material layer.
5. the method for claim 1, is characterized in that, described pattern layer is dielectric materials layer.
6. method as described in claim 4 or 5, is characterized in that, the Thickness scope of described pattern layer is 300 dust to 4000 dusts.
7. the method for claim 1, is characterized in that, the material of described the first insulating barrier is silicon dioxide, silicon nitride, a kind of in the smooth or alundum (Al2O3) of three oxidations two.
8. method as claimed in claim 6, is characterized in that, the Thickness scope of described the first insulating barrier is 150 dust to 700 dusts.
9. the method for claim 1, is characterized in that, the material of described the second insulating barrier is the silex glass of unadulterated Si oxide or doped with fluorine.
10. method as claimed in claim 4, is characterized in that, described pattern layer and described first, second metal level adopt physical vaporous deposition to make.
11. the method for claim 1 is characterized in that, described the first insulating barrier and described the second insulating barrier adopt chemical vapour deposition technique to make.
12. a semiconductor device that comprises high desnity metal-insulating barrier-metal capacitance is characterized in that, comprising:
The metal interconnecting wires that arranges in a dielectric base and be connected to the metal joint of metal interconnecting wires, and be deposited on this suprabasil one deck the first barrier layer, the first barrier layer covers on metal interconnecting wires and metal joint simultaneously;
Be formed on the pattern layer on the first barrier layer, form a plurality of grooves in the pattern layer;
Cover the first metal layer on the pattern layer, the subregion of the close pattern layer on the first barrier layer is also covered by the first metal layer, and the first metal layer also covers on the bottom and sidewall of described groove simultaneously;
Cover successively the first insulating barrier and the second metal level on the first metal layer, and the extended structure that the first metal layer comprises is not covered by the second metal level and the first insulating barrier;
Wherein, pattern layer, first, second metal level and the first insulating barrier and metal joint do not have overlapping in vertical direction;
Cover the second insulating barrier on described the second metal level, the extended structure that the first metal layer comprises is also covered by the second insulating barrier, simultaneously the first barrier layer is not covered by the second insulating barrier by the zone that the first metal layer and pattern layer are covered yet, and the second insulating barrier also is filled in sidewall and the bottom is coated with in the described groove of the first metal layer, the first insulating barrier, the second metal level successively;
Be formed on a plurality of first kind grooves at the second insulating barrier top, and at least one first kind groove and the through hole that contacts the second metal level overlapping and connection in vertical direction, at least one first kind groove and the through hole that contacts extended structure are overlapping and be communicated with in vertical direction, and the through hole of at least one first kind groove and contacting metal joint is overlapping and be communicated with in vertical direction;
And be filled in metal material in first kind groove and through hole.
13. the semiconductor device that comprises high desnity metal-insulating barrier-metal capacitance as claimed in claim 12 is characterized in that, described pattern layer is metal material layer.
14. the semiconductor device that comprises high desnity metal-insulating barrier-metal capacitance as claimed in claim 12 is characterized in that, described pattern layer is dielectric materials layer.
15. the semiconductor device that comprises high desnity metal-insulating barrier-metal capacitance as described in claim 13 or 14 is characterized in that, the Thickness scope of described pattern layer is 300 dust to 4000 dusts.
16. the semiconductor device that comprises high desnity metal-insulating barrier-metal capacitance as claimed in claim 12 is characterized in that, the material of described the first insulating barrier is silicon dioxide, silicon nitride, a kind of in the smooth or alundum (Al2O3) of three oxidations two.
17. the semiconductor device that comprises high desnity metal-insulating barrier-metal capacitance as claimed in claim 16 is characterized in that, the Thickness scope of described the first insulating barrier is 150 dust to 700 dusts.
18. the semiconductor device that comprises high desnity metal-insulating barrier-metal capacitance as claimed in claim 12 is characterized in that, the material of described the second insulating barrier is the silex glass of unadulterated Si oxide or doped with fluorine.
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