CN102446859A - Method for making floating dynamic random access memory unit capable of increasing writing speed - Google Patents
Method for making floating dynamic random access memory unit capable of increasing writing speed Download PDFInfo
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- CN102446859A CN102446859A CN2011103143272A CN201110314327A CN102446859A CN 102446859 A CN102446859 A CN 102446859A CN 2011103143272 A CN2011103143272 A CN 2011103143272A CN 201110314327 A CN201110314327 A CN 201110314327A CN 102446859 A CN102446859 A CN 102446859A
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Abstract
The invention discloses a method for making a floating dynamic random access memory unit capable of increasing the writing speed, which comprises a lightly doping and drain injecting technology and is characterized in that the lightly doping and drain injecting technology comprises the following steps of: masking an N trap region with photoresist, injecting a pentavalent element with a first measurement value into a P trap region firstly, and then injecting a trivalent element with a second measurement value into the P trap region; and masking the P trap region with photoresist, injecting the trivalent element with the first measurement value into the N trap region firstly, and then injecting the pentavalent element with the second measurement value into the N trap region, wherein the second measurement value is smaller than the first measurement value. In the lightly doping and drain injecting technology, with the adoption of a reverse injection method, impurity dispersing centers at a drain terminal are increased, and the impact ionization rate of a current carrier between the drain terminal and the impurity dispersing centers is increased, so that the substrate current of a floating effect memory unit is increased, and the writing speed of the floating effect memory unit is increased.
Description
Technical field
The present invention relates to the manufacture method of a kind of dynamic random access memory (DRAM) unit; This dynamic storage unit is a kind of floater effect (Floating Body Effect that utilizes; Be FBE) dynamic random access memory (DRAM) unit, the invention particularly relates to a kind of manufacture method of buoyancy aid DRAM cell of high writing speed.
Background technology
The development of embedded dynamic memory technology has made big capacity DRAM very general in present system level chip (SOC).The big embedded dynamic memory of capacity (eDRAM) has brought to SOC can only be through the various benefits that adopt embedded technology to realize such as improving bandwidth and reduction power consumption etc.Each memory cell of the embedded dynamic memory of tradition (eDRAM) also needs a deep trench capacitor structure except transistor, the deep trench of capacitor makes that its width of aspect ratio of memory cell is a lot of greatly, causes the manufacturing process difficulty.Its manufacture craft and cmos vlsi technology are very incompatible, have limited its application in embedded system chip.
Floater effect memory cell (Floating Body Cell; Be FBC) be a kind of floater effect (Floating Body Effect that utilizes; Be FBE) DRAM cell, its principle is the floater effect that utilizes the buffer action of oxygen buried regions (BOX) in silicon-on-insulator (Silicon on Insulator, the i.e. SOI) device to bring; Segregate buoyancy aid (Floating Body) as memory node, is realized one writing and write " 0 ".
With reference to the shown prior art of Figure 1A ~ 1B, it discloses the operation principle of FBC.
In Figure 1A, be example with NMOS, add positive bias at grid (G) and drain electrode (D) end, break-over of device is because the transverse electric field effect; Electronics the drain electrode near with the silicon atom ionization by collision, the generation electron hole pair, a part of hole is swept substrate by longitudinal electric field; Form substrate current, because the existence of aerobic buried regions (BOX), substrate current can't discharge; Make the hole gather, be defined as first kind of store status, may be defined as one writing at buoyancy aid.The situation of writing " 0 " applies positive bias on grid shown in Figure 1B, in drain electrode, apply back bias voltage, and through the PN junction forward bias, launch from buoyancy aid in the hole, is defined as second kind of store status.Because gathering of substrate electric charge can change the threshold voltage (Vt) of device, can cause the difference of threshold voltage through this two states of big or small perception of electric current, promptly realizes read operation.Because the floater effect memory cell has been removed the capacitor among traditional DRAM; Make its technological process fully and the CMOS process compatible; Simultaneously can the higher memory of component density, therefore be hopeful to substitute existing traditional eDRAM and be applied in the embedded system chip.
The floater effect memory cell is when one writing, and promptly charge carrier is in the process that substrate gathers, and the speed of one writing is by the decision of the size of substrate current.Improve the substrate current of floater effect memory cell, just can improve the writing speed of floater effect memory cell, thereby improve the performance of floater effect memory cell.
Therefore; A kind of substrate current that can improve the floater effect memory cell is provided, thereby the buoyancy aid DRAM cell and preparation method thereof that improves the writing speed of floater effect memory cell and improve the performance of floater effect memory cell just seems particularly important.
Summary of the invention
The objective of the invention is to be to strengthen the impact ionization rate of charge carrier between drain terminal and impurity scattering center, thereby improved the substrate current of floater effect memory cell, improved the writing speed of floater effect memory cell.
The present invention discloses a kind of manufacture method of buoyancy aid DRAM cell of high writing speed; Comprise: on substrate, form the N trap and the P trap at some intervals earlier, leave with a shallow trench isolation between adjacent N trap and the P trap, on said N trap, form first polysilicon gate; On said P trap, form second polysilicon gate; Then carry out the lightly doped drain injection technology, wherein, said lightly doped drain injection technology comprises the steps:
The zone of said N trap is injected the pentad of first metering earlier, the triad of second metering of reinjecting with photoresist masking in the zone of P trap;
The zone of said P trap is injected the triad of first metering earlier, the pentad of second metering of reinjecting with photoresist masking in the zone of N trap;
Wherein, said second variable is less than said first variable.
Above-mentioned manufacture method, wherein, the difference of said second variable and said first metering is that lightly doped drain injects variable.
Above-mentioned manufacture method, wherein, the direction that said element injects is a vertical direction.
The present invention is through preparing in the process in the floater effect memory cell, in lightly doped drain (Lightly Doped Drain, i.e. LDD) injection technology; Adopt the reverse method of injecting (Counter Dope); Make the impurity scattering center of drain terminal increase, strengthen the impact ionization rate of charge carrier between drain terminal and impurity scattering center, thereby improved the substrate current of floater effect memory cell; Improved the writing speed of floater effect memory cell; Simultaneously, relative traditional handicraft, method of the present invention does not increase unnecessary processing step.
Description of drawings
Through reading the detailed description of non-limiting example being done with reference to following accompanying drawing, it is more obvious that the present invention and characteristic thereof, profile and advantage will become.Mark identical in whole accompanying drawings is indicated identical part.Painstakingly proportionally do not draw accompanying drawing, focus on illustrating purport of the present invention.In the accompanying drawings, for cheer and bright, the part parts have been amplified.
Figure 1A is the process of the floater effect memory cell one writing of prior art;
Figure 1B writes the process of " 0 " for the floater effect memory cell of prior art; And
Fig. 2 shows employing manufacture method of the present invention, the reverse sketch map that increases substrate current that injects.
Embodiment
Below in conjunction with accompanying drawing and embodiment the present invention is further elaborated.Embodiment described herein only is used to explain the present invention, and is not used in qualification protection scope of the present invention.
The present invention increases the injection metering of different elements through in lightly doped drain (Lightly Doped Drain, i.e. LDD) injection technology, improves the unit intensity at impurity scattering center.
With reference to figure 3, improvement of the present invention is primarily aimed at the lightly doped drain injection technology in the CMOS manufacture craft, therefore; The preorder step of memory making adopts prior art, comprising: on substrate 1, form the N trap 3 and P trap (not shown among Fig. 3) at some intervals earlier, separate with a shallow trench isolation STI between adjacent N trap 3 and the P trap; On said N trap 3, form first polysilicon gate 10, on said P trap, form second polysilicon gate (not shown among Fig. 3), then carry out the lightly doped drain injection technology; Among Fig. 3, wherein, also show the oxygen buried regions 2 that is positioned on the substrate 1; Source electrode 11 and drain electrode 122, said lightly doped drain injection technology comprises the steps:
The zone of said N trap 3 is injected the pentad of first metering earlier, the triad of second metering of reinjecting with photoresist masking in the zone of P trap;
The zone of said P trap is injected the triad 101 of first metering earlier, the pentad 102 of second metering of reinjecting with photoresist masking in the zone of N trap 3;
Above-mentioned is prior art with the photoresist masking subregion, can cover N trap and P trap by first spin coating photoresist, and etching is removed the part photoresist and made N trap or the exposure of P well area again, and those skilled in the art can combine existing techniques in realizing, do not repeat them here.
Wherein, said second variable is less than said first variable.
Like this, the pentad 102 that the triad 101 and second that measures with first of N trap 3 measures is injected to example, the neutralization that distributes in a spot of pentad 102 and the first metering triad 101, and raising is greatly measured in total injection.
In a preference, for the electric property that guarantees the memory cell that memory cell that manufacture method of the present invention obtains is original relatively is constant, the difference of said second variable and said first metering is that lightly doped drain injects variable.The triad that the pentad and second that measures with first of P trap measures is injected to example, compares prior art, has increased the reverse injection (Counter Dope) of the triad of doses.Carrying out pentad when injecting, implantation dosage can increase to some extent, and the implantation dosage of increase just in time equate with the implantation dosage of the triad of reverse injection, thereby the implantation dosage that has guaranteed total pentad is constant, is lightly doped drain injection variable.
In a specific embodiment, said pentad is an arsenic.
In a specific embodiment, said triad is a boron.
More particularly, said first metering is 5.05X10
14/ cm
2
More particularly, said second metering is 0.05X10
14/ cm
2
Further, the direction of said element injection is a vertical direction.
In 65 nanometer SOI technologies, the floater effect memory cell that common NMOS constitutes, its LDD implantation dosage is arsenic 5X10
14/ cm
2, adopt oppositely and inject, can take arsenic implantation dosage 5.05X10
14/ cm
2, adopting the boron implantation dosage simultaneously is 0.05X10
14/ cm
2Oppositely inject, total group-v element implantation dosage still is 5X10
14/ cm
2, remain unchanged, simultaneously, the density at impurity scattering center is by the 5X10 in the common process
14/ cm
2Become 5.1X0
14/ cm
2, because the existence of reverse injection triads such as boron is arranged, the impurity scattering center of device drain terminal increases; Increased the collision probability at charge carrier and impurity scattering center, under the prerequisite that the impurity scattering centre concentration suitably increases, the electron hole pair density that collision produces increases; The hole is swept substrate by longitudinal electric field and forms substrate current (with reference to the indication of the arrow among the figure 3); Because the density in hole increases, thereby substrate current increases, and has improved the writing speed of floater effect memory cell.
Those skilled in the art combine prior art and the foregoing description can realize said variant, and such variant does not influence flesh and blood of the present invention, does not repeat them here.
More than preferred embodiment of the present invention is described.It will be appreciated that the present invention is not limited to above-mentioned specific implementations, equipment of wherein not describing in detail to the greatest extent and structure are construed as with the common mode in this area to be implemented; Any those of ordinary skill in the art; Do not breaking away under the technical scheme scope situation of the present invention; All the method for above-mentioned announcement capable of using and technology contents are made many possible changes and modification to technical scheme of the present invention; Or being revised as the equivalent embodiment of equivalent variations, this does not influence flesh and blood of the present invention.Therefore, every content that does not break away from technical scheme of the present invention, all still belongs in the scope of technical scheme protection of the present invention any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (3)
1. the manufacture method of the buoyancy aid DRAM cell of a high writing speed; Comprise: on substrate, form the N trap and the P trap at some intervals earlier, leave with a shallow trench isolation between adjacent N trap and the P trap, on said N trap, form first polysilicon gate; On said P trap, form second polysilicon gate; Then carry out the lightly doped drain injection technology, it is characterized in that, said lightly doped drain injection technology comprises the steps:
The zone of said N trap is injected the pentad of first metering earlier, the triad of second metering of reinjecting with photoresist masking in the zone of P trap;
The zone of said P trap is injected the triad of first metering earlier, the pentad of second metering of reinjecting with photoresist masking in the zone of N trap;
Wherein, said second variable is less than said first variable.
2. manufacture method according to claim 1 is characterized in that, the difference of said second variable and said first metering is that lightly doped drain injects variable.
3. according to any described manufacture method in the claim 1 and 2, it is characterized in that the direction that said element injects is a vertical direction.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090242996A1 (en) * | 2008-03-31 | 2009-10-01 | Van Bentum Ralf | Soi transistor with floating body for information storage having asymmetric drain/source regions |
| CN102169714A (en) * | 2010-02-25 | 2011-08-31 | 复旦大学 | Method for refreshing bulk-silicon floating body cell transistor memory |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090242996A1 (en) * | 2008-03-31 | 2009-10-01 | Van Bentum Ralf | Soi transistor with floating body for information storage having asymmetric drain/source regions |
| CN102169714A (en) * | 2010-02-25 | 2011-08-31 | 复旦大学 | Method for refreshing bulk-silicon floating body cell transistor memory |
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