CN102446828A - Manufacturing process for removing redundant filled metal from metal layers - Google Patents
Manufacturing process for removing redundant filled metal from metal layers Download PDFInfo
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- CN102446828A CN102446828A CN2011102851052A CN201110285105A CN102446828A CN 102446828 A CN102446828 A CN 102446828A CN 2011102851052 A CN2011102851052 A CN 2011102851052A CN 201110285105 A CN201110285105 A CN 201110285105A CN 102446828 A CN102446828 A CN 102446828A
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Abstract
The invention provides a manufacturing process for removing redundant filled metal from metal layers, wherein the process comprises the following steps of: 1) depositing a low-k-value medium layer; 2) forming an etching blocking layer on the deposited low-k-value medium layer; 3) completing photoetching and etching to remove an etching blocking layer at the non-redundant metal region; 4) depositing the low-k-value medium layer again to obtain the low-k-value medium layer with the required thickness; 5) carrying out photoetching and etching again to form a metal conducting wire groove and a redundant metal groove; 6) filling the conducting wire metal and the redundant metal, and completing the deposition of the metal layers; 7) carrying out chemical and mechanical grinding on the metal layers; and 8) carrying out chemical and mechanical grinding continuously on the low-k-value medium layer and a metal mixed layer, and further removing the redundant metal. According to the method, through the process that the redundant metal is further removed by utilizing chemical and mechanical grinding in manufacturing single Damascus and double Damascus metal interconnection, the coupling capacitance in the metal layers and between the metal layers caused by redundant filed metal can be reduced or eliminated effectively, and the manufacturing process is very practical.
Description
Technical field
The present invention relates to a kind of semiconductor fabrication process, particularly relate to a kind of redundant metal filled manufacturing process of metal level of removing.
Background technology
Along with the integrated level of semiconductor chip improves constantly, transistorized characteristic size is constantly dwindled.Enter into after 130 nm technology node, receive the restriction of the high-ohmic of aluminium, copper-connection substitution of Al interconnection gradually becomes the metal interconnected main flow that gets.Because the dry etch process of copper is difficult for realizing that the manufacture method of copper conductor can not obtain through etching sheet metal as aluminum conductor.The manufacture method of the copper conductor that extensively adopts now is the embedding technique that is called Damascus technics.This technology low k value dielectric layer of deposition at first on silicon chip then through photoetching be etched in and form metallic channel in the dielectric layer, continues follow-up layer metal deposition and metal level cmp and processes plain conductor.This technology comprises the single Damascus technics of only making plain conductor and the dual damascene process of making contact hole and plain conductor simultaneously.
In Damascus technics, use final formation of metal level cmp and be embedded in the plain conductor in the dielectric layer.In order to reach uniform grinding effect, require the metallic pattern density on the silicon chip even as far as possible.And the metallic pattern density of product design usually can not satisfy the requirement of the cmp uniformity.The method that solves is to fill redundant metal at the white space of domain to make domain pattern density homogenizing.Redundant metal has improved the uniformity of pattern density, but has introduced extra intermetallic coupling capacitance inevitably.In order to reduce the negative effect that extra coupling capacitance brings device, in the redundant filling quantity that will reduce redundant metal when metal filled as far as possible of design.
Electric capacity can be calculated by formula:
Wherein, ε
0Be permittivity of vacuum; ε
rBe the medium dielectric constant; S is relative metallic area; The intermetallic distance that d is.Visible by above-mentioned formula, the relative area that reduces metal can reduce electric capacity with increase intermetallic distance.That is to say that the volume that reduces redundant metal can reduce owing to adding the extra intermetallic coupling capacitance that redundant metal is introduced.
The patent No. is the manufacturing approach that the Chinese patent of CN101752298A relates to a kind of metal interconnect structure; Comprise: Semiconductor substrate is provided; Have dual damascene opening in intermetallic dielectric layer, the intermetallic dielectric layer on the said Semiconductor substrate, be covered in barrier layer and the metal level on the barrier layer on the said intermetallic dielectric layer, said metal level is filled in the dual damascene opening; The surface of the said intermetallic dielectric layer of planarization is to form metal interconnecting layer; On said metal interconnecting layer, form first etching stop layer; Remove said first etching stop layer through flatening process; Form the passivation layer on second etching stop layer, second etching stop layer on the metal interconnecting layer remove said first etching stop layer through flatening process after and be embedded in the soldering pad layer in the said passivation layer, said soldering pad layer is positioned on the said metal interconnecting layer.The circuit that said method can be avoided being caused by the metal protuberance of metal interconnecting layer connects defective, improves the reliability of semiconductor device.
The patent No. is the manufacturing approach that the Chinese patent of CN101740479A relates to a kind of semiconductor device; Comprise: Semiconductor substrate is provided; The surface of the said Semiconductor substrate of planarization is to form metal interconnecting layer, and said planarization comprises at least: remove the outer excess metal of said dual damascene opening; Remove the outer barrier layer of said dual damascene opening; Form the passivation layer on etching stop layer, the etching stop layer on the Semiconductor substrate after planarization and be embedded in the soldering pad layer in the said passivation layer, said soldering pad layer is positioned on the said metal interconnecting layer; Also comprise before removing the outer barrier layer of said dual damascene opening: place the equipment that forms said etching stop layer to carry out heat treated said Semiconductor substrate, the temperature of said heat treated is more than or equal to the temperature of follow-up arbitrary technology.Adopt the manufacturing approach of said semiconductor device, can avoid the oxidized erosion and form corrosion default in rear-end cleaning process of these projections, improve the reliability of device.
For in the metal level that reduces or eliminates redundant metal filled introducing effectively with the coupling capacitance of metal interlevel, the present invention provides a kind of attenuate or removes the redundant metal filled manufacturing process of metal level.Preferred embodiment provided by the present invention and that as just example but invention is constituted restriction embodies in embodiment to some extent.
Summary of the invention
In view of the above problems, the object of the present invention is to provide a kind of attenuate or the redundant metal filled manufacturing process of removal metal level.The present invention proposes a kind ofly to utilize the further attenuate of cmp or remove the technology than the redundant metal of lead metal foil fully in metal interconnected making single Damascus and dual damascene.The present invention is metal filled through removing the metal level redundancy, can reduce or eliminate in the metal level of redundant metal filled introducing the coupling capacitance with metal interlevel effectively.
The object of the invention and solve its technical problem and adopt following technical scheme to realize.
A kind of redundant metal filled manufacturing process of metal level of removing that the present invention proposes, its processing step is following:
1) the low k value dielectric layer of deposition;
2) on the low k value dielectric layer of deposition, form etching barrier layer;
3) accomplish the etching barrier layer that photoetching and etching are removed the nonredundancy metallic region;
4) deposition is hanged down the low k value dielectric layer that k value medium reaches desired thickness once more;
5) photoetching and etching form metallic channel and redundant metallic channel once more;
6) carry out the filling of lead metal and redundant metal, accomplish layer metal deposition;
7) metal level is carried out cmp;
8) continue low k value dielectric layer of cmp and metal mixed layer, further remove redundant metal.
Described etching barrier layer, its material are carborundum, silicon nitride, silicon oxynitride, titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, tantalum oxide.
Described etching barrier layer, its thickness range is between 1 nanometer to 1000 nanometer.
The present invention is metal filled through removing the metal level redundancy, can reduce or eliminate in the metal level of redundant metal filled introducing the coupling capacitance with metal interlevel effectively.
Above-mentioned explanation only is the general introduction of technical scheme of the present invention; Understand technological means of the present invention in order can more to know; And can implement according to the content of specification, and for let of the present invention above-mentioned with other purposes, feature and advantage can be more obviously understandable, below special act preferred embodiment; And conjunction with figs., specify as follows.
Description of drawings
With reference to appended accompanying drawing, to describe embodiments of the invention more fully.Yet appended accompanying drawing only is used for explanation and sets forth, and does not constitute limitation of the scope of the invention.
Fig. 1 illustrates the profile of low k value dielectric layer and etching barrier layer.
Fig. 2 illustrates the profile of the etching barrier layer of accomplishing photoetching and etching removal nonredundancy metallic region.
Fig. 3 illustrates and accomplishes the low post-depositional again profile of k value dielectric layer.
Fig. 4 illustrates and accomplishes photoetching and etching formation metallic channel and redundant metallic channel profile.
Fig. 5 illustrates and accomplishes the lead metal profile metal filled with redundancy behind layer metal deposition and the metal level cmp.
Fig. 6 illustrates cmp and further removes redundant metal filled profile.
Reference numeral: 1. low k value dielectric layer, 2. etching barrier layer, 3. redundant metallic channel, 4. metallic channel, 5. plain conductor, 6. redundant metal.
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention,,, specify as follows the redundant metal filled manufacturing process of the removal metal level that proposes according to the present invention below in conjunction with accompanying drawing and preferred embodiment.
Different embodiments of the invention will details are as follows, with the different techniques characteristic of embodiment of the present invention, will be understood that, the unit of the specific embodiment of the following stated and configuration are in order to simplify the present invention, and it is merely example and does not limit the scope of the invention.
A kind of redundant metal filled manufacturing process of metal level of removing that the present invention proposes, its processing step is following:
1) the low k value dielectric layer of deposition;
2) on the low k value dielectric layer of deposition, form etching barrier layer;
3) accomplish the etching barrier layer that photoetching and etching are removed the nonredundancy metallic region;
4) deposition is hanged down the low k value dielectric layer that k value medium reaches desired thickness once more;
5) photoetching and etching form metallic channel and redundant metallic channel once more;
6) carry out the filling of lead metal and redundant metal, accomplish layer metal deposition;
7) metal level is carried out cmp;
8) continue low k value dielectric layer of cmp and metal mixed layer, further remove redundant metal.
Wherein the material of etching barrier layer is carborundum, silicon nitride, silicon oxynitride, titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, tantalum oxide, and its thickness range is between 1 nanometer to 1000 nanometer.
At first behind the low k value dielectric layer of deposition, on the low k value dielectric layer of deposition, form etching barrier layer, Fig. 1 illustrates the profile of low k value dielectric layer and etching barrier layer.Remove the etching barrier layer of nonredundancy metallic region then through photoetching and etching, Fig. 2 illustrates the profile of the etching barrier layer of accomplishing photoetching and etching removal nonredundancy metallic region.The low k value medium of deposition reaches the low k value dielectric layer of desired thickness once more, and Fig. 3 illustrates and accomplishes the low post-depositional again profile of k value dielectric layer.Form metallic channel and redundant metallic channel through photoetching and etching again, Fig. 4 illustrates and accomplishes photoetching and etching formation metallic channel and redundant metallic channel profile, and wherein redundant metallic channel is more shallow than metallic channel.Then carry out the filling of lead metal and redundant metal, accomplish layer metal deposition after, metal level is carried out cmp, Fig. 5 illustrates and accomplishes the lead metal profile metal filled with redundancy behind layer metal deposition and the metal level cmp.Continue low k value dielectric layer of cmp and metal mixed layer at last, further remove redundant metal, Fig. 6 illustrates cmp and further removes redundant metal filled profile.
This method utilizes cmp further to remove the technology of redundant metal with dual damascene in metal interconnected through a kind of making single Damascus, can reduce or eliminate in the metal level of redundant metal filled introducing effectively and the coupling capacitance of metal interlevel.
Through explanation and accompanying drawing, provided the exemplary embodiments of the ad hoc structure of embodiment.Although foregoing invention has proposed existing preferred embodiment, yet these contents are not as limitation.For a person skilled in the art, read above-mentioned explanation after, various variations and revise undoubtedly will be obvious.Therefore, appending claims should be regarded whole variations and the correction of containing true intention of the present invention and scope as.Any and all scope of equal value and contents all should be thought still to belong in the intent of the present invention and the scope in claims scope.
Claims (4)
1. remove the redundant metal filled manufacturing process of metal level for one kind, it is characterized in that its processing step is following:
1) the low k value dielectric layer of deposition;
2) on the low k value dielectric layer of deposition, form etching barrier layer;
3) accomplish the etching barrier layer that photoetching and etching are removed the nonredundancy metallic region;
4) deposition is hanged down the low k value dielectric layer that k value medium reaches desired thickness once more;
5) photoetching and etching form metallic channel and redundant metallic channel once more;
6) carry out the filling of lead metal and redundant metal, accomplish layer metal deposition;
7) metal level is carried out cmp;
8) continue low k value dielectric layer of cmp and metal mixed layer, further remove redundant metal.
2. a kind of redundant metal filled manufacturing process of metal level of removing as claimed in claim 1; It is characterized in that the material of said described etching barrier layer is carborundum, silicon nitride, silicon oxynitride, titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, tantalum oxide.
3. a kind of redundant metal filled manufacturing process of metal level of removing as claimed in claim 1 is characterized in that the thickness range of said described etching barrier layer is between 1 nanometer to 1000 nanometer.
4. a kind of redundant metal filled manufacturing process of metal level of removing as claimed in claim 4 is characterized in that described redundant metallic channel is more shallow than metallic channel.
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| CN201110285105.2A CN102446828B (en) | 2011-09-23 | 2011-09-23 | Manufacturing process for removing redundant filled metal from metal layers |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6849549B1 (en) * | 2003-12-04 | 2005-02-01 | Taiwan Semiconductor Manufacturing Co., Ltd | Method for forming dummy structures for improved CMP and reduced capacitance |
| CN101231667A (en) * | 2007-01-22 | 2008-07-30 | 台湾积体电路制造股份有限公司 | Method of filling redundancy for semiconductor manufacturing process and semiconductor device |
| US7470630B1 (en) * | 2005-04-14 | 2008-12-30 | Altera Corporation | Approach to reduce parasitic capacitance from dummy fill |
| CN102117348A (en) * | 2009-12-31 | 2011-07-06 | 中国科学院微电子研究所 | Preprocessing method using redundancy metal filling for realizing layout density uniformity |
| CN102130043A (en) * | 2010-12-30 | 2011-07-20 | 中国科学院微电子研究所 | Method for filling redundancy metal |
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- 2011-09-23 CN CN201110285105.2A patent/CN102446828B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6849549B1 (en) * | 2003-12-04 | 2005-02-01 | Taiwan Semiconductor Manufacturing Co., Ltd | Method for forming dummy structures for improved CMP and reduced capacitance |
| US7470630B1 (en) * | 2005-04-14 | 2008-12-30 | Altera Corporation | Approach to reduce parasitic capacitance from dummy fill |
| CN101231667A (en) * | 2007-01-22 | 2008-07-30 | 台湾积体电路制造股份有限公司 | Method of filling redundancy for semiconductor manufacturing process and semiconductor device |
| CN102117348A (en) * | 2009-12-31 | 2011-07-06 | 中国科学院微电子研究所 | Preprocessing method using redundancy metal filling for realizing layout density uniformity |
| CN102130043A (en) * | 2010-12-30 | 2011-07-20 | 中国科学院微电子研究所 | Method for filling redundancy metal |
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