CN102446725A - Cascaded grid production method - Google Patents

Cascaded grid production method Download PDF

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Publication number
CN102446725A
CN102446725A CN2010105070642A CN201010507064A CN102446725A CN 102446725 A CN102446725 A CN 102446725A CN 2010105070642 A CN2010105070642 A CN 2010105070642A CN 201010507064 A CN201010507064 A CN 201010507064A CN 102446725 A CN102446725 A CN 102446725A
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layer
etching
dielectric coefficient
silicon dioxide
dielectric
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刘金华
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
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Abstract

The invention provides a cascaded grid production method which is characterized in that: a wafer of a silicon substrate having a negative (N) well, a positive (P) well and a shallow trough isolator (STI) is provided, an interlayer grid oxidized layer and a high dielectric coefficient grid electric dielectric layer are sequentially produced on the surface of a wafer device, and the method comprises the following steps that: a first silicon dioxide layer is formed on the surface of a deposited first high dielectric coefficient grid dielectric coverage layer, and after a first protection layer and an n-type high dielectric coefficient grid dielectric coverage layer are sequentially etched above the P well, first-time cineration is carried out to remove photoresist which is left on the first protection layer; then after a second protection layer and a p-type high dielectric coefficient grid dielectric coverage layer are formed above the N well, second-time cineration is carried out to remove photoresist, and then the first and the second protection layers are removed in a wet etching way; and finally a deposited metal layer is etched to form a cascaded grid. During the photoresist cineration removal process, the first and the second protection layers are used as the protection layers of the p-type and the n-type high dielectric coefficient grid dielectric coverage layers, so the damage of the photoresist removal process on the p-type high dielectric coefficient grid dielectric coverage layer and the n-type high dielectric coefficient grid dielectric coverage layer can be effectively avoided, and the threshold voltage of the high dielectric coefficient grid dielectric/metal cascaded grid complementary metal oxide semiconductor (CMOS) device can be reduced.

Description

A kind of range upon range of grid making method
Technical field
The present invention relates to a kind of semiconductor making method, particularly a kind of range upon range of grid making method.
Background technology
At present, semi-conductor industry is growth of device on wafer (wafer) device side of silicon substrate mainly, for example, and CMOS complementary metal-oxide-semiconductor (CMOS) device.Cmos device occupies an important position on the semiconductor technology of microprocessor, flash memory and application-specific IC (ASIC).Generally adopt now two trap CMOS technologies on silicon substrate, to make the n type channel mosfet that p type NMOS N-channel MOS N FET (MOSFET) that conducting channel is the hole and conducting channel are electronics simultaneously; Concrete steps are: at first; Zones of different in the silicon substrate become respectively with the electronics through mixing be (n type) silicon substrate of majority carrier and be after (p type) silicon substrate of majority carrier with the hole; Between n type silicon substrate and p type silicon substrate, make shallow trench isolation from (STI) 101; The method of injecting with ion in the STI both sides then forms cavity type doped diffusion region (P trap) 102 and electron type doped diffusion region (N trap) 103 respectively; Then make the range upon range of grid of forming by gate dielectric layer 104 and metal gate 105 successively in the wafer device side of P trap 102 and N trap 103 positions respectively; In P trap 102 and N trap 103, make source electrode and drain electrode respectively at last, source electrode is arranged in the both sides (figure does not draw) of range upon range of grid with draining, and in the P trap, forms n type channel mosfet; In the N trap, form p type channel mosfet, obtain cmos device structure as shown in Figure 1.
The range upon range of grid of traditional oxynitrides/polysilicon, be with nitrogen oxide as gate dielectric layer, polysilicon is as metal gate.Along with development of semiconductor, the cmos device of the range upon range of grid of oxynitrides/polysilicon can not satisfy the needs of small size semiconductor technology because problem such as leakage current and power consumption be excessive.Therefore, the laminated gate structure to CMOS has proposed with high-dielectric coefficient (High K) material as gate dielectric layer, with the High K gate-dielectric/metal stacking grid technology of metal material as metal gate.More very important in the High K gate-dielectric of CMOS/metal stacking grid technology is exactly the threshold voltage of controlling p type channel mosfet and n type channel mosfet.But in the manufacturing process of follow-up source electrode and drain electrode, the annealing steps of employing can cause interface state instability between High K gate dielectric layer and the metal gate, makes the threshold voltage of cmos device very big variation arranged, bad control.In order to address this problem; Between the High K gate dielectric layer of p type channel mosfet and n type channel mosfet and metal gate, introduce high-dielectric coefficient gate medium cover layer (capping layer) respectively; Since between High K gate dielectric layer and the capping layer and the interface state between cappinglayer and the metal gate more stable, thereby can reduce the variations in threshold voltage that subsequent anneal technology causes.Usually, with lanthana (La 2O 3) as the HighK gate dielectric layer of n type channel mosfet and the n type capping layer between the metal gate, with aluminium oxide (Al 2O 3) as the High K gate dielectric layer of p type channel mosfet and the p type capping layer between the metal gate.
Provide have above-mentioned STI301, the wafer (wafer) of p type (or the n type) silicon substrate of P trap 302 and N trap 303, on said wafer device side, make the concrete steps of HighK gate dielectric layer/metal stacking grid of CMOS in conjunction with Fig. 3 a～3g explanation:
Step 201, Fig. 3 a are the cross-sectional view of the step 201 of range upon range of grid making method in the prior art; Shown in Fig. 3 a; The wafer device side is gate oxide (inter layer gateoxide) (not drawing among the figure) and High K gate dielectric layer 304 between making layer successively, at High K gate dielectric layer 304 surface deposition lanthanas 305;
Step 202, Fig. 3 b are step 202 cross-sectional view of range upon range of grid making method in the prior art; Shown in Fig. 3 b; The first etching oxidation lanthanum 305 after first photoetching; High K gate dielectric layer 304 surfaces above P trap 302 form n type capping layer305 ', expose the High K gate dielectric layer 304 above N trap 303;
In this step, first photoetching is meant, first photoengraving pattern of definition n type capping layer on first photoresist 306 that overexposure and developing process are applying on the lanthana;
In this step, lanthana is used for the gate electrode stack structure of n type channel mosfet as the first high-dielectric coefficient gate medium cover layer; Can also use aluminium oxide as the first high-dielectric coefficient gate medium cover layer, High K gate dielectric layer 304 surfaces above N trap 303 form p type capping layer, expose the High K gate dielectric layer above P trap 302;
In this step, be the mask first etching oxidation lanthanum 305 with first photoengraving pattern; First etching is dry etching or wet etching.The used etching gas of dry etching is the plasma gas that contains oxygen; The wet etching solutions employed is hydrochloric acid or ammoniacal liquor.This is a prior art, repeats no more.
Step 203, Fig. 3 c are step 203 cross-sectional view of range upon range of grid making method in the prior art; Shown in Fig. 3 c; After etching formed n type capping layer305 ', first ashing was removed and is remained in first photoresist 306 on the n type capping layer305 '.
Step 204, Fig. 3 d are step 204 cross-sectional view of range upon range of grid making method in the prior art, shown in Fig. 3 d, and wafer device side deposition of aluminium oxide 307;
Step 205, Fig. 3 e are step 205 cross-sectional view of range upon range of grid making method in the prior art; Shown in Fig. 3 e; The second etching oxidation aluminium 307 after second photoetching; High K gate dielectric layer 304 surfaces above N trap 303 form p type capping layer307 ', expose n type cappinglayer305 ';
In this step, second photoetching is meant, through second photoengraving pattern of overexposure and developing process definition p type capping layer on second photoresist 308 that applies on the aluminium oxide 307;
In this step, aluminium oxide 307 is used for the gate electrode stack structure of p type channel mosfet as the second high-dielectric coefficient gate medium cover layer; If when step 201; Formed p type capping layer; Then use lanthana as the second high-dielectric coefficient gate medium cover layer, High K gate dielectric layer 304 surfaces above P trap 302 form n type capping layer, expose the HighK gate dielectric layer above N trap 303;
In this step, be the mask second etching oxidation aluminium 307 with second photoengraving pattern; Second etching is dry etching or wet etching.The used etching gas of dry etching is the plasma gas that contains oxygen; The wet etching solutions employed is hydrochloric acid or ammoniacal liquor.This is a prior art, repeats no more.
Step 206; Step 206 cross-sectional view of range upon range of grid making method in Fig. 3 f prior art; Shown in Fig. 3 f, after etching formed p type capping layer307 ', second ashing was removed and is remained in second photoresist 308 on the p type capping layer307 ';
Step 207 cross-sectional view of range upon range of grid making method in step 207, Fig. 3 g prior art; Shown in Fig. 3 g; Behind p type capping layer307 ' and the last depositing metal layers 309 of n type capping layer305 ', the 3rd etching forms High K gate dielectric layer/metal stacking grid after the 3rd photoetching.
In this step, the 3rd photoetching is meant, on the photoresist that layer on surface of metal applies, defines gate pattern through overexposure and developing process;
In this step, be mask with the photoresist with gate pattern, etching is removed metal level, p type capping layer307 ', n type capping layer305 ', High K gate dielectric layer and the interlayer gate oxide that is not covered by photoresist successively.
So far, High K gate dielectric layer/metal stacking grid of the CMOS of prior art completes.
But in the above-mentioned steps; After first dry etching forms p type capping layer and second dry etching formation n type capping layer; All will pass through ashing and remove the step of photoresist, this step is easy to damage p type capping layer and the n type capping layer that thickness is merely several nanometers, causes the interface state between High K gate dielectric layer and the metal gate unstable; The threshold voltage of cmos device is changed, wayward.
Summary of the invention
In view of this; The technical problem that the present invention solves is: in the manufacture process of high-dielectric coefficient gate-dielectric/metal stacking grid cmos device; After etching forms p type high-dielectric coefficient gate medium cover layer and n type high-dielectric coefficient gate medium cover layer; Removal can damage p type high-dielectric coefficient gate medium cover layer and n type high-dielectric coefficient gate medium cover layer as the cineration step of the photoresist of etch mask, and the threshold voltage of cmos device is changed, and is wayward.
For addressing the above problem, technical scheme of the present invention specifically is achieved in that
A kind of range upon range of grid making method; Wafer is provided; Have the wafer of the silicon substrate that N trap, P trap and shallow trench isolation leave in the silicon substrate of said wafer, make interlayer gate oxide and high-dielectric coefficient gate dielectric layer successively in the device side of said wafer, this method comprises:
Deposit the first high-dielectric coefficient gate medium cover layer and first silicon dioxide layer successively at said high-dielectric coefficient gate-dielectric laminar surface;
On said first silicon dioxide layer, apply first photoresist; Above the P trap, form first photoengraving pattern after first photoetching; With first photoengraving pattern is mask said first silicon dioxide layer of first etching and the said first high-dielectric coefficient gate medium cover layer of second etching successively, forms first protective layer and n type high-dielectric coefficient gate medium cover layer respectively;
First residual on said first protective layer photoresist is removed in first ashing;
Deposit the second high-dielectric coefficient gate medium cover layer and second silicon dioxide layer successively in said wafer device side;
On second silicon dioxide layer, apply second photoresist; Above the N trap, form second photoengraving pattern after second photoetching; With second photoengraving pattern is mask said second silicon dioxide layer of the 3rd etching and the said second high-dielectric coefficient gate medium cover layer of the 4th etching successively, forms second protective layer and p type high-dielectric coefficient gate medium cover layer respectively;
Second residual on said second protective layer photoresist is removed in second ashing;
The 5th etching is removed first protective layer and second protective layer;
Depositing metal layers on said wafer device side, etching forms high-dielectric coefficient gate dielectric layer/metal stacking grid after the 3rd photoetching.
The said first high-dielectric coefficient gate medium cover layer is a lanthana, the said second high-dielectric coefficient gate medium cover layer aluminium oxide.
The thickness range of said deposition first silicon dioxide layer and second silicon dioxide layer is 50 to 500 dusts.
The deposit thickness of said first silicon dioxide layer and second silicon dioxide layer equates.
Said first etching dry etching or the wet etching; Said the 3rd etching is dry etching or wet etching; Said the 5th etching is a wet etching.
A kind of range upon range of grid making method provides wafer, has N trap, P trap and shallow trench isolation in the silicon substrate of said wafer and leaves, and makes interlayer gate oxide and high-dielectric coefficient gate dielectric layer successively in the device side of said wafer, and this method comprises:
Deposit the first high-dielectric coefficient gate medium cover layer and first silicon dioxide layer successively at said high-dielectric coefficient gate-dielectric laminar surface;
On said first silicon dioxide layer, apply first photoresist; Above the N trap, form first photoengraving pattern after first photoetching; With first photoengraving pattern is mask said first silicon dioxide layer of first etching and the said first high-dielectric coefficient gate medium cover layer of second etching successively, forms first protective layer and p type high-dielectric coefficient gate medium cover layer respectively;
First residual on said first protective layer photoresist is removed in first ashing;
Deposit the second high-dielectric coefficient gate medium cover layer and second silicon dioxide layer successively in said wafer device side;
On second silicon dioxide layer, apply second photoresist; Form second photoengraving pattern at the P trap after second photoetching; With second photoengraving pattern is mask said second silicon dioxide layer of the 3rd etching and the said second high-dielectric coefficient gate medium cover layer of the 4th etching successively, forms second protective layer and n type high-dielectric coefficient gate medium cover layer respectively;
Second residual on said second protective layer photoresist is removed in second ashing;
The 5th etching is removed first protective layer and second protective layer;
Depositing metal layers on said wafer device side, etching forms high-dielectric coefficient gate dielectric layer/metal stacking grid after the 3rd photoetching.
The said first high-dielectric coefficient gate medium cover layer is an aluminium oxide, and the said second high-dielectric coefficient gate medium cover layer is a lanthana.
The thickness range of said deposition first silicon dioxide layer and second silicon dioxide layer is 50 to 500 dusts.
The deposit thickness of said first silicon dioxide layer and second silicon dioxide layer equates.
Said first etching is wet etching or dry etching; Said the 3rd etching is wet etching or dry etching; Said the 5th etching is a wet etching, and used solution is hydrofluoric acid.
Visible by above-mentioned technical scheme; The present invention removes in the process of photoresist in ashing; By first, second silicon dioxide layer as the tectal protective layer of high-dielectric coefficient gate medium; Effectively avoid podzolic process to p type high-dielectric coefficient gate medium cover layer and the tectal destruction of n type high-dielectric coefficient gate medium, reduced the variation of threshold voltage in follow-up pyroprocess of high-dielectric coefficient gate-dielectric/metal stacking grid cmos device.
Description of drawings
Fig. 1 is the cmos device structure chart;
Fig. 2 is the flow chart that High K gate dielectric layer/metal stacking grid of prior art CMOS is made;
Fig. 3 a～3g is the cross-sectional view that High K gate dielectric layer/metal stacking grid of prior art CMOS is made;
The flow chart that Fig. 4 makes for High K gate dielectric layer/metal stacking grid of CMOS of the present invention;
The cross-sectional view that Fig. 5 a～5l makes for High K gate dielectric layer/metal stacking grid of CMOS of the present invention.
Embodiment
For make the object of the invention, technical scheme, and advantage clearer, below with reference to the accompanying drawing embodiment that develops simultaneously, to further explain of the present invention.
The wafer (wafer) of p type (or the n type) silicon substrate with P trap 502, N trap 503 and STI501 is provided, and the concrete steps that are described in detail in High K gate dielectric layer/metal stacking grid of making CMOS on the silicon substrate in conjunction with Fig. 5 a～5l are following:
Step 401, Fig. 5 a are the cross-sectional view of the step 401 of the range upon range of grid making method of the present invention; Shown in Fig. 5 a; The wafer device side is successively between making layer behind gate oxide (inter layer gate oxide) (not drawing in the drawings), the High K gate dielectric layer 504, at High K gate dielectric layer 304 surface deposition lanthanas 505;
In this step, lanthana 505 is used for the gate electrode stack structure of n type channel mosfet as the first high-dielectric coefficient gate medium cover layer; If deposition of aluminium oxide is as the first high-dielectric coefficient gate medium cover layer; Then the alumina surface that becomes above N trap 503 of subsequent step 403 forms first protective layer; Step 404 can form p type cappinglayer by the High K gate-dielectric laminar surface above N trap 503, exposes the High K gate dielectric layer above P trap 502;
Step 402, Fig. 5 b are the cross-sectional view of the step 402 of the range upon range of grid making method of the present invention, shown in Fig. 5 b, and deposition first silicon dioxide layer 506 on lanthana 505;
In this step, deposit first silicon dioxide layer 506 and adopt plasma enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD), gases used is (tetra-ethyl-oxy-silane, Si (OC 2H 5) 4, TEOS) or the mist of silane and oxygen; The thickness range that deposits first silicon dioxide layer 506 is 50 to 500 dusts.
Step 403, Fig. 5 c are the cross-sectional view of the step 403 of the range upon range of grid making method of the present invention; Shown in Fig. 5 c; On first silicon dioxide layer 506, apply first photoresist 507; Said first silicon dioxide layer 506 of first etching after first photoetching, lanthana 505 surfaces above P trap 502 form first protective layer 506 ';
In this step, first photoetching is meant, on first photoresist 507, defines first photoengraving pattern of p type capping layer through overexposure and developing process;
In this step, be the mask first etching silicon dioxide layer 506 with first photoengraving pattern; First etching is dry etching or wet etching, and the used reacting gas of dry etching is sulfur fluoride (SF 6), carbon tetrafluoride (CF 4), fluoroform (CHF 3), octafluorocyclobutane (C 4F 8), ammonium fluoride (NF 3), perfluoroethane (C 2F 6), pentafluoroethane (C 2HF 5), octafluoro cyclopentene (C 5F 8), perfluorobutadiene (C 4F 6), difluoromethane (CH 2F 2), fluoromethane (CH 3F) and/or perfluoropropane (C 3F 8), can add argon Ar, nitrogen (N simultaneously 2), oxygen (O 2) and/or hydrogen (H 2) as assist gas; Dry etching adopts the end point determination method, when in finding the etching gas of discharging, also having lanthanum (La) element, is the etching terminal of first silicon dioxide layer 506; Wet method adopts hydrofluoric acid (HF) solution, according to the deposit thickness of first silicon dioxide layer 506, controls the time of first etching.
Step 404, Fig. 5 d are the cross-sectional view of the step 404 of the range upon range of grid making method of the present invention; Shown in Fig. 5 d; The second etching oxidation lanthanum 505; High K gate dielectric layer 304 surfaces above P trap 502 form n type capping layer505 ', expose the High K gate dielectric layer 304 above N trap 503;
In this step, be the mask second etching oxidation lanthanum 505 with first photoengraving pattern; Said second etching is that dry etching maybe can be a wet etching.The used etching gas of dry etching is the plasma gas that contains oxygen; The wet etching solutions employed is hydrochloric acid or ammoniacal liquor.This is a prior art, repeats no more.
Step 405, Fig. 5 e are the cross-sectional view of the step 405 of the range upon range of grid making method of the present invention, and shown in Fig. 5 e, first ashing is removed first protective layer 506 ' and gone up the first residual photoresist 507;
In this step, first protective layer 506 ' is isolated first photoresist 507 and n type cappinglayer505 ', and the process that makes the ashing of winning remove first photoresist 507 can not destroyed the surface of n type cappinglayer505 '.
Step 406, Fig. 5 f are the cross-sectional view of the step 406 of the range upon range of grid making method of the present invention, shown in Fig. 5 f, and wafer device side deposition of aluminium oxide 508;
In this step, aluminium oxide 508 is used for the gate electrode stack structure of p type channel mosfet as the second high-dielectric coefficient gate medium cover layer; If formed p type cappinglayer in the above-mentioned steps 404; Then deposit lanthana as the second high-dielectric coefficient gate medium cover layer; Then subsequent step 408 becomes lanthana surface formation second protective layer 509 ' above P trap 502; High K gate dielectric layer 304 surfaces that step 409 becomes above P trap 502 form n type capping layer, expose the High K gate dielectric layer above N trap 503;
Step 407, Fig. 5 g are the cross-sectional view of the step 407 of the range upon range of grid making method of the present invention, shown in Fig. 5 g, and deposition second silicon dioxide layer 509 on aluminium oxide 508;
In this step, deposit second silicon dioxide layer 509 and adopt PECVD or LPCVD, gases used is TEOS (tetra-ethyl-oxy-silane, Si (OC 2H 5) 4) or the mist of silane and oxygen; The thickness range that deposits second silicon dioxide layer 509 is 50 to 500 dusts.
The thickness that it should be noted that deposition first silicon dioxide layer 506 and second silicon dioxide layer 509 equates to be optimum execution mode.
Step 408, Fig. 5 h are the cross-sectional view of the step 408 of the range upon range of grid making method of the present invention; Shown in Fig. 5 h; On second silicon dioxide layer 509, apply second photoresist 510; The 3rd etching second silicon dioxide layer 509 after second photoetching, aluminium oxide 508 surfaces above N trap 503 form second protective layer 509 ';
In this step, second photoetching is meant, on second photoresist 510, defines second photoengraving pattern of p type capping layer through overexposure and developing process;
In this step, be mask the 3rd etching second silicon dioxide layer 509 with second photoengraving pattern; The 3rd etching is dry etching or wet etching, and the used reacting gas of dry etching is sulfur fluoride (SF 6), carbon tetrafluoride (CF 4), fluoroform (CHF 3), octafluorocyclobutane (C 4F 8), ammonium fluoride (NF 3), perfluoroethane (C 2F 6), pentafluoroethane (C 2HF 5), octafluoro cyclopentene (C 5F 8), perfluorobutadiene (C 4F 6), difluoromethane (CH 2F 2), fluoromethane (CH 3F) and/or perfluoropropane (C 3F 8), can add argon Ar, nitrogen (N simultaneously 2), oxygen (O 2) and/or hydrogen (H 2) as assist gas; Dry etching adopts the end point determination method, when in finding the etching gas of discharging, also having lanthanum (La) element, is the etching terminal of second silicon dioxide layer 509; Wet method adopts hydrofluoric acid (HF) solution, according to the deposit thickness of second silicon dioxide layer 509, controls the time of the 3rd etching.
Step 409, Fig. 5 i are the cross-sectional view of the step 409 of the range upon range of grid making method of the present invention; Shown in Fig. 5 i; The 4th etching oxidation aluminium 508, High K gate dielectric layer 304 surfaces above N trap 503 form p type capping layer, expose first protective layer 506 ';
In this step, be mask the 4th etching oxidation aluminium 508 with second photoengraving pattern; The 4th etching is that dry etching maybe can be a wet etching.The used etching gas of dry etching is the plasma gas that contains oxygen; The wet etching solutions employed is hydrochloric acid or ammoniacal liquor.This is a prior art, repeats no more.
Step 410, Fig. 5 j are the cross-sectional view of the step 410 of the range upon range of grid making method of the present invention, and shown in Fig. 5 j, second ashing is removed second protective layer 509 ' and gone up the second residual photoresist 510;
In this step, second protective layer 509 ' is isolated second photoresist 510 and p type cappinglayer508 ', and the process that makes second ashing remove second photoresist 510 can not destroyed the surface of p type cappinglayer508 '.
Step 411, Fig. 5 k are the cross-sectional view of the step 411 of the range upon range of grid making method of the present invention; Shown in Fig. 5 k; The 5th etching is removed first protective layer 506 ' and second protective layer 509 ', exposes n type capping layer505 ' and said p type capping layer508 ';
In this step; The 5th etching is a wet etching; The wet etching solutions employed is hydrofluoric acid (HF); Because the high selectivity of HF when etching silicon dioxide and lanthana and silicon dioxide and aluminium oxide, HF is corrosion oxidation lanthanum and aluminium oxide hardly, therefore can be according to the thickness of deposition first protective layer 506 ' and the thickness of second protective layer 509 '; Select higher value among both accurately to control the time of wet etching, obtain intact n type capping layer505 ' and p type capping layer508 ' through an etching.
Step 412, Fig. 5 l are the cross-sectional view of the step 412 of the range upon range of grid making method of the present invention; Shown in Fig. 5 l; Go up depositing metal layers at p type capping layer508 ' and said n type capping layer505 ', etching forms High K gate dielectric layer/metal stacking grid after the 3rd photoetching.
In this step, the 3rd photoetching is meant, on the photoresist that layer on surface of metal applies, defines gate pattern through overexposure and developing process;
In this step, be mask with the photoresist with gate pattern, etching is removed metal level, p type capping layer508 ', n type capping layer505 ', High K gate dielectric layer 304 and the interlayer gate oxide that is not covered by photoresist successively.
So far, the making step of the High K gate dielectric layer 304/ metal stacking grid of CMOS of the present invention is accomplished.
Visible by above-mentioned technical scheme; The present invention forms first silicon dioxide layer in the first high-dielectric coefficient gate medium cover surface of deposition earlier, and photoresist residual on first protective layer is removed in first ashing after etching forms first protective layer and n type high-dielectric coefficient gate medium cover layer successively above the P trap; Then remove photoresist in second ashing after forming second protective layer and p type high-dielectric coefficient gate medium cover layer above the N trap, wet etching is removed first, second protective layer then; Last depositing metal layers etching forms range upon range of grid.The present invention removes in the process of photoresist in ashing; By first, second protective layer as p type and the tectal protective layer of n type high-dielectric coefficient gate medium; The podzolic process of effectively having avoided removing photoresist has reduced the variation of threshold voltage in follow-up pyroprocess of high-dielectric coefficient gate-dielectric/metal stacking grid cmos device to p type high-dielectric coefficient gate medium cover layer and the tectal destruction of n type high-dielectric coefficient gate medium.
The above is merely preferred embodiment of the present invention, and is in order to restriction the present invention, not all within spirit of the present invention and principle, any modification of being made, is equal to replacement, improvement etc., all should be included within the scope that the present invention protects.

Claims (10)

1. range upon range of grid making method; Wafer is provided, has N trap, P trap and shallow trench isolation in the silicon substrate of said wafer and leave, make interlayer gate oxide and high-dielectric coefficient gate dielectric layer successively in the device side of said wafer; It is characterized in that this method comprises:
Deposit the first high-dielectric coefficient gate medium cover layer and first silicon dioxide layer successively at said high-dielectric coefficient gate-dielectric laminar surface;
On said first silicon dioxide layer, apply first photoresist; Above the P trap, form first photoengraving pattern after first photoetching; With first photoengraving pattern is mask said first silicon dioxide layer of first etching and the said first high-dielectric coefficient gate medium cover layer of second etching successively, forms first protective layer and n type high-dielectric coefficient gate medium cover layer respectively;
First residual on said first protective layer photoresist is removed in first ashing;
Deposit the second high-dielectric coefficient gate medium cover layer and second silicon dioxide layer successively in said wafer device side;
On said second silicon dioxide layer, apply second photoresist; Above the N trap, form second photoengraving pattern after second photoetching; With second photoengraving pattern is mask said second silicon dioxide layer of the 3rd etching and the said second high-dielectric coefficient gate medium cover layer of the 4th etching successively, forms second protective layer and p type high-dielectric coefficient gate medium cover layer respectively;
Second residual on said second protective layer photoresist is removed in second ashing;
The 5th etching is removed first protective layer and second protective layer;
Depositing metal layers on said wafer device side, etching forms high-dielectric coefficient gate dielectric layer/metal stacking grid after the 3rd photoetching.
2. the method for claim 1 is characterized in that, the said first high-dielectric coefficient gate medium cover layer is a lanthana, and the said second high-dielectric coefficient gate medium cover layer is an aluminium oxide.
3. the method for claim 1 is characterized in that, the thickness range of said deposition first silicon dioxide layer and second silicon dioxide layer is 50 to 500 dusts.
4. the method for claim 1 is characterized in that, the deposit thickness of said first silicon dioxide layer and second silicon dioxide layer equates.
5. the method for claim 1 is characterized in that, said first etching is wet etching or dry etching; Said the 3rd etching is wet etching or dry etching; Said the 5th etching is a wet etching, and used solution is hydrofluoric acid.
6. range upon range of grid making method; Wafer is provided, has N trap, P trap and shallow trench isolation in the silicon substrate of said wafer and leave, make interlayer gate oxide and high-dielectric coefficient gate dielectric layer successively in the device side of said wafer; It is characterized in that this method comprises:
Deposit the first high-dielectric coefficient gate medium cover layer and first silicon dioxide layer successively at said high-dielectric coefficient gate-dielectric laminar surface;
On said first silicon dioxide layer, apply first photoresist; Above the N trap, form first photoengraving pattern after first photoetching; With first photoengraving pattern is mask said first silicon dioxide layer of first etching and the said first high-dielectric coefficient gate medium cover layer of second etching successively, forms first protective layer and p type high-dielectric coefficient gate medium cover layer respectively;
First residual on said first protective layer photoresist is removed in first ashing;
Deposit the second high-dielectric coefficient gate medium cover layer and second silicon dioxide layer successively in said wafer device side;
On second silicon dioxide layer, apply second photoresist; Form second photoengraving pattern at the P trap after second photoetching; With second photoengraving pattern is mask said second silicon dioxide layer of the 3rd etching and the said second high-dielectric coefficient gate medium cover layer of the 4th etching successively, forms second protective layer and n type high-dielectric coefficient gate medium cover layer respectively;
Second residual on said second protective layer photoresist is removed in second ashing;
The 5th etching is removed first protective layer and second protective layer;
Depositing metal layers on said wafer device side, etching forms high-dielectric coefficient gate dielectric layer/metal stacking grid after the 3rd photoetching.
7. method as claimed in claim 2 is characterized in that, the said first high-dielectric coefficient gate medium cover layer is an aluminium oxide, and the said second high-dielectric coefficient gate medium cover layer is a lanthana.
8. method as claimed in claim 2 is characterized in that, the thickness range of said deposition first silicon dioxide layer and second silicon dioxide layer is 50 to 500 dusts.
9. method as claimed in claim 2 is characterized in that, the deposit thickness of said first silicon dioxide layer and second silicon dioxide layer equates.
10. method as claimed in claim 2 is characterized in that, said first etching is wet etching or dry etching; Said the 3rd etching is wet etching or dry etching; Said the 5th etching is a wet etching, and used solution is hydrofluoric acid.
CN2010105070642A 2010-10-14 2010-10-14 Cascaded grid production method Pending CN102446725A (en)

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