CN102437189A - Silicon nanowire device and manufacturing method thereof - Google Patents
Silicon nanowire device and manufacturing method thereof Download PDFInfo
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- CN102437189A CN102437189A CN2011103889574A CN201110388957A CN102437189A CN 102437189 A CN102437189 A CN 102437189A CN 2011103889574 A CN2011103889574 A CN 2011103889574A CN 201110388957 A CN201110388957 A CN 201110388957A CN 102437189 A CN102437189 A CN 102437189A
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- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 118
- 239000010703 silicon Substances 0.000 title claims abstract description 118
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 115
- 239000002070 nanowire Substances 0.000 title claims abstract description 112
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 229910052751 metal Inorganic materials 0.000 claims abstract description 44
- 239000002184 metal Substances 0.000 claims abstract description 44
- 238000000034 method Methods 0.000 claims abstract description 33
- 239000010410 layer Substances 0.000 claims description 48
- 239000011241 protective layer Substances 0.000 claims description 30
- 238000001259 photo etching Methods 0.000 claims description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 12
- 230000008021 deposition Effects 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- 235000012239 silicon dioxide Nutrition 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- 238000002161 passivation Methods 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical group [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 3
- 238000009740 moulding (composite fabrication) Methods 0.000 claims description 2
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- 238000001312 dry etching Methods 0.000 description 6
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- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
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- 150000003376 silicon Chemical class 0.000 description 3
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Abstract
The invention relates to a silicon nanowire device and a manufacturing method thereof. The oxide layer (40) of the silicon nanowire device is covered by the metal conductive protection layer (5), so that the oxide layer (40) can be protected from the influence of subsequent processes, and a dry release process compatible with CMOS can be used. In addition, in the dry release process, even if the side walls (41) are formed on two sides of the silicon nanowire device, charges can be uniformly distributed on the surface of the silicon nanowire device due to the conductivity of the metal conductive protection layer, so that the reduction of the affected rate can be reliably prevented.
Description
Technical field
The present invention relates to a kind of biochip and manufacturing approach thereof, particularly a kind of have the silicon nanowires device of optimizing structure and preparation method thereof.
Background technology
In recent years, be accompanied by continuous exploration and the research of people, have the material of one-dimensional nano structure,, more and more receive people's attention like silicon nanowires (SiNW, Silicon Nanowire) to field of nanometer technology.Silicon nanowires has characteristics such as significant quantum effect, super large surface to volume ratio, so in fields such as MOS device, transducers good prospects for application is arranged.
The silicon nanowires device as a kind of biochip elementary cell, just is applied to the biological detection field more and more widely.
People such as Kuan-l Chen have delivered one piece of article that exercise question is " Silicon nanowire field-effect transistor-based biosensors for biomedical diagnosis and cellular recoding investigation ", the manufacture craft of wherein having introduced the application of silicon nanowires and having proposed to make the silicon nanowires device at " nanometer magazine today (Nano Today) " the 6th phase 131-154 page or leaf in 2011.Figure 1A is the schematic top plan view of silicon nanowires device of the prior art, and Figure 1B is the A-A generalized section of Figure 1A.Shown in Figure 1A, Figure 1B; Silicon nanowires device of the prior art; Be to have the source/drain region 3 that forms silicon nanowires 4 on the polysilicon substrate 1 of silicon dioxide layer 2 and be connected respectively with silicon nanowires 4 two ends on the surface and constitute, wherein, silicon nanowires normally covers layer of oxide layer and forms on polysilicon or monocrystalline silicon surface; Its main operation principle is similar to MOSFET; Utilize oxide layer on polysilicon or the monocrystalline silicon as grid oxygen, because the biomolecule group of absorption on it all has electric charge usually, this electric charge can be similar to the potential regulating of MOSFET to silicon nanowires; And then influence the conductive characteristic of silicon nanowires, through discerning specific biomolecule group to the monitoring of this conductive characteristic.
In the silicon nanowires device making technics of prior art; After forming silicon nanowires and source/drain region on the substrate; Adopt insulating medium layer to cover silicon nanowires, so that for example on source/drain region, form metal pad and offer in the subsequent technique of contact hole the protection silicon nanowires injury-free.After making such as above-mentioned metal pad, contact hole finish, need to remove the insulating medium layer on the silicon nanowires, to discharge the silicon nanowires zone, make directly contact measured liquid of silicon nanowires.
Fig. 2 is the profile of the silicon nanowires device of the prior art before the release process.Because after the whole technology of silicon nanowires device is accomplished, carry out this release process after promptly all metal pads complete usually, this just makes release process can't get into the relevant base station of preceding road technology.This is because if use the relevant base station of preceding road technology to carry out release process, then the metal on the metal pad can bring pollution to preceding working procedure.Therefore, can't use the selection of preceding working procedure to carry out operation than very high hot phosphoric acid base station, and the new hot phosphoric acid base station of extra buying, this can increase production cost greatly.
In order not increase manufacturing cost, selected dry method release (being dry etching) in the prior art for use.Fig. 3 is the profile of the silicon nanowires device of the prior art behind the dry etching.The weak point of this silicon nanowires device is: because dry etching can't be accomplished high selectivity isotropic etching completely; So can form side wall (spacer) 41 in the side of silicon nanowires 4; When the side of silicon nanowires 4 is covered by side wall 41; This silicon nanowires 4 can't be realized effectively contacting with testing liquid, and what be left can mainly be the end face of silicon nanowires 4 with the position that testing liquid effectively contacts, but top surface area shared ratio in the total surface area of silicon nanowires is very little; Thereby effective contact area of silicon nanowires and testing liquid is reduced significantly; The area that influenced by biomolecule group also reduces thereupon, and this can make the influenced rate of silicon nanowires device reduce, and causes the sensitivity of silicon nano-device to reduce.Here, so-called influenced rate is meant, receives the surface area of the silicon that biomolecule group influences and the ratio of the total surface area of this silicon.
Summary of the invention
The present invention proposes in view of the above problems, and its purpose is, a kind of silicon nanowires device and manufacturing approach thereof that can prevent reliably that influenced rate from reducing is provided.
To achieve these goals; The present invention provides a kind of silicon nanowires device; It comprises silicon nanowires and the source/drain region that is formed on the substrate, and said silicon nanowires is connected with said source/drain region, and the end face of said silicon nanowires and side are covered by the metallic conduction protective layer.
Preferably, said silicon nanowires device comprises two source/drain regions, lays respectively at the both sides of said silicon nanowires.
The present invention also provides the manufacture method of said silicon nanowires device, comprises the steps:
On substrate, form silicon nanowires and source/drain region, said silicon nanowires links to each other with said source/drain region;
On silicon nanowires, form the metallic conduction protective layer, this metallic conduction protective layer covers the end face and the side of said silicon nanowires;
On source/drain region, form metal pad successively and be communicated to the contact hole of metal pad;
Remove the material on the metallic conduction protective layer, exposing metal conductive protecting layer, above-mentioned substance are in the step that forms metal pad and contact hole, to be formed on the metallic conduction protective layer.
Preferably, the said step that on substrate, forms silicon nanowires and source/drain region comprises:
Adopt thermal oxidation process, on substrate, form silicon dioxide layer;
Deposit spathic silicon layer and carry out light dope on silicon dioxide layer;
Said polysilicon layer is adopted photoetching, etching, form silicon nanowires and source/drain region;
Adopt thermal oxidation process, form oxide-film on the surface at silicon nanowires and source/drain region.
Preferably, after adopting photoetching, etching, forming the step in silicon nanowires and source/drain region, also comprise: adopt photoetching, ion implantation technology that heavy doping is carried out in source/drain region.
Preferably, in the said step that on silicon nanowires, forms the metallic conduction protective layer, adopt deposition process, deposition layer of metal layer covers silicon nanowires and source/drain region, and employing photoetching, etching sheet metal are to form above-mentioned metallic conduction protective layer.
Preferably; The said step that on source/drain region, forms metal pad and contact hole successively comprises: deposit first oxide layer; Adopt photoetching, etching to form through hole, in through hole, fill metal and form metal level, adopt photoetching, etching to form metal pad; Deposition second oxide layer and silicon nitride passivation on metal pad adopt photoetching, etching to form contact hole.
Preferably, in the step of said exposing metal conductive protecting layer, remove silicon nitride passivation, second oxide layer and first oxide layer of metallic conduction protective layer top.
Preferably, the material of said metallic conduction protective layer is TiN or TaN.
The oxide layer of silicon nanowires of the present invention (grid oxygen) is covered by the layer of metal conductive protecting layer, thus can protect the influence of oxide layer protect against subsequent operation, and can adopt and cmos compatible dry method release process.And in the dry method release process, even form side wall in the side of silicon nanowires device, also the conductivity because of the metallic conduction protective layer can make electric charge be evenly distributed in the surface of silicon nanowires device, thereby can prevent reliably that influenced rate from reducing.
Description of drawings
Figure 1A is the schematic top plan view of silicon nanowires device of the prior art.
Figure 1B is the A-A generalized section of Figure 1A.
Fig. 2 is the profile of the silicon nanowires device of the prior art before the release process.
Fig. 3 is the profile of the silicon nanowires device of the prior art behind the release process.
Fig. 4 is the process chart of silicon nanowires device of the present invention.
Fig. 5 is the profile that is used to represent silicon nanowires device technology step of the present invention.
Fig. 6 is the profile that is used to represent silicon nanowires device technology step of the present invention.
Fig. 7 is the profile that is used to represent silicon nanowires device technology step of the present invention.
Embodiment
Below, with reference to accompanying drawing, the present invention is carried out detailed explanation.
A lot of details have been set forth so that make much of the present invention in the explanation below; But the present invention can implement much to be different from the alternate manner that is described below; Those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention does not receive the restriction of following disclosed specific embodiment.
Secondly; The present invention utilizes sketch map to be elaborated; But when embodiments of the invention were elaborated, for ease of explanation, the profile of expression device architecture can be disobeyed general ratio and done local the amplification; And said sketch map is instance, not can be considered the qualification to the scope of the present invention's protection.The three dimensions size that in actual fabrication, should comprise in addition, length, width and the degree of depth.In the present invention, the profile of silicon nanowires device only drawn in a simplified manner part silicon nanowires and a source/drain region, those skilled in the art can do similar popularization under the situation of intension of the present invention.
Fig. 4 is the process chart of silicon nanowires device of the present invention, and Fig. 5～7 are respectively the profiles that is used to represent silicon nanowires device technology step of the present invention.Below, with reference to Fig. 4 and Fig. 5～7, silicon nanowires device manufacture method of the present invention is elaborated.
At first, on substrate, form silicon nanowires and source/drain region (step 101).
As shown in Figure 5, on substrate 1, adopt thermal oxidation technology to generate silicon dioxide layer 2, deposit spathic silicon layer and carry out light dope on this silicon dioxide layer 2 adopts the reactive ion etching polysilicon layer with formation source/drain region 3 and silicon nanowires 4.Preferably, can also may further comprise the steps after the employing reactive ion etching forms source/drain region 3 and silicon nanowires 4 steps in step 101: adopt photoetching, ion implantation technology, heavy doping is carried out in source/drain region 3, thus the contact resistance in reduction source/drain region 3.Then, thermal oxide growth layer oxide film 40 on source/drain region 3 and silicon nanowires 4, said oxide-film 40 is a silicon dioxide.
Next; Adopt physical gas-phase deposition; Deposition layer of metal layer 5 covers silicon nanowires 4 and source/drain region 3 (with reference to Fig. 5), and adopts photoetching, etching sheet metal to be formed for covering the end face of silicon nanowires 4 and the metallic conduction protective layer 5 (step 102) of side.5 pairs of silicon nanowires of said metallic conduction protective layer have protective effect, the destruction of oxide layer (grid oxygen) the protect against subsequent technology of protection silicon nanowires device.Said metallic conduction protective layer 5 can adopt TiN or TaN etc. to have the metal of conductivity.
Then, adopt standard CMOS process, on source/drain region 3, form metal pad 7 successively and be connected to the contact hole (step 103) of metal pad 7.
As shown in Figure 6, deposition first oxide layer 61 on metallic conduction protective layer 5 adopts photoetching, etching to form through hole in the source/drain region 3 of said device; In through hole, fill metal and form metal level; Adopt photoetching, etching sheet metal to form metal pad 7, said metal pad 7 is an aluminium welding pad, deposition second oxide layer 62 and silicon nitride passivation 63 on metal pad 7; Adopt photoetching, etching to form contact hole, said oxide layer 61,62 is a silica.
Said silicon nanowires device is after metal pad 7 and contact hole completion; Be coated with oxide layer 61,62 and silicon nitride passivation 63 on the metallic conduction protective layer 5 of covering silicon nanowires 4; Need discharge these layers, thereby in step 104, adopt dry etching; Remove silicon nitride passivation 63, the oxide layer 61,62 of silicon nanowires 4 tops, thereby expose said metallic conduction protective layer 5.
Profile after silicon nanowires device of the present invention discharges, as shown in Figure 7.When the silicon nanowires device is carried out dry etching, because dry etching can't be accomplished high selectivity isotropic etching completely, so can form side wall 41 in the side of metallic conduction protective layer 5.
When utilizing silicon nanowires device of the present invention to measure; Though can't realize effectively contacting with the side of metallic conduction protective layer 5 because of there being side wall 41 testing liquids; But the biomolecule group that has electric charge in the testing liquid can directly contact with the end face of metallic conduction protective layer 5 at least; Because metallic conduction protective layer 5 has conductivity, electric charge can be evenly distributed on the surface of silicon nanowires device, thereby can avoid influenced rate to reduce.
The above is merely preferred embodiment of the present invention, and all equalizations of being done according to claim scope of the present invention change and modify, and all should belong to the covering scope of claim of the present invention.
Claims (10)
1. a silicon nanowires device comprises the silicon nanowires and the source/drain region that are formed on the substrate, and said silicon nanowires is connected with said source/drain region, it is characterized in that, the end face of said silicon nanowires and side are covered by the metallic conduction protective layer.
2. silicon nanowires device according to claim 1 is characterized in that, said silicon nanowires device comprises two source/drain regions, lays respectively at the both sides of said silicon nanowires.
3. silicon nanowires device according to claim 1 and 2 is characterized in that, the material of said metallic conduction protective layer is TiN or TaN.
4. the manufacture method of a silicon nanowires device may further comprise the steps:
On substrate, form silicon nanowires and source/drain region, said silicon nanowires links to each other with said source/drain region;
On silicon nanowires, form the metallic conduction protective layer, this metallic conduction protective layer covers the end face and the side of said silicon nanowires;
On source/drain region, form metal pad successively and be communicated to the contact hole of metal pad;
Remove the material on the metallic conduction protective layer, exposing metal conductive protecting layer, above-mentioned substance are in the step that forms metal pad and contact hole, to be formed on the metallic conduction protective layer.
5. the manufacture method of silicon nanowires device according to claim 4 is characterized in that, the said step that on substrate, forms silicon nanowires and source/drain region comprises:
Adopt thermal oxidation process, on substrate, form silicon dioxide layer;
Deposit spathic silicon layer and carry out light dope on silicon dioxide layer;
Said polysilicon layer is adopted photoetching, etching, form silicon nanowires and source/drain region;
Adopt thermal oxidation process, form oxide-film on the surface at silicon nanowires and source/drain region.
6. the manufacture method of silicon nanowires device according to claim 5 is characterized in that, after adopting photoetching, etching, forming the step in silicon nanowires and source/drain region, also comprises: adopt photoetching, ion implantation technology that heavy doping is carried out in source/drain region.
7. the manufacture method of silicon nanowires device according to claim 4; It is characterized in that; In the said step that on silicon nanowires, forms the metallic conduction protective layer; Adopt physical gas-phase deposition, deposition layer of metal layer covers silicon nanowires and source/drain region, and adopts photoetching, etching sheet metal to form above-mentioned metallic conduction protective layer.
8. the manufacture method of silicon nanowires device according to claim 4; It is characterized in that the said step that on source/drain region, forms metal pad and contact hole successively comprises: deposit first oxide layer, adopt photoetching, etching to form through hole; In through hole, fill metal and form metal level; Adopt photoetching, etching to form metal pad, deposition second oxide layer and silicon nitride passivation on metal pad adopt photoetching, etching to form contact hole.
9. the manufacture method of silicon nanowires device according to claim 8 is characterized in that, in the step of said exposing metal conductive protecting layer, removes silicon nitride passivation, second oxide layer and first oxide layer of said metallic conduction protective layer top.
10. according to the manufacture method of each described silicon nanowires device in the claim 4～9, it is characterized in that the material of said metallic conduction protective layer is TiN or TaN.
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| CN2011103889574A CN102437189A (en) | 2011-11-30 | 2011-11-30 | Silicon nanowire device and manufacturing method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103018429A (en) * | 2012-11-01 | 2013-04-03 | 上海集成电路研发中心有限公司 | Structure used for biologic detection chip of silicon nanowire and manufacturing method of structure |
| WO2014075373A1 (en) * | 2012-11-14 | 2014-05-22 | 上海集成电路研发中心有限公司 | Silicon nanowire chip for simultaneously detecting mirnas and protein markers, detecting method and application thereof |
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| US20050136585A1 (en) * | 2003-12-23 | 2005-06-23 | Chau Robert S. | Method of fabricating semiconductor devices with replacement, coaxial gate structure |
| US20070178477A1 (en) * | 2002-01-16 | 2007-08-02 | Nanomix, Inc. | Nanotube sensor devices for DNA detection |
| CN101060135A (en) * | 2007-06-05 | 2007-10-24 | 北京大学 | A double silicon nanowire wrap gate field-effect transistor and its manufacture method |
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2011
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070178477A1 (en) * | 2002-01-16 | 2007-08-02 | Nanomix, Inc. | Nanotube sensor devices for DNA detection |
| US20050136585A1 (en) * | 2003-12-23 | 2005-06-23 | Chau Robert S. | Method of fabricating semiconductor devices with replacement, coaxial gate structure |
| CN101060135A (en) * | 2007-06-05 | 2007-10-24 | 北京大学 | A double silicon nanowire wrap gate field-effect transistor and its manufacture method |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103018429A (en) * | 2012-11-01 | 2013-04-03 | 上海集成电路研发中心有限公司 | Structure used for biologic detection chip of silicon nanowire and manufacturing method of structure |
| WO2014067185A1 (en) * | 2012-11-01 | 2014-05-08 | 上海集成电路研发中心有限公司 | Structure for silicon nanowire chip for biological detection and manufacturing method therefor |
| CN103018429B (en) * | 2012-11-01 | 2017-03-15 | 上海集成电路研发中心有限公司 | A kind of structure and its manufacture method for silicon nano-wire biological detection chip |
| WO2014075373A1 (en) * | 2012-11-14 | 2014-05-22 | 上海集成电路研发中心有限公司 | Silicon nanowire chip for simultaneously detecting mirnas and protein markers, detecting method and application thereof |
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Application publication date: 20120502 |