CN109427908A - Three-dimensional silicon nanowire array field effect transistor, biosensor and preparation method - Google Patents
Three-dimensional silicon nanowire array field effect transistor, biosensor and preparation method Download PDFInfo
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 127
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 127
- 239000010703 silicon Substances 0.000 title claims abstract description 127
- 230000005669 field effect Effects 0.000 title claims abstract description 67
- 238000002360 preparation method Methods 0.000 title claims abstract description 46
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
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- G01N27/00—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means
- G01N27/26—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating electrochemical variables; by using electrolysis or electrophoresis
- G01N27/403—Cells and electrode assemblies
- G01N27/414—Ion-sensitive or chemical field-effect transistors, i.e. ISFETS or CHEMFETS
- G01N27/4146—Ion-sensitive or chemical field-effect transistors, i.e. ISFETS or CHEMFETS involving nanosized elements, e.g. nanotubes, nanowires
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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Abstract
The present invention provides a kind of three-dimensional silicon nanowire array field effect transistor, biosensor and preparation method, transistor preparation includes: offer substrate, and in substrate surface deposition by first material layer and the alternate laminated material bed of material of second material layer, second material layer is material layer；Form the figure of channel region and the source region and drain region that are connected with its both ends；Etching stack material layer, until exposing substrate；Corrode above structure, obtains three-dimensional silicon nanowire array channel, source region and drain region；In silicon nanowires channel surface metallization medium layer；In production source electrode, drain electrode and gate electrode in the substrate of source region, the top surface in drain region and nanowire channel periphery.Through the above scheme, biosensor of the invention has ring grid structure, 360 ° of circulating type inductions can be achieved, silicon nanowires field effect transistor uses three-dimensional stacked array structure, device size can be reduced, the step of realizing the promotion of signal-to-noise ratio, omitting source and drain doping, simple process are suitable for batch production.
Description
Technical field
The invention belongs to semiconductor device processing technology fields, more particularly to a kind of three-dimensional silicon nanowire array field-effect
Transistor, biosensor and preparation method.
Background technique
The highly sensitive detection of biomolecule is in disease detection, clinical medicine, environmental monitoring, Pharmaceutical Analysis, field of food
Etc. having wide practical use, nano material has the property completely different with block materials, unique electricity, magnetics, light
It learns, thermal property, provides completely new approach for the detection of biomolecule.
Silicon nanowires is as a kind of novel One, Dimensional Semiconductor Nano Materials, due to the specific surface area of its superelevation, high stable
The characteristics of property, repeatable electrology characteristic and easy modified biological group in surface, become the important generation of biochemical sensor of new generation
Table.Semiconductor field effect transistor sensor based on silicon nanostructure has great specific surface area, channel carriers pair
Channel surface distribution of charges is extremely sensitive, has many advantages, such as high sensitivity, high specific, quick response, is conducive to biochemical molecular and passes
Sense.
Currently, the preparation method of silicon nanowires can be mainly divided into two kinds, one is " from bottom to top " (bottom-up)
Method, this method processing efficiency is relatively low, repeatability is poor, inconvenient, be difficult to position, the purity of silicon nanowires and
The uniformity of scale is also unable to get good guarantee in process, therefore, is not met by the requirement of large-scale integrated manufacture；
Another kind is " from top to bottom " method of (top-down), this method be in the material layer prepared by photoetching,
The modes such as etching and deposition, produce required nanometer line graph, and manufacture craft accuracy is higher, nano wire scale is convenient for control
System, device accurate positioning and production efficiency are relatively high.
However, the silicon nanowires fieldtron for biochemical sensor mostly uses cmos compatible " from top to bottom " method
Preparation, but there are still some problems at present: and 1) source electrode of silicon nanowires fieldtron, drain electrode need to adulterate, complex process；2)
The non-hanging structure of silicon nanowires make device can only using surface induction target molecule, signal strength and minimum detection limit by
Limitation；3) silicon nanowire array extension is only carried out in the two-dimensional direction, is claimed to minimum device size.
Therefore it provides a kind of silicon nanowire array structure and based on the biosensor of silicon nanowire array to solve on
The problem of stating is necessary.
Summary of the invention
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of three-dimensional silicon nanowire array fields
Effect transistor, biosensor and preparation method are needed for solving silicon nanowires fieldtron source and drain in the prior art
Doping and sensor can only surface induction target molecule, can only two-dimensional directional extension and signal strength etc. it is limited the problems such as.
In order to achieve the above objects and other related objects, the present invention provides a kind of three-dimensional silicon nanowire array field effect transistor
The preparation method of pipe, includes the following steps:
1) substrate is provided, and in substrate surface deposition by least one layer of first material layer and at least one layer of second material
The laminated material bed of material that the bed of material is alternately superimposed on, the bottom that the laminated material bed of material is in contact with the substrate are first material
Layer, the second material layer are material layer；
2) channel region and respectively two with the channel region are formed in the laminated material layer surface using photoetching process
The figure of the source region and drain region that are connected is held, and the channel region includes several trench cells areas being intervally arranged；
3) using the figure as the laminated material bed of material described in mask etching, until exposing the substrate；
4) corrosion step 3) obtained structure, the first material layer in the channel region is removed, three-dimensional silica is obtained and receives
Nanowire arrays channel, source region and drain region, the three-dimensional silicon nanowire array channel includes several by the second material layer shape
At three-dimensional silica nanowire channel unit, the source region and the drain region include by least one layer of first structure layer and at least
The laminated construction that one layer of second structure sheaf is alternately superimposed on；
5) surface of Yu Suoshu three-dimensional silica nanowire channel unit deposits one layer of dielectric layer；
6) Yu Suoshu source region, the top surface in the drain region and the three-dimensional silicon nanowire array channel periphery is described
Source electrode, drain electrode and gate electrode are made in substrate, respectively to obtain three-dimensional silicon nanowire array field effect transistor.
It as a preferred solution of the present invention, further include to less than the source region and institute between step 5) and step 6)
The step of top surface and lateral wall for stating drain region form metal silicide layer.
As a preferred solution of the present invention, the step of forming the metal silicide layer specifically:
A) one layer of metal layer is deposited to the top surface and lateral wall less than the source region and the drain region；
B) it anneals to the obtained structure of step a), to form the metal silicide layer.
As a preferred solution of the present invention, in step 1), the substrate is SOI substrate, the SOI substrate from lower and
On successively include bottom silicon, buried oxide layer and top layer silicon.
As a preferred solution of the present invention, in step 1), the first material layer be germanium silicon material layer, described second
Material layer is silicon material layer；In step 4), the first structure layer is germanium silicon layer, and second structure sheaf is silicon layer.
It as a preferred solution of the present invention, further include the progress p-type doping in the first material layer in step 1)
Or the step of n-type doping.
As a preferred solution of the present invention, in step 4), corrosion step 3) corrosive liquid used by obtained structure
For the mixed solution of hydrofluoric acid, hydrogen peroxide and acetic acid.
As a preferred solution of the present invention, in step 5), the dielectric layer of deposition is high-K dielectric layer.
The present invention also provides a kind of preparation methods of biosensor, include the following steps:
1) the three-dimensional silicon nanowire array field-effect being prepared using preparation method described in any of the above-described scheme is brilliant
Body pipe；
2) it is carried out in the surface of the three-dimensional silica nanowire channel unit of the three-dimensional silicon nanowire array field effect transistor
Modification, to form one layer of active film to end up with active group；
3) Yu Suoshu active film surface forms capture probe, wherein the capture probe passes through with the active group
Chemical bond combines, and the capture probe is modified in the three-dimensional silica nanowire channel cell surface.
As a preferred solution of the present invention, in step 2), the active group is amino, carboxyl, hydroxyl and aldehyde radical
One or both of or more combination.
The present invention also provides a kind of three-dimensional silicon nanowire array field effect transistor, three-dimensional silicon nanowire array field effects
Answering transistor is the structure being prepared using method provided by the present invention, comprising:
Substrate；
Source region and drain region are located at the substrate surface, include by least one layer of first structure layer and at least one layer of the
The laminated construction that two structure sheafs are alternately superimposed on, and the bottom that the laminated construction is in contact with the substrate is the first structure
Layer, second structure sheaf are containing silicon structural layer；
Three-dimensional silicon nanowire array channel, the three-dimensional silica nanowire channel unit including the arrangement of several parallel intervals, institute
One end of three-dimensional silica nanowire channel unit is stated to be connected with second structure sheaf in the laminated construction of the source region, it is another
One end is connected with second structure sheaf in the laminated construction in the drain region；
Dielectric layer, positioned at the surface of the three-dimensional silica nanowire channel unit；
Source electrode, drain electrode and gate electrode, the source electrode are located at the top surface of the source region, the drain electrode position
Top surface in the drain region, the gate electrode are located in the substrate of the three-dimensional silicon nanowire array channel periphery.
As a preferred solution of the present invention, further include metal silicide layer, be located at least in the source region and the source
Between electrode and between the drain region and the drain electrode.
As a preferred solution of the present invention, the first structure layer is germanium silicon layer, and second structure sheaf is silicon layer.
As a preferred solution of the present invention, the material of the germanium silicon layer is Si1-xGex, wherein the range of Ge content x
It is 0.15~0.6.
As a preferred solution of the present invention, the germanium silicon layer is the germanium silicon layer of p-type doping or n-type doping.
The present invention also provides a kind of biosensors, comprising:
Three-dimensional silicon nanowire array field effect transistor as described in above-mentioned any one scheme；
Active film, positioned at the three-dimensional silica nanowire channel unit of the three-dimensional silicon nanowire array field effect transistor
Surface, and the active film is ended up with active group；
Capture probe, is located at the active film surface, and the capture probe passes through chemical bond phase with the active group
In conjunction with.
As described above, present invention three-dimensional silicon nanowire array field effect transistor, biosensor and respective preparation side
Method has the advantages that
1) biosensor of the invention is based on three-dimensional silicon nanowire array FET device, has ring grid knot
Structure is different from the surface sensing of traditional structure, it can be achieved that 360 ° of circulating type inductions, are more applicable for highly sensitive biochemical molecular
Detection；
2) silicon nanowires field effect transistor of the invention uses three-dimensional stacked array structure, can reduce device size,
By the superposition of signal, so that the promotion of signal-to-noise ratio can be realized；
3) the step of production of silicon nanowires field effect transistor of the invention can be omitted source and drain doping, technical process letter
List, cost is relatively low, is suitable for batch production；
4) three-dimensional silica nanowire channel surface of the invention uses dielectric layer of high dielectric constant material, enhances the stabilization of device
Property simultaneously improves device to the responding ability of biochemical molecular.
Detailed description of the invention
Fig. 1 is shown as the process of each step of three-dimensional silicon nanowire array field effect transistor preparation process provided by the invention
Figure.
Fig. 2 is shown as the structural representation of the step 1) of three-dimensional silicon nanowire array field effect transistor preparation of the invention
Figure.
Fig. 3 is shown as the structural representation of the step 1) of three-dimensional silicon nanowire array field effect transistor preparation of the invention
Figure.
Fig. 4 is shown as the structural representation of the step 2) of three-dimensional silicon nanowire array field effect transistor preparation of the invention
Figure.
Fig. 5 is shown as the structural representation of the step 2) of three-dimensional silicon nanowire array field effect transistor preparation of the invention
Figure.
Fig. 6 is shown as the structural representation of the step 3) of three-dimensional silicon nanowire array field effect transistor preparation of the invention
Figure.
Fig. 7 is shown as the structural representation of the step 3) of three-dimensional silicon nanowire array field effect transistor preparation of the invention
Figure.
Fig. 8 is shown as the structural representation of the step 4) of three-dimensional silicon nanowire array field effect transistor preparation of the invention
Figure.
Fig. 9 is shown as the structural representation of the step 4) of three-dimensional silicon nanowire array field effect transistor preparation of the invention
Figure.
Figure 10 is shown as the structural representation of the step 5) of three-dimensional silicon nanowire array field effect transistor preparation of the invention
Figure.
Figure 11 is shown as the structural representation of the step 5) of three-dimensional silicon nanowire array field effect transistor preparation of the invention
Figure.
Figure 12 is shown as the structural representation of the step 6) of three-dimensional silicon nanowire array field effect transistor preparation of the invention
Figure.
Figure 13 is shown as the structural representation of the step 6) of three-dimensional silicon nanowire array field effect transistor preparation of the invention
Figure.
Figure 14 is shown as the structural schematic diagram of the biosensor of the offer of the embodiment of the present invention two.
Component label instructions
11 substrates
111 top layer silicons
112 buried oxide layers
113 top layer silicons
The 21 laminated material bed of materials
211 first material layers
212 second material layers
31 figures
311 channel region figures
3111 trench cells area figures
312 source regions or drain region figure
41 laminated construction
411 first structure layers
412 second structure sheafs
511 three-dimensional silicon nanowire array channels
5111 three-dimensional silica nanowire channel units
512 dielectric layers
61 metal silicide layers
71,72 source electrodes or drain electrode
73 gate electrodes
S1~S6 step
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from
Various modifications or alterations are carried out under spirit of the invention.
Fig. 1 is please referred to Figure 14.It should be noted that diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, though only show in diagram with related component in the present invention rather than package count when according to actual implementation
Mesh, shape and size are drawn, when actual implementation form, quantity and the ratio of each component can arbitrarily change for one kind, and its
Assembly layout form may also be increasingly complex.
Embodiment one
The present invention provides a kind of preparation method of three-dimensional silicon nanowire array field effect transistor, includes the following steps:
1) substrate is provided, and in substrate surface deposition by least one layer of first material layer and at least one layer of second material
The laminated material bed of material that the bed of material is alternately superimposed on, the bottom that the laminated material bed of material is in contact with the substrate are first material
Layer, the second material layer are material layer；
2) channel region and respectively two with the channel region are formed in the laminated material layer surface using photoetching process
The figure of the source region and drain region that are connected is held, and the channel region includes several trench cells areas being intervally arranged；
3) using the figure as the laminated material bed of material described in mask etching, until exposing the substrate；
4) corrosion step 3) obtained structure, the first material layer in the channel region is removed, three-dimensional silica is obtained and receives
Nanowire arrays channel, source region and drain region, the three-dimensional silicon nanowire array channel includes several by the second material layer shape
At three-dimensional silica nanowire channel unit, the source region and the drain region include by least one layer of first structure layer and at least
The laminated construction that one layer of second structure sheaf is alternately superimposed on；
5) surface of Yu Suoshu three-dimensional silica nanowire channel unit deposits one layer of dielectric layer；
6) Yu Suoshu source region, the top surface in the drain region and the three-dimensional silicon nanowire array channel periphery is described
Source electrode, drain electrode and gate electrode are made in substrate, respectively to obtain three-dimensional silicon nanowire array field effect transistor.
The preparation of three-dimensional silicon nanowire array field effect transistor of the invention is specifically introduced below in conjunction with attached drawing.
Shown in S1 and Fig. 2 and Fig. 3 as shown in figure 1, step 1) is carried out, provides a substrate 11, and in 11 surface of substrate
The laminated material bed of material 21 that deposition is alternately superimposed on by least one layer of first material layer 211 and at least one layer of second material layer 212, it is described
The bottom that the laminated material bed of material 21 is in contact with the substrate 11 be the first material layer 211, the second material layer 212 be containing
Silicon material layer；
As an example, the substrate 11 is SOI substrate in step 1), the SOI substrate successively includes bottom from bottom to top
Silicon 113, buried oxide layer 112 and top layer silicon 111.
As an example, the first material layer is germanium silicon material layer in step 1), the second material layer is silicon materials
Layer.
Specifically, the substrate 11 of the invention is preferably SOI substrate layer, for providing mechanical support, and the bottom
The crystal orientation of silicon 113 is preferably (100) orientation, the top layer silicon 111 in the SOI substrate layer with a thickness of 20~40nm, for into
One step guarantees that the effect of subsequent layers of material is selected as 25nm in the present embodiment.
As an example, further including the step for carrying out p-type doping or n-type doping in the first material layer 211 in step 1)
Suddenly.
Specifically, in the present embodiment, further include to the first material layer, such as germanium silicon material layer, the process being doped,
To which source and drain doping step is omitted in the production of the field effect transistor, technical process is simple, and cost is relatively low, and it is raw to be suitable for batch
It produces, it is preferable that be doped in the growth course of the germanium silicon material layer, it is, of course, also possible to raw in the germanium silicon material layer
Ion implantation doping is carried out after the completion of long, is not particularly limited herein.Its doping type can be p-type or N-type, according to actual demand
Depending on, it is selected as boron doping in the present embodiment, doping concentration is greater than 1e19cm-3, 6e is selected as in the present embodiment19cm-3, institute
State germanium silicon material layer 211 with a thickness of 20~40nm, be selected as 25nm in the present embodiment, the silicon material layer 212 with a thickness of
15~20nm is selected as 18nm in the present embodiment.
In addition, the germanium silicon material layer of the laminated material bed of material 21 and the stacked structure of silicon material layer are preferably 3~6 layer heaps
It is folded, it certainly, in other embodiments, can also arbitrarily be set according to actual demand, such as can be 2~100 layers.Wherein, described
Germanium silicon material layer in the laminated material bed of material is in contact with the substrate, and then is corroded in subsequent corrosion process, thus
The formation for guaranteeing three-dimensional silica nanowire channel, can be germanium silicon material layer or silicon material for the top layer of the laminated material bed of material 21
The bed of material.Certainly, if there is other are easy to realize on wafer, and corrode selection than high other materials with silicon materials, it can also be with
Instead of the germanium silicon material layer in the application, it is not limited to the germanium silicon material layer of the application.
Shown in S2 and Fig. 4 and Fig. 5 as shown in figure 1, step 2) is carried out, using photoetching process in the laminated material bed of material 21
Surface forms the figure of channel region 311 and the source region and drain region that are connected respectively with the both ends of the channel region 311, and described
Channel region 311 includes several trench cells areas 3111 being intervally arranged；
Specifically, defining the position of subsequent channel region to be formed and source region and drain region using photoresist layer, such as
Using e-beam lithography, wherein the figure 311 of the channel region includes several trench cells areas 3111, it is preferable that institute
State the arrangement of 3111 parallel interval of trench cells area, and the shortest distance between the source region and the drain region, i.e., the described channel
The length in area is set as 10~200nm, in the present embodiment, can be 50nm, 100nm, 120nm or 180nm, it is as subsequent
The length of the three-dimensional silica nanowire channel of formation.
Shown in S3 and Fig. 6 and Fig. 7 as shown in figure 1, step 3) is carried out, is lamination described in mask etching with the figure 31
Material layer 21, until exposing the substrate；
Specifically, by the graph copying in the laminated material bed of material, and remove the photoresist layer.
Shown in S4 and Fig. 8 and Fig. 9 as shown in figure 1, step 4), corrosion step 3 are carried out) obtained structure, described in removal
311 first material layer in channel region, obtains three-dimensional silicon nanowire array channel 511, source region and drain region, the three-dimensional silica
Nano-wire array channel 511 includes several three-dimensional silica nanowire channel units 5111 formed by the second material layer 212,
The source region and the drain region include being replaced by least one layer of first structure layer 411 and at least one layer of second structure sheaf 412
Stacked laminated construction 41；
As an example, the first structure layer 411 is germanium silicon layer in step 4), second structure sheaf 412 is silicon layer.
Specifically, the first structure layer is formed by structure of the first material layer after corroding, second structure
Layer is formed by structure of the second material layer after corroding.By the corrosion of the step, the germanium silicon material in channel region is eliminated
The bed of material, so that correspondence obtains hanging three-dimensional silicon nanowire array channel 511, source region and drain region, it is preferable that three-dimensional silicon nanowires
Array channel 511 includes the array-like three-dimensional silica nanowire channel unit 5111 of several parallel intervals arrangement.The corrosion work
Skill can corrode using using reactive ion etching (RIE) and anisotropic wet.
As an example, in step 4), corrosion step 3) corrosive liquid used by obtained structure be hydrofluoric acid, hydrogen peroxide with
And the mixed solution of acetic acid.
Specifically, being corroded using above-mentioned mixed liquor to it, wherein the hydrofluoric acid is preferably the hydrogen that concentration is 1%
Fluoric acid, in addition, the ratio of each ingredient of the mixed liquor are as follows: HF:H2O2: CH3COOH=1:2:3.
Shown in S5 and Figure 10 and Figure 11 as shown in figure 1, step 5), Yu Suoshu three-dimensional silica nanowire channel unit are carried out
5111 surface deposits one layer of dielectric layer 512；
As an example, the dielectric layer 512 of deposition is high-K dielectric layer in step 5).
Specifically, one layer of dielectric layer 512 is formed on the surface of the silicon nanowires trench cells of above structure, it can be using original
The technologies such as sublayer deposition (ALD) are deposited, it is preferable that the dielectric layer is high-K dielectric layer or high dielectric constant
Layer, in the present invention, K represent dielectric constant, and high K represents dielectric constant greater than 3.9, and high-K dielectric layer is mainly formed at silicon nanometer
The surface of line, effect are enhancing liquid grid to the ability of regulation and control of nano wire, enhance the stability of device and improve device to biochemistry
The responding ability of molecule.In addition, the dielectric layer 512 with a thickness of 5~20nm, material includes but is not limited to aluminium oxide, oxygen
Change one of hafnium alternatively, the stacked structure that aluminium oxide and hafnium oxide are constituted, it is of course also possible to be other high-K dielectric layers.
Shown in S6 and Figure 12 and Figure 13 as shown in figure 1, carry out step 6), Yu Suoshu source region, the drain region top table
Source electrode 71, drain electrode 72 are made respectively in the substrate 11 of face and three-dimensional 511 periphery of silicon nanowire array channel
And gate electrode 73, to obtain three-dimensional silicon nanowire array field effect transistor.
Specifically, electrode preparation is finally completed, to form complete field effect transistor, wherein the electrode material can
Think any electrode material well known within the skill of those ordinarily skilled, such as gold material.The gate electrode 73 is located at the three-dimensional
Near nano-wire array channel, wherein grid is to be regulated and controled by solution to nanowire channel, silicon nanometer of the invention
Line is hanging structure, is surrounded by liquid, and ring grid structure is formed, and the gate electrode is used for the electrode of the ring grid.
As an example, further including to the top table for being less than the source region and the drain region 41 between step 5) and step 6)
The step of face and lateral wall form metal silicide layer 61.
As an example, the step of forming metal silicide layer 61 specifically:
A) one layer of metal layer is deposited to the top surface and lateral wall less than the source region and the drain region 41；
B) it anneals to the obtained structure of step a), to form the metal silicide layer 61.
Specifically, further include the steps that preparing metal silicide 61 in the present embodiment, be formed in source region and source electrode it
Between, between drain region and drain electrode, furthermore it is also possible to be formed simultaneously on the side wall in the source region Yu the drain region, silicide
Effect is to increase electric conductivity, reduces contact resistance.Specifically, physical vapour deposition (PVD) can such as be used by being initially formed metal layer
(PVD) method deposits, then the mode annealed forms metal silicide layer, wherein annealing temperature is 500~700 DEG C, this reality
It applies in example, is selected as to form nickel metal layer, annealing temperature is 650 DEG C, to form nickel silicide.Certainly, the material of the metal layer
Material can also be zirconium, titanium etc., with a thickness of 10~20nm, preferably 16nm.
As shown in figure 12, the present embodiment one also provides a kind of three-dimensional silicon nanowire array field effect transistor, wherein described
Three-dimensional silicon nanowire array field effect transistor is the structure obtained using the preparation method of the present embodiment, comprising:
Substrate 11；
Source region and drain region are located at 11 surface of substrate, include by least one layer of first structure layer 411 and at least one
The laminated construction 41 that the second structure sheaf 412 of layer is alternately superimposed on, and the bottom that the laminated construction 41 is in contact with the substrate 11
For the first structure layer 411, second structure sheaf is containing silicon structural layer；
Three-dimensional silicon nanowire array channel 511, the three-dimensional silica nanowire channel unit including the arrangement of several parallel intervals
5111, second structure sheaf in one end of the three-dimensional silica nanowire channel unit 5111 and the laminated construction of the source region
It is connected, the other end is connected with second structure sheaf in the laminated construction in the drain region；
Dielectric layer 512, positioned at the surface of the three-dimensional silica nanowire channel unit 5111；
Source electrode 71, drain electrode 72 and gate electrode 73, the source electrode 71 is located at the top surface of the source region, described
Drain electrode 72 is located at the top surface in the drain region, and the gate electrode 73 is located at the three-dimensional silicon nanowire array channel periphery
In the substrate.
Specifically, the substrate 11 is preferably SOI substrate layer, for providing mechanical support, and the crystalline substance of the bottom silicon 113
Be orientated to preferably (100), the top layer silicon 111 in the SOI substrate layer with a thickness of 20~40nm, after being further ensured that
The effect of continuous material layer is selected as 25nm in the present embodiment.
Specifically, the length of the three-dimensional silica nanowire channel unit is set as 10~200nm, in the present embodiment,
It can be 50nm, 100nm, 120nm or 180nm.
As an example, further include metal silicide layer 61, it is located at least between the source region and the source electrode and institute
It states between drain region and the drain electrode.
Specifically, further include the steps that preparing metal silicide 61 in the present embodiment, be formed in source region and source electrode it
Between, between drain region and drain electrode, furthermore it is also possible to be formed simultaneously on the side wall in the source region Yu the drain region, silicide
Effect is to increase electric conductivity, reduces contact resistance.Specifically, physical vapour deposition (PVD) can such as be used by being initially formed metal layer
(PVD) method deposits, then the mode annealed forms metal silicide layer, wherein annealing temperature is 500~700 DEG C, this reality
It applies in example, is selected as to form nickel metal layer, annealing temperature is 650 DEG C, to form nickel silicide.Certainly, the material of the metal layer
Material can also be zirconium, titanium etc., with a thickness of 10~20nm, preferably 16nm.
As an example, the first structure layer 411 is germanium silicon layer, second structure sheaf 412 is silicon layer.
As an example, the material of the germanium silicon layer is Si1-xGex, wherein the range of Ge content x is 0.15~0.6.
As an example, the germanium silicon layer is the germanium silicon layer of p-type doping or n-type doping.
Specifically, the material of the germanium silicon layer is Si1-xGex, wherein the range of Ge content x is 0.15~0.6, preferably
0.3.In the present embodiment, the germanium silicon material layer is doped, the source-drain area as the field effect transistor.Its doping type
It can be p-type or N-type, depending on actual demand, be selected as boron doping in the present embodiment, doping concentration is greater than 1e19cm-3,
6e is selected as in the present embodiment19cm-3, the germanium silicon layer with a thickness of 20~40nm, be selected as 25nm in the present embodiment, it is described
Silicon layer with a thickness of 15~20nm, be selected as 18nm in the present embodiment.In addition, the germanium silicon layer and silicon layer of the laminated construction 41
Stacked structure is preferably that 3~6 layer heaps are folded, certainly, in other embodiments, can also arbitrarily set according to actual demand, such as may be used
To be set as 2~100 layers.
Embodiment two
As shown in Figure 12 and 13, the present embodiment two provides a kind of preparation method of biosensor, wherein the biology passes
The preparation method of sensor includes the method for the three-dimensional silicon nanowire array field effect transistor of preparation in embodiment one, is specifically included
Following steps:
1) the three-dimensional silicon nanowire array being prepared using the preparation method as described in any one of embodiment one scheme
Field effect transistor；
2) it is carried out in the surface of the three-dimensional silica nanowire channel unit of the three-dimensional silicon nanowire array field effect transistor
Modification, to form one layer of active film to end up with active group；
3) Yu Suoshu active film surface forms capture probe, wherein the capture probe passes through with the active group
Chemical bond combines, and the capture probe is modified in the three-dimensional silica nanowire channel cell surface.
Specifically, the present invention also provides a kind of bio-sensings based on three-dimensional silicon nanowire array slot field-effect transistor
Device, wherein in the present embodiment, be selected as and modified using reagent on the surface of nanowire channel unit, to be self-assembly of
One layer of active film to be ended up with active group.
As an example, the active group is the group of one or both of amino, carboxyl, hydroxyl and aldehyde radical or more
It closes.
It should be noted that being electrically connected, after the completion of the preparation of biosensor device architecture to realize sensor
Effect, the present invention in, it is described three-dimensional silicon nanowire array channel be hanging structure, can with multiple surface induction target molecules,
The problem of surface induction target molecule can only be used in the prior art by solving, and signal strength and minimum detection limit are restricted,
Meanwhile the extension of silicon nanowire array can be carried out on three-dimensional, it is more suitable for the requirement of device size reduction.
The present embodiment two also provides a kind of biosensor, wherein the biosensor is the system using the present embodiment
The biosensor that Preparation Method is prepared, comprising:
Three-dimensional silicon nanowire array field effect transistor as described in any one in embodiment one；
Active film, positioned at the three-dimensional silica nanowire channel unit of the three-dimensional silicon nanowire array field effect transistor
Surface, and the active film is ended up with active group；
Capture probe, is located at the active film surface, and the capture probe passes through chemical bond phase with the active group
In conjunction with.
In conclusion the present invention provides a kind of three-dimensional silicon nanowire array field effect transistor, specific steps include: to provide
One substrate, and be alternately superimposed in substrate surface deposition by least one layer of first material layer and at least one layer of second material layer
The laminated material bed of material, the bottom that the laminated material bed of material is in contact with the substrate are the first material layer, second material
Layer is material layer；Using photoetching process in the laminated material layer surface formed channel region and respectively with the channel region
The figure of source region and drain region that is connected of both ends, and the channel region includes several trench cells areas being intervally arranged；With
The figure is the laminated material bed of material described in mask etching, until exposing the substrate；The structure that corrosion previous step obtains, goes
Except the first material layer in the channel region, three-dimensional silicon nanowire array channel, source region and drain region, the three-dimensional silica are obtained
Nano-wire array channel includes several three-dimensional silica nanowire channel units formed by the second material layer, the source region and
The drain region includes the laminated construction being alternately superimposed on by least one layer of first structure layer and at least one layer of second structure sheaf；In
The surface of the three-dimensional silica nanowire channel unit deposits one layer of dielectric layer；In the source region, the drain region top surface with
And source electrode, drain electrode and gate electrode are made respectively in the substrate of the three-dimensional silicon nanowire array channel periphery, with
Obtain three-dimensional silicon nanowire array field effect transistor.Through the above technical solutions, 1) biosensor of the invention is based on three
Silicon nanowire array FET device is tieed up, there is ring grid structure, is different from the surface sensing of traditional structure, it can be real
Existing 360 ° of circulating types induction is more applicable for highly sensitive biochemical molecular detection；2) silicon nanowires field effect transistor of the invention
Pipe uses three-dimensional stacked array structure, can reduce device size, by the superposition of signal, so that mentioning for signal-to-noise ratio can be realized
It rises；3) the step of production of silicon nanowires field effect transistor of the invention can be omitted source and drain doping, technical process is simple, at
This is lower, is suitable for batch production；4) three-dimensional silica nanowire channel surface of the invention uses dielectric layer of high dielectric constant material, increases
The stability of strong device simultaneously improves device to the responding ability of biochemical molecular.So the present invention effectively overcomes in the prior art
Various shortcoming and have high industrial utilization value.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should be covered by the claims of the present invention.
Claims (16)
1. a kind of preparation method of three-dimensional silicon nanowire array field effect transistor, which comprises the steps of:
1) substrate is provided, and in substrate surface deposition by least one layer of first material layer and at least one layer of second material layer
The laminated material bed of material being alternately superimposed on, the bottom that the laminated material bed of material is in contact with the substrate are the first material layer, institute
Stating second material layer is material layer；
2) using photoetching process in the laminated material layer surface formed channel region and respectively with the both ends phase of the channel region
The source region of connection and the figure in drain region, and the channel region includes several trench cells areas being intervally arranged；
3) using the figure as the laminated material bed of material described in mask etching, until exposing the substrate；
4) corrosion step 3) obtained structure, the first material layer in the channel region is removed, three-dimensional silicon nanowires is obtained
Array channel, source region and drain region, the three-dimensional silicon nanowire array channel include several and are formed by the second material layer
Three-dimensional silica nanowire channel unit, the source region and the drain region include by least one layer of first structure layer and at least one layer
The laminated construction that second structure sheaf is alternately superimposed on；
5) surface of Yu Suoshu three-dimensional silica nanowire channel unit deposits one layer of dielectric layer；
6) substrate of Yu Suoshu source region, the top surface in the drain region and the three-dimensional silicon nanowire array channel periphery
It is upper to make source electrode, drain electrode and gate electrode respectively, to obtain three-dimensional silicon nanowire array field effect transistor.
2. the preparation method of three-dimensional silicon nanowire array field effect transistor according to claim 1, which is characterized in that step
It is rapid 5) between step 6), further include forming metallic silicon to the top surface and lateral wall less than the source region and the drain region
The step of compound layer.
3. the preparation method of three-dimensional silicon nanowire array field effect transistor according to claim 2, which is characterized in that shape
The step of at the metal silicide layer specifically:
A) one layer of metal layer is deposited to the top surface and lateral wall less than the source region and the drain region；
B) it anneals to the obtained structure of step a), to form the metal silicide layer.
4. the preparation method of three-dimensional silicon nanowire array field effect transistor according to claim 1, which is characterized in that step
It is rapid 1) in, the substrate be SOI substrate, the SOI substrate from bottom to top successively include bottom silicon, buried oxide layer and top layer silicon.
5. the preparation method of this column field effect transistor of three-dimensional silicon nanowires according to claim 1, which is characterized in that step
It is rapid 1) in, the first material layer be germanium silicon material layer, the second material layer be silicon material layer；In step 4), described first
Structure sheaf is germanium silicon layer, and second structure sheaf is silicon layer.
6. the preparation method of three-dimensional silicon nanowire array field effect transistor according to claim 5, which is characterized in that step
It is rapid 1) in, further include the steps that carrying out p-type doping or n-type doping in the first material layer.
7. the preparation method of three-dimensional silicon nanowire array field effect transistor according to claim 1, which is characterized in that step
It is rapid 4) in, corrosion step 3) corrosive liquid used by obtained structure be hydrofluoric acid, hydrogen peroxide and acetic acid mixed solution.
8. the preparation method of three-dimensional silicon nanowire array field effect transistor according to any one of claims 1 to 7,
It is characterized in that, in step 5), the dielectric layer of deposition is high-K dielectric layer.
9. a kind of preparation method of biosensor, which comprises the steps of:
1) the three-dimensional silicon nanowire array field effect being prepared using such as preparation method according to any one of claims 1 to 8
Answer transistor；
2) it is modified in the surface of the three-dimensional silica nanowire channel unit of the three-dimensional silicon nanowire array field effect transistor,
To form one layer of active film to end up with active group；
3) Yu Suoshu active film surface forms capture probe, wherein the capture probe and the active group pass through chemistry
Key combines, and the capture probe is modified in the three-dimensional silica nanowire channel cell surface.
10. the preparation method of biosensor according to claim 9, which is characterized in that in step 2), the active group
Group is the combination of one or both of amino, carboxyl, hydroxyl and aldehyde radical or more.
11. a kind of three-dimensional silicon nanowire array field effect transistor characterized by comprising
Substrate；
Source region and drain region are located at the substrate surface, include by least one layer of first structure layer and at least one layer of second layer
The laminated construction being alternately superimposed on, and the bottom that the laminated construction is in contact with the substrate is the first structure layer, it is described
Second structure sheaf is containing silicon structural layer；
Three-dimensional silicon nanowire array channel, the three-dimensional silica nanowire channel unit including the arrangement of several parallel intervals, described three
One end of dimension silicon nanowires trench cells is connected with second structure sheaf in the laminated construction of the source region, the other end
It is connected with second structure sheaf in the laminated construction in the drain region；
Dielectric layer, positioned at the surface of the three-dimensional silica nanowire channel unit；
Source electrode, drain electrode and gate electrode, the source electrode are located at the top surface of the source region, and the drain electrode is located at institute
The top surface in drain region is stated, the gate electrode is located in the substrate of the three-dimensional silicon nanowire array channel periphery.
12. three-dimensional silicon nanowire array field effect transistor according to claim 11, which is characterized in that further include metal
Silicide layer is located at least between the source region and the source electrode and between the drain region and the drain electrode.
13. three-dimensional silicon nanowire array field effect transistor, feature described in any one of 1 or 12 according to claim 1
It is, the first structure layer is germanium silicon layer, and second structure sheaf is silicon layer.
14. three-dimensional silicon nanowire array field effect transistor according to claim 13, which is characterized in that the germanium silicon layer
Material be Si1-xGex, wherein the range of Ge content x is 0.15~0.6.
15. three-dimensional silicon nanowire array field effect transistor according to claim 13, which is characterized in that the germanium silicon layer
For p-type doping or the germanium silicon layer of n-type doping.
16. a kind of biosensor characterized by comprising
Three-dimensional silicon nanowire array field effect transistor as described in any one of claim 11~15；
Active film, positioned at the table of the three-dimensional silica nanowire channel unit of the three-dimensional silicon nanowire array field effect transistor
Face, and the active film is ended up with active group；
Capture probe, is located at the active film surface, and the capture probe is combined with the active group by chemical bond.
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