CN102437109A - Semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor structure and manufacturing method thereof Download PDFInfo
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- CN102437109A CN102437109A CN2011103913164A CN201110391316A CN102437109A CN 102437109 A CN102437109 A CN 102437109A CN 2011103913164 A CN2011103913164 A CN 2011103913164A CN 201110391316 A CN201110391316 A CN 201110391316A CN 102437109 A CN102437109 A CN 102437109A
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Abstract
The invention discloses a semiconductor structure and a manufacturing method thereof. The manufacturing method comprises the following steps of: providing a semiconductor substrate and a line layer, wherein the semiconductor substrate has a front surface and a back surface opposite to each other, and the line layer is configured on the front side of the semiconductor substrate and is provided with at least one connection pad positioned on the front side; forming at least one through hole for connecting the front side and the back side of the semiconductor substrate, wherein the through hole exposes part of the connection pad; and forming a conductive adhesive to fully fill the through hole and cover the back side of the semiconductor substrate so as to form at least one conductive through hole positioned in the through hole and a conductive layer positioned on the back side, wherein the conductive through hole is electrically connected with the connection pad and the conductive layer.
Description
Technical field
The present invention relates to a kind of semiconductor structure and preparation method thereof, and particularly relate to a kind of semiconductor structure and preparation method thereof with common contact point structure.
Background technology
In the making of integrated circuit, chip (chip) is to accomplish via wafer (wafer) making, formation integrated circuit and cut crystal steps such as (wafer sawing).After the inner integrated circuit of wafer is accomplished, can line layer be disposed on the surface of wafer, and see through the mode of the perforation at the surface that forms a plurality of connecting wafers and the back side, come to expose respectively a plurality of connection pads of line layer.Yet because these connection pads are separated from one another, therefore finally cutting formed chip by wafer can't the directly direct and external circuit electric connection via these connection pads that these perforations exposed.
Summary of the invention
The present invention provides a kind of semiconductor structure and preparation method thereof, and its processing step is simple, can reduce process time and production cost.
The present invention proposes a kind of semiconductor structure, and it comprises the semiconductor-based end, line layer, a plurality of conductive through hole and conductive layer.The semiconductor-based end, have front and the back side and at least one perforation that is connected positive and the back side.Line layer is disposed on the front at the semiconductor-based end, and has a plurality of connection pads, and wherein these perforations expose these connection pads of part respectively.These conductive through holes are disposed at respectively in these perforations.Conductive layer is disposed on the back side at the semiconductor-based end, and covers the back side, and wherein these conductive through holes electrically connect these connection pads and conductive layer respectively.
The present invention also proposes a kind of manufacture method of semiconductor structure, and it may further comprise the steps.The semiconductor-based end and line layer are provided.The semiconductor-based end, have the front and the back side, and line layer is disposed on the front at the semiconductor-based end.Line layer has at least one connection pad that is positioned on the front.Form the perforation that at least one connects the front and the back side at the semiconductor-based end, wherein perforation exposes the part connection pad.Form conducting resinl filling up perforation and to cover the back side at the semiconductor-based end, at least onely lay respectively at the conductive through hole in the perforation and be positioned at the conductive layer on the back side and constitute, wherein conductive through hole electrically connects connection pad and conductive layer.
Based on above-mentioned, the present invention sees through the conductive layer that the mode of screen painting is come to form simultaneously these conductive through holes and connected these conductive through holes, wherein these connection pads of these conductive through holes difference connection line layers.Therefore, semiconductor structure of the present invention can have the design of common contact point structure (being conductive layer and these conductive through holes), and that the manufacture method of semiconductor structure of the present invention can have a processing step is simple and can reduce the advantage of process time and production cost.
For letting the above-mentioned feature and advantage of the present invention can be more obviously understandable, hereinafter is special lifts embodiment, and conjunction with figs. elaborates as follows.
Description of drawings
Figure 1A to Fig. 1 G is the generalized section of manufacture method of a kind of semiconductor structure of embodiments of the invention.
Fig. 2 A to Fig. 2 B is the generalized section of local step of manufacture method of a kind of semiconductor structure of another embodiment of the present invention.
Description of reference numerals
100: semiconductor structure
110: the semiconductor-based end
112: the front
114: the back side
116: perforation
120: line layer
122: connection pad
130,130a, 130b: conducting resinl
140: conductive through hole
145: conductive layer
150: web plate
160: cutter
C: be total to contact point structure
Embodiment
Figure 1A to Fig. 1 G is the generalized section of manufacture method of a kind of semiconductor structure of embodiments of the invention.The manufacture method that accordings to the semiconductor structure of present embodiment; At first, please refer to Figure 1A, the semiconductor-based end 110 and line layer 120 are provided; The wherein semiconductor-based end 110 have respect to one another positive 112 with the back side 114, and line layer 120 is disposed on the front 112 at the semiconductor-based end 110.
What need explanation is; In the present embodiment; Line layer 120 is by existing semiconductor integrated circuit technique made, and line layer 120 can be by at least one dielectric layer, at least one line layer and at least one electronic component, and wherein electronic component for example is active element (active device), passive component (passive device) or micro-electro-mechanical systems element (Microelectromechanical system device; MEMS device), do not limit at this.
Then; Please refer to Figure 1B; Utilize dry-etching mode or laser cutting mode to form the perforation 116 (only schematically illustrating three among Figure 1B) at least one front that connects the semiconductor-based end 110 112 and the back side 114; Wherein these perforations 116 expose at least one connection pad 122 (only schematically illustrating three among Figure 1B) of line layer 120 respectively, and these connection pads 122 are to be positioned on the front 112 at the semiconductor-based end 110.
Then, carry out the screen painting step, wherein the screen painting step may further comprise the steps.At first, please refer to Fig. 1 C, place half tone (stencil) 150 on the back side 114 at the semiconductor-based end 110, wherein half tone 150 exposes the part back side 114 at the semiconductor-based end 110.Then, please refer to Fig. 1 D, make conducting resinl 130 fill up these perforations 116 and cover not the back side 114 at the semiconductor-based end 110 that is covered by half tone 150.Afterwards; Please refer to Fig. 1 E; Remove half tone 150 to expose the part back side 114 at the semiconductor-based end 110; And conducting resinl 130 carried out the vacuum bakeout step, removing the solvent in the conducting resinl 130, lay respectively at the conductive through hole 140 in these perforations 116 and be positioned at the conductive layer 145 on the back side 114 at the semiconductor-based end 110 and form at least one.
Particularly, in the present embodiment, these conductive through holes 140 connect these connection pads 122 of the line layer 120 that these perforations 116 are exposed respectively, and conductive layer 145 connects these conductive through holes 140.In other words, these connection pads 122 can see through these conductive through holes 140 and structural and be electrically connected to conductive layer 145.Moreover the thickness of conductive layer 145 is identical in fact with the thickness of half tone 150 (please refer to Fig. 1 C).That is to say, can select the thickness of web plate 150 according to the thickness of required conductive layer 145.
At last, please be simultaneously with reference to figure 1F and Fig. 1 G, the part back side 114 that is exposed out along the semiconductor-based end 110 sees through cutter 160 cutting semiconductor substrates 110 and line layer 120, and forms semiconductor structure 100 (only schematically illustrating among Fig. 1 E) at least.In this, be that the position with half tone 150 (please refer to Fig. 1 C) defines the position that cutter 160 cuts, but not as limit.So far, accomplished the making of semiconductor structure 100.
What deserves to be mentioned is that the screen painting step that Fig. 1 C, Fig. 1 D and Fig. 1 E are illustrated only is as the usefulness that illustrates.In other embodiment, also can adopt the mode of coating to form conducting resinl 130a.In detail; Please refer to Fig. 2 A; Can after the step of Figure 1B, promptly form after the perforation 116 at these fronts that connect the semiconductor-based end 110 112 and the back side 114, see through the back side 112 that the mode that is coated with makes conducting resinl 130a fill up these perforations 116 and covers this semiconductor-based end 110.Then, please refer to Fig. 2 B, conducting resinl 130a is carried out the thinning program,, have conducting resinl 130b than minimal thickness and form to reduce the thickness of conducting resinl 130a.At last, again conducting resinl 130b is carried out the vacuum bakeout step of Fig. 1 E, removing the solvent in the conducting resinl 130b, lay respectively at the conductive through hole 140 in these perforations 116 and be positioned at the conductive layer 145 on the back side 114 at the semiconductor-based end 110 and form these.Above-mentioned Fig. 2 A to Fig. 2 B employing application step forms conducting resinl 130a, and this still belongs to the adoptable technical scheme of the present invention, does not break away from the scope of institute of the present invention desire protection.
Structurally, please again with reference to figure 1G, the semiconductor structure 100 of present embodiment comprises the semiconductor-based end 110, line layer 120, these conductive through holes 140 and conductive layer 145.The semiconductor-based end 110 have respect to one another positive 112 be connected with the back side 114 and these positive 112 with the perforation 116 at the back side 114.Line layer 120 is disposed on the front 112 at the semiconductor-based end 110, and has these connection pads 122, and wherein these perforations 116 expose these connection pads 122 of part of line layer 120 respectively.These conductive through holes 140 are disposed at respectively in these perforations 116.Conductive layer 145 is disposed on the back side 114 at the semiconductor-based end 110; And cover the back side 114; Wherein these conductive through holes 140 are distinguished these connection pads 122 of connection line layers 120; And conductive layer 145 connects these conductive through holes 140, and conductive layer 145 all is to be made up of 130 of conducting resinls with these conductive through holes 140.In other words, conductive layer 145 is integrally formed in fact with these conductive through holes 140.In addition, conductive layer 145 constitutes contact point structure C altogether with these conductive through holes 140.
Come to form simultaneously these conductive through holes 140 and connect the conductive layer 145 of these conductive through holes 140 because present embodiment is the mode that sees through screen painting, thus the manufacture method of the semiconductor structure 100 of present embodiment to have a processing step simple and can reduce the advantage of process time and production cost.Moreover, structural and be electrically connected to conductive layer 145 because these connection pads 122 of line layer 120 can see through these conductive through holes 140.Anticipate promptly, these connection pads 122 are connected to same contact (being conductive layer 145) via these conductive through holes 140 respectively.Therefore; Design and external circuit (not illustrating) that formed semiconductor structure 100 can see through this common contact point structure C (being conductive layer 145 and these conductive through holes 140) electrically connect; Also or, can this conductive layer 145 be regarded as ground plane, can effectively expand the range of application of semiconductor structure 100.
In sum, the present invention sees through the conductive layer that the mode of screen painting is come to form simultaneously these conductive through holes and connected these conductive through holes, wherein these connection pads of these conductive through holes difference connection line layers.Therefore, semiconductor structure of the present invention can have the design of common contact point structure (being conductive layer and these conductive through holes), and that the manufacture method of semiconductor structure of the present invention can have a processing step is simple and can reduce the advantage of process time and production cost.
Though the present invention discloses as above with embodiment; Right its is not in order to qualification the present invention, and those of ordinary skill in any affiliated technical field is not breaking away from the spirit and scope of the present invention; When can doing a little change and retouching, so protection scope of the present invention defines and is as the criterion when looking claim.
Claims (13)
1. the manufacture method of a semiconductor structure comprises:
The semiconductor-based end and line layer are provided, and this semiconductor-based end, have the front and the back side, and this line layer is disposed on this front at this semiconductor-based end, and wherein this line layer has at least one connection pad that is positioned on this front;
Form this front at least one semiconductor-based end and the perforation at this back side, wherein this perforation exposes connection pad; And
Form conducting resinl filling up this perforation and to cover this back side at this semiconductor-based end, at least onely be positioned at the conductive through hole of this perforation and be positioned at the conductive layer on this back side and constitute, wherein this conductive through hole this connection pad of electric connection and this conductive layer.
2. the manufacture method of semiconductor structure as claimed in claim 1, the method that wherein forms this conducting resinl comprises the screen painting step.
3. the manufacture method of semiconductor structure as claimed in claim 2, wherein this screen painting step comprises:
Place half tone on this back side at this semiconductor-based end, wherein this half tone exposes this back side of part; And
Fill up this perforation and cover not this back side with this conducting resinl by this half tone covered.
4. the manufacture method of semiconductor structure as claimed in claim 3 also comprises:
This conducting resinl is carried out the vacuum bakeout step, removing the solvent in this conducting resinl, and form this conductive through hole and this conductive layer.
5. the manufacture method of semiconductor structure as claimed in claim 4 also comprises:
After carrying out this vacuum bakeout step, the part that is exposed out along this semiconductor-based end this this semiconductor-based end of cutting, back side and this line layer, and form semiconductor structure at least.
6. the manufacture method of semiconductor structure as claimed in claim 1, the method that wherein forms this conducting resinl comprises rubbing method.
7. the manufacture method of semiconductor structure as claimed in claim 6 also comprises:
This conducting resinl is carried out the vacuum bakeout step, removing the solvent in this conducting resinl, and form this conductive through hole and this conductive layer.
8. the manufacture method of semiconductor structure as claimed in claim 7 also comprises:
Before carrying out this vacuum bakeout step, this conducting resinl is carried out the thinning program, to reduce the thickness of this conducting resinl.
9. the manufacture method of semiconductor structure as claimed in claim 1; Wherein this at least one connection pad comprises a plurality of connection pads; And this at least one perforation comprises a plurality of perforations, and at least one conductive through hole comprises a plurality of conductive through holes, and these a plurality of conductive through holes and the common contact point structure of this conductive layer formation.
10. semiconductor structure comprises:
The semiconductor-based end, have front and the back side and at least one perforation that is connected this front and this back side;
Line layer is disposed on this front at this semiconductor-based end, and has a plurality of connection pads, and wherein these a plurality of perforations expose these a plurality of connection pads of part respectively;
A plurality of conductive through holes are disposed at respectively in these a plurality of perforations; And
Conductive layer is disposed on this back side at this semiconductor-based end, and covers this back side, and wherein these a plurality of conductive through holes are electrically connected at these a plurality of connection pads and this conductive layer respectively.
11. semiconductor structure as claimed in claim 10, wherein this conductive layer is integrally formed with these a plurality of conductive through holes.
12. semiconductor structure as claimed in claim 10, wherein this conductive layer is formed by same conducting resinl with these a plurality of conductive through holes.
13. semiconductor structure as claimed in claim 10, wherein these a plurality of conductive through holes and this conductive layer constitute contact point structure altogether.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011103913164A CN102437109A (en) | 2011-11-30 | 2011-11-30 | Semiconductor structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011103913164A CN102437109A (en) | 2011-11-30 | 2011-11-30 | Semiconductor structure and manufacturing method thereof |
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| CN102437109A true CN102437109A (en) | 2012-05-02 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2011103913164A Pending CN102437109A (en) | 2011-11-30 | 2011-11-30 | Semiconductor structure and manufacturing method thereof |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2737548B2 (en) * | 1992-06-24 | 1998-04-08 | 日本電気株式会社 | Manufacturing method of multilayer printed wiring board |
| CN201383900Y (en) * | 2009-02-18 | 2010-01-13 | 王定锋 | Blind hole type circuit board |
| CN102157462A (en) * | 2010-01-21 | 2011-08-17 | 精材科技股份有限公司 | Chip package and fabrication method thereof |
| TW201140750A (en) * | 2010-05-06 | 2011-11-16 | Mos Art Pack Corp | Semiconductor structure and manufacturing method thereof |
-
2011
- 2011-11-30 CN CN2011103913164A patent/CN102437109A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2737548B2 (en) * | 1992-06-24 | 1998-04-08 | 日本電気株式会社 | Manufacturing method of multilayer printed wiring board |
| CN201383900Y (en) * | 2009-02-18 | 2010-01-13 | 王定锋 | Blind hole type circuit board |
| CN102157462A (en) * | 2010-01-21 | 2011-08-17 | 精材科技股份有限公司 | Chip package and fabrication method thereof |
| TW201140750A (en) * | 2010-05-06 | 2011-11-16 | Mos Art Pack Corp | Semiconductor structure and manufacturing method thereof |
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Application publication date: 20120502 |