CN102437086A - Manufacturing method of mechanical uniaxial strain GeOI (germanium-on-insulator) wafer based on SiN buried insulating layer - Google Patents
Manufacturing method of mechanical uniaxial strain GeOI (germanium-on-insulator) wafer based on SiN buried insulating layer Download PDFInfo
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Abstract
The invention discloses a manufacturing method of a mechanical uniaxial strain GeOI (germanium-on-insulator) wafer based on an SiN buried insulating layer, which comprises the following steps: 1) putting a GeOI wafer on a cambered bending table, wherein the top layer (Ge layer surface) of the GeOI wafer faces up or down; 2) respectively horizontally putting two cylindrical stainless steel pressure bars on both ends of the GeOI wafer, wherein the two cylindrical stainless steel pressure bars are respectively 1cm away from the edge of the GeOI wafer; 3) slowly rotating a screw cap which connects the pressure bars, so that the GeOI wafer is gradually bent along the cambered table until the GeOI wafer is completely laminated on the cambered table; 4) putting the cambered bending table carrying the GeOI wafer in an annealing furnace, and carrying out annealing; 5) after the annealing finishes, slowly cooling to room temperature, and taking out the cambered bending table carrying the GeOI wafer; and 6) rotating the screw cap which connects the pressure bars, and slowly elevating the pressure bars until the bent GeOI wafer restores to the original state. The invention has the advantages of 1) simple manufacturing technique, 2) fewer manufacturing devices, 3) wide annealing temperature range, 4) high strain effect, 5) favorable thermal properties and 6) low manufacturing cost.
Description
Technical field
The invention belongs to microelectronics technology, relate to the semi-conducting material manufacturing technology.Uniaxial strain GeOI (Germanium On Insulater on a kind of specifically manufacturing SiN (silicon nitride) enterree; Germanium on the insulating barrier) new method of wafer; Can significantly strengthen the electron mobility and the hole mobility of GeOI wafer, improve the electric property and the optical property of GeOI device and integrated circuit.
Background technology
The electronics of semiconductor Ge and hole mobility are respectively 2.8 times and 4.2 times of Si, and its hole mobility is the highest in all semiconductors.Si is similar with strain, and the carrier mobility of strain Ge also has bigger lifting, and the hole mobility of buried channel strain Ge can improve 6-8 doubly.Therefore, Ge and strain Ge will be the best channel material of 16 nanometers and following technology Si based CMOS devices and integrated circuit.Ge still is a utmost point excellent photoelectric material, has very widely at detector (visible light is to near-infrared), modulator, fiber waveguide, optical transmitting set, solar cell etc. and uses.
Because energy gap has only 0.67eV, the greatest weakness of Ge device and circuit is that the electric leakage of substrate is bigger.And GeOI develops for the solution substrate leakage currents just, be widely used in the manufacturing of semiconductor device and integrated circuit at present.
In conjunction with the strain GeOI of strain Ge and GeOI advantage for novel ultrahigh speed, low-power consumption, radioresistance, high integration silicon-based devices and the chip of research and development a kind of new solution is provided, there is important application prospects aspects such as, system level chip integrated at photoelectricity.
The enterree of GeOI wafer is SiO normally
2(silicon dioxide), its thermal conductivity is merely one of percentage of silicon, hindered GeOI in high temperature, application aspect high-power; Its dielectric constant is merely 3.9, is prone to cause the signal transmission to lose, and has also hindered the application of GeOI in high density, high power integrated circuit.And replace SiO with SiN
2GeOI have better insulating properties and thermal diffusivity, be widely used in high temperature, big power consumption, the high power integrated circuit.
Traditional strain GeOI is based on the twin shaft compressive strain of SOI wafer; Promptly at GeOI (Silicon On Insulater; Silicon on the insulating barrier) direct growth strain Ge on the wafer; Or earlier on the GeOI wafer SiGe layer of growth Ge content gradually variational make empty substrate, the required strain Ge layer of epitaxial growth on this SiGe layer again.The major defect of tradition strain GeOI is that dislocation density is high, can only to be that twin shaft compressive strain, mobility promote not high, the empty substrate of SiGe has increased hot expense and cost of manufacture, the empty substrate of SiGe have had a strong impact on device and circuit heat radiation, strain Ge layer critical thickness receive that the Ge component limits, the hole mobility lifting under the High-Field can be degenerated etc.
C.Himcinschi has proposed the manufacturing technology of uniaxial strain GeOI wafer in 2007, referring to [1] C.Himcinschi., I.Radu; F.Muster, R.SiNgh, M.Reiche; M.Petzold, U.Go ¨ sele, S.H.Christiansen; Uniaxially strained silicon by wafer bonding and layer transfer, Solid-State electronics, 51 (2007) 226-230; [2] C.Himcinschi; M.Reiche; R.Scholz; S.H.Chri stiansen; And U.
Compressive uniaxially strained silicon on insulator by prestrained wafer bonding and layer transferAPPLIeD, PHYSICS LeTTeRS 90,231909 (2007).Technological principle and step that this is technological are as depicted in figs. 1 and 2, and the manufacturing process steps of its single shaft tensile strain GeOI is described below:
1. earlier with 4 inches Si sheet 1 thermal oxidations, again this oxidation sheet 1 is injected H
+(hydrogen ion).
2. will annotate H
+Oxidation sheet 1 be placed on the arc-shaped bend platform,, fit tightly its bending through outer depression bar with the arc table top; Subsequently 3 inches Si sheets 2 are placed on 4 inches crooked notes H along the same flex direction
+On the oxidation sheet 1, with its bending, and annotate H through interior depression bar
+Oxidation sheet 1 fits tightly;
3. crooked platform is placed in the annealing furnace, annealed 15 hours down at 200 ℃.
4. take off crooked and two Si wafers of bonding from crooked platform, be reentered in the annealing furnace,, accomplish smart peeling, and finally form uniaxial strain GeOI wafer 500 ℃ of annealing 1 hour down.
This technological major defect is: 1) processing step is complicated: this method must experience thermal oxidation, H
+Ion injects, peels off requisite main technique and correlation step thereof such as annealing.2) flexure temperature is limited: owing to be to close and crooked annealing at the smart peeling line unit that advances, annotated H
+The restriction of exfoliation temperature, its crooked annealing temperature can not be higher than 300 ℃, otherwise will in crooked annealing process, peel off, and makes the Si sheet broken.3) fabrication cycle is long: extra thermal oxidation, H
+Ion injects, peels off the time that processing step such as annealing has increased its making.4) rate of finished products is low: this method is to carry out mechanical bend and bonding with two overlapping silicon wafer, and under case of bending, carries out high temperature again and peel off, and silicon wafer is easy to fragmentation.
Summary of the invention
The objective of the invention is to overcome the deficiency of above-mentioned prior art; The manufacture method that a kind of machinery based on the SiN enterree causes uniaxial strain GeOI wafer is proposed; With the cost of manufacture that reduces strain GeOI wafer, heat dispersion, insulation property and the integrated level that improves strain GeOI device and integrated circuit, satisfy microelectronics technology, particularly ultrahigh speed, low-power consumption, anti-irradiation and high power device and integrated circuit demand to strain GeOI wafer.Adopt following technical scheme:
A kind of machinery based on the SiN enterree causes the manufacture method of uniaxial strain GeOI wafer, may further comprise the steps: 1) GeOI wafer top layer Ge aspect is placed on the arc-shaped bend platform up or down; 2) two cylindrical stainless steel depression bars lie in a horizontal plane in GeOI wafer two ends respectively, apart from GeOI crystal round fringes 1cm; 3) slow turn connects the nut of depression bar, makes the GeOI wafer crooked gradually along the arc table top, the complete and arc table top applying until the GeOI wafer; 4) the arc-shaped bend platform that is loaded with the GeOI wafer is placed in the annealing furnace anneals, and annealing temperature can be selected arbitrarily in 250 ℃ to 900 ℃ scopes.For example, can anneal 10 hours down, also can anneal 2.5 hours down at 900 ℃ at 250 ℃; 5) annealing slowly is cooled to room temperature after finishing, and takes out the arc-shaped bend platform that is loaded with the GeOI sheet; 6) turn connects the nut of depression bar, depression bar is slowly promoted, until the reinstatement of the GeOI of bending wafer.Being loaded with temperature that the crooked platform of GeOI wafer anneals minimum in annealing furnace is 250 ℃, can surpass its yield strength to guarantee the deformation of SiN enterree in this process in the GeOI wafer, the generation plastic deformation; The highest annealing temperature is 900 ℃, near the fusing point of Ge.But the highest annealing temperature must not be higher than the deformation temperature of mechanical bend platform.
Described manufacture method, the radius of curvature of described arc-shaped bend platform can change from 1.2m to 0.4m continuously, the uniaxial strain GeOI wafer of the differently strained amount of its respective production.
Described manufacture method, the annealing process of said step 4) is: annealed 10 hours down at 250 ℃; Perhaps annealed 6 hours down at 400 ℃; Perhaps annealed 2.5 hours down at 900 ℃.
Described manufacture method, said GeOI wafer are 3 inches, 4 inches, 5 inches, 6 inches, 8 inches GeOI wafer.
Know-why of the present invention:
The GeOI sheet top layer Si Ge of finished product towards on be placed on and carry out mechanical bend, thermal annealing then on the circular arc table top.According to material plastoelasticity principle; Receive the effect of long-time crooked thermomechanical treatment; The SiN layer and the top layer Si Ge layer that are in GeOI wafer neutral surface top will be along bending direction generation uniaxial tensile deformations, and its lattice constant will become greatly, and so-called single shaft tensile strain promptly takes place.Simultaneously, in GeOI wafer internal reservoir certain elastic potential energy.After annealing finished to remove mechanical external force, under this elastic potential energy effect, resilience can take place in the GeOI wafer, promptly is returned to ortho states by case of bending, and was as shown in Figure 3.
But top layer Si Ge layer has kept a certain amount of tensile strain in the GeOI wafer that restores.This is because when crooked thermal anneal process, has set suitable annealing temperature and time, guarantees that the mechanical external force that is applied can surpass the yield strength of SiN but less than the yield strength of Si substrate, make SiN generation plastic deformation, and the Si substrate is elastic deformation all the time.The SiN enterree of plastic deformation is resilience fully when the resilience of GeOI wafer is restored, and still keeps a certain amount of tensile strain.And top layer Si Ge receives the effect that pulls and supports of plastic deformation SiN enterree, and resilience fully finally forms single shaft tensile strain GeOI.
In like manner; As if being placed on, GeOI wafer top layer Si Ge aspect carries out mechanical bend and thermal annealing on the circular arc table top downwards; Because top layer Si Ge layer is in the bottom of GeOI wafer neutral surface; Its lattice will be compressed when bending is annealed, and lattice constant diminishes, and finally can obtain single shaft compressive strain GeOI wafer.
With respect to existing uniaxial strain GeOI technology, the present invention has the following advantages:
1) manufacture craft is simple: with existing similar compared with techniques, do not have thermal oxidation, ion injection, high temperature to peel off extra technology, two processing steps of mechanical bend and thermal annealing are only arranged.。
2) equipment is few and can make by oneself: only need crooked platform and two equipment of annealing furnace can realize the present invention, and crooked platform can be made by oneself.
3) annealing region is big: 200 ℃ to 300 ℃ annealing regions of existing relatively uniaxial strain SOI technology, annealing temperature of the present invention from minimum 250 ℃ to the highest 900 ℃, can select arbitrarily.
4) strain effects is good: with existing similar compared with techniques, under the same flexibility, dependent variable of the present invention is high, thereby can obtain higher carrier mobility.
5) hot property is good: compare with the biaxial strain GeOI wafer based on the empty substrate of SiGe that traditional C VD (chemical vapor deposition) extension is made; The uniaxial strain GeOI wafer that the present invention makes does not have thick SiGe resilient coating; Can reduce the hot expense of device and circuit greatly, its SiN enterree makes its device and circuit have good performance of heat dissipation again.
6) cost of manufacture is low: because manufacture craft is simple, equipment investment is few, thereby cost of manufacture is low.
Description of drawings
Fig. 1 is existing single shaft tensile strain GeOI principle and processing step;
Fig. 2 is existing single shaft compressive strain GeOI principle and processing step;
Fig. 3 is single shaft tensile strain GeOI wafer manufacturing principle of the present invention and processing step;
Fig. 4 is single shaft compressive strain GeOI wafer manufacturing principle of the present invention and processing step;
The 1-Si substrate, 2-SiN enterree, 3-top layer Ge layer.
Embodiment
Below in conjunction with specific embodiment, the present invention is elaborated.
The preparation of embodiment 1:3 inch uniaxial strain GeOI wafer
1, the GeOI wafer is selected: 3 inches (100) or (110) wafer ((100) or (110) refer to certain crystal face of GeOI wafer plane of crystal), the thick 0.4mm of Si substrate, the thick 500nm of SiN enterree, the thick 500nm of top layer Si.
The GeOI diameter wafer is selected: the diameter of GeOI wafer is big more; Its crooked minimum bending radius is just more little; The dependent variable of the uniaxial strain GeOI wafer that obtains is also just big more, and the electron mobility of final uniaxial strain GeOI wafer and the enhancing of hole mobility are also just high more.For made of the present invention based on for the uniaxial strain GeOI wafer of SiN enterree, according to the different process of its GeOI device and circuit, can select different-diameter GeOI wafer from 3 inches to 8 inches.
GeOI wafer crystal face and crystal orientation are selected: for the tensile strain GeOI wafer of made of the present invention; Should select (100) crystal face; Bending direction should be selected < 110>crystal orientation, and (< 110>refer to certain crystal orientation of wafer surface; Usually also be the channel direction of device), can obtain maximum electron mobility and promote.For the compressive strain GeOI wafer of made of the present invention, should select (110) crystal face, bending direction should be selected < 100>crystal orientation, can obtain maximum hole mobility and promote.
GeOI wafer Si substrate thickness is selected: the thickness of Si substrate is thin more, and the minimum bending radius of its GeOI wafer is just little, and the dependent variable of the single shaft tensile strain GeOI wafer that obtains is also just big more.For made of the present invention based on for the uniaxial strain GeOI wafer of SiN enterree, according to the different structure and the technology thereof of its GeOI device and circuit, can select the GeOI wafer of different Si substrate thickness.
GeOI wafer top layer Ge layer thickness is selected: according to the different structure of its GeOI device and circuit, can select the GeOI wafer of different top layer Ge layer thickness.If the compressive strain GeOI wafer based on the SiN enterree of made of the present invention is applied to cmos device and circuit, then require top layer Ge thickness can not surpass 30nm; If be applied to photo-detector, then require top layer Ge thickness can not be lower than 700nm;
GeOI wafer SiN thickness of insulating layer is selected: according to the different structure of GeOI device and circuit, can select the GeOI wafer of different SiN enterree thickness.If the tensile strain GeOI wafer based on the SiN enterree of made of the present invention is applied to cmos device and circuit, then require the SiN thickness of insulating layer to be not less than 250nm; If be applied to photo-detector, then require SiO
2Thickness of insulating layer is no more than 200nm;
Crooked platform material is selected: crooked platform material mainly is to select according to annealing temperature, guarantee that crooked platform is indeformable under the highest annealing temperature.For the present invention adopted based on for the GeOI wafer of SiN enterree, its highest annealing temperature is 900 ℃, and therefore crooked platform material can adopt the ZG35Cr26Ni12 heat-resisting steel material.
2, crooked platform radius of curvature is selected: according to the GeOI wafer of selecting, selecting crooked platform radius of curvature is 1m.The radius of curvature of crooked platform is to select according to the diameter and the thickness of GeOI wafer.Under the identical GeOI wafer size, the minimum bending radius of thin GeOI wafer is littler than thick GeOI wafer.Under the same thickness, the minimum bending radius of large scale GeOI wafer is littler than small size GeOI wafer.For made of the present invention based on for the tensile strain GeOI wafer of SiN enterree; The bending radius scope of its 4 inches GeOI wafers is 0.50m-1.2m; The bending radius scope of its 6 inches GeOI wafers is 0.45m-1.2m,, its 8 inches GeOI wafer bending radius scopes are 0.4m-1.2m.
3, GeOI wafer bending process step:
1) with GeOI wafer top layer Ge aspect upwards (or, upwards be tensile strain downwards,, be compressive strain downwards like Fig. 3, like Fig. 4, down with) be placed on the arc-shaped bend platform, its bending direction is parallel with < 110>or < 100>direction;
2) two cylindrical horizontal depression bars on the crooked platform lie in a horizontal plane in GeOI wafer two ends respectively, apart from 1 centimetre at its edge;
3) the push rod nut of one of them depression bar on the crooked platform of turn makes GeOI wafer one end fixing earlier;
4) the slow push rod nut of another depression bar of turn again makes the GeOI wafer crooked gradually along arc-shaped bend platform table top, until the GeOI wafer fully and arc-shaped bend platform table top fit fully.
4, annealing process step:
1) annealing temperature: 250 ℃;
2) heating rate: 5 ℃/minute;
3) annealing time: 10 hours;
4) rate of temperature fall: 5 ℃/minute;
5, unload frame: treat that furnace temperature reduces to room temperature, take out crooked platform.The push rod nut of two depression bars in the crooked platform two ends of simultaneously slow turn slowly promotes horizontal struts simultaneously, breaks away from the GeOI wafer fully until depression bar.
Through above-mentioned processing step, can obtain 3 inches uniaxial strain GeOI wafers based on the SiN enterree.
The preparation of embodiment 2:4 inch uniaxial strain GeOI wafer
1, the GeOI wafer is selected: 4 inches (100) or (110) crystal face, the thick 0.55mm of Si substrate, the thick 300nm of SiN enterree, top layer Ge bed thickness 50nm.
2, the bending curvature radius is selected: according to the GeOI wafer of selecting, selecting crooked platform radius of curvature is 0.75m.
3, GeOI wafer bending process step:
1) with GeOI wafer top layer Ge aspect upwards (or downwards) be placed on the stainless steel arc-shaped bend platform of cleaning, its < 110>or < 100>direction are parallel with bending direction, like Fig. 3 or shown in Figure 4;
2) two cylindrical horizontal depression bars on the crooked platform lie in a horizontal plane in GeOI wafer two ends respectively, apart from 1 centimetre at its edge;
3) the push rod nut of one of them depression bar on the crooked platform of turn makes GeOI wafer one end fixing earlier;
4) the slow push rod nut of another depression bar of turn again makes the GeOI wafer crooked gradually along arc-shaped bend platform table top, until the GeOI wafer fully and arc-shaped bend platform table top fit fully.
4, annealing process step:
1) annealing temperature: 400 ℃;
2) heating rate: 4 ℃/minute;
3) annealing time: 6 hours;
4) rate of temperature fall: 4 ℃/minute;
5, unload frame: treat that furnace temperature reduces to room temperature, take out crooked platform.The push rod nut of two depression bars in the crooked platform two ends of simultaneously slow turn slowly promotes horizontal struts simultaneously, breaks away from the GeOI wafer fully until depression bar.
Through above-mentioned processing step, can obtain 4 inches uniaxial strain GeOI wafers based on the SiN enterree.
The preparation of embodiment 3:6 inch uniaxial strain GeOI wafer
1, the GeOI wafer is selected: 6 inches (100) or (110) crystal face, the thick 0.68mm of Si substrate, the thick 1000nm of SiN enterree, the thick 1000nm of top layer Si Ge.
2, the bending curvature radius is selected: according to the GeOI wafer of selecting, selecting crooked platform radius of curvature is 0.5m.
3, GeOI wafer bending process step:
1) GeOI wafer top layer Si Ge is placed on the arc-shaped bend platform towards last (or downwards), its bending direction is parallel with < 110>or < 100>direction, like Fig. 3 or shown in Figure 4;
2) two cylindrical horizontal depression bars on the crooked platform lie in a horizontal plane in GeOI wafer two ends respectively, apart from 1 centimetre at its edge;
3) the push rod nut of one of them depression bar on the crooked platform of turn makes GeOI wafer one end fixing earlier;
4) the slow push rod nut of another depression bar of turn again makes the GeOI wafer crooked gradually along arc-shaped bend platform table top, until the GeOI wafer fully and arc-shaped bend platform table top fit fully.
4, annealing process step:
1) annealing temperature: 900 ℃;
2) heating rate: 3 ℃/minute;
3) annealing time: 2.5 hours;
4) rate of temperature fall: 3 ℃/minute;
5, unload frame: treat that furnace temperature reduces to room temperature, take out crooked platform.The push rod nut of two depression bars in the crooked platform two ends of simultaneously slow turn slowly promotes horizontal struts simultaneously, breaks away from the GeOI wafer fully until depression bar.
Through above-mentioned processing step, can obtain 6 inches uniaxial strain GeOI wafers based on the SiN enterree.
In order to make narration of the present invention more clear, below will make specifying to many details.For example concrete structure, composition, material, size, technical process and technology.
The used arc-shaped bend platform of the present invention adopts the ZG35Cr26Ni12 heat-resisting steel material, and this is indeformable under the highest annealing temperature in order to guarantee crooked platform.In addition, the used crooked platform of the present invention can adopt also that other are easy to machining, fineness is higher and resistant to elevated temperatures all materials are made.
Strain GeOI wafer base semiconductor substrate 1 of the present invention can be other semi-conducting materials also, like all possible semi-conducting materials such as Ge, GaAs.
Strain GeOI wafer top layer semi-conducting material 3 of the present invention is not limited to the Ge semi-conducting material, also Si, SiGe, GaAs etc. all be fit to make semi-conducting materials of GeOI wafer top layer semiconductive thin films.
The GeOI wafer that any process is made all is suitable for the present invention and makes uniaxial strain GeOI wafer, these processes comprise smart peeling (Smart-cut), annotate oxygen isolate (SIMOX), bonding and back of the body corrosion (BeGeOI), layer transfer (eLRANT), based on the epitaxial growth of GeOI wafer etc.
The selection principle of crooked annealing temperature of the present invention and annealing time is guarantee that plastic deformation takes place the SiN film in the GeOI crystal circle structure in annealing process, but the Si substrate in the GeOI wafer in annealing elastic deformation can only take place.Therefore, according to the Material Thermodynamics characteristic of SiN film, its minimum annealing temperature must not be lower than 250 ℃.And according to the thermodynamic behaviour of the Si backing material of GeOI wafer, its highest annealing temperature is not limited to 800 ℃, reaches as high as 900 ℃, near the fusing point of GeOI wafer top layer Ge.But the highest annealing temperature must be considered the thermodynamic property of crooked platform material, can not be higher than its deformation temperature.
Detailed description of the present invention and describing all based on the optimization test scheme, but person of skill in the art will appreciate that above-mentioned variation with other forms and details can't depart from essence of the present invention and scope.To those skilled in the art; After having understood content of the present invention and principle; Can be under the situation that does not deviate from the principle and scope of the present invention; Carry out various corrections and change on form and the details according to the method for the invention, but these are based on correction of the present invention with change still within claim protection range of the present invention.
Should be understood that, concerning those of ordinary skills, can improve or conversion, and all these improvement and conversion all should belong to the protection range of accompanying claims of the present invention according to above-mentioned explanation.
Claims (4)
1. the machinery based on the SiN enterree causes the manufacture method of uniaxial strain GeOI wafer, it is characterized in that may further comprise the steps: 1) GeOI wafer top layer Ge aspect is placed on the arc-shaped bend platform up or down; 2) two cylindrical stainless steel depression bars lie in a horizontal plane in GeOI wafer two ends respectively, apart from GeOI crystal round fringes 1cm; 3) slow turn connects the nut of depression bar, makes the GeOI wafer crooked gradually along the arc table top, the complete and arc table top applying until the GeOI wafer; 4) the arc-shaped bend platform that is loaded with the GeOI wafer is placed in the annealing furnace anneals, and annealing temperature can be selected arbitrarily in 250 ℃ to 900 ℃ scopes; 5) annealing slowly is cooled to room temperature after finishing, and takes out the arc-shaped bend platform that is loaded with the GeOI wafer; 6) turn connects the nut of depression bar, depression bar is slowly promoted, until the reinstatement of the GeOI of bending wafer.
2. manufacture method according to claim 1 is characterized in that, the radius of curvature of described crooked platform can change from 1.2m to 0.35m continuously, the uniaxial strain GeOI wafer of the differently strained amount of its respective production; Crooked platform material adopts the ZG35Cr26Ni12 heat-resisting steel material.
3. manufacture method according to claim 1 is characterized in that, the annealing process of said step 4) is: annealed 10 hours down at 250 ℃; Perhaps annealed 6 hours down at 400 ℃; Perhaps annealed 2.5 hours down at 900 ℃.
4. manufacture method according to claim 1 is characterized in that, said GeOI wafer is 3 inches, 4 inches, 5 inches, 6 inches, 8 inches a GeOI wafer.
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| CN102201364A (en) * | 2011-05-26 | 2011-09-28 | 北京大学 | Method for preparing germanium-on-insulator (GeOI) substrate |
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| US20060141748A1 (en) * | 2004-03-05 | 2006-06-29 | Nicolas Daval | Thermal treament of a semiconductor layer |
| CN101203943A (en) * | 2005-06-27 | 2008-06-18 | 加利福尼亚大学董事会 | Method for producing dislocation-free strained crystalline films |
| CN102201364A (en) * | 2011-05-26 | 2011-09-28 | 北京大学 | Method for preparing germanium-on-insulator (GeOI) substrate |
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