CN102403259B - Manufacturing method of single-shaft strain GeOI wafer based on mechanical bending table - Google Patents

Abstract

The invention discloses a method for manufacturing a uniaxially strained GeOI wafer based on a mechanical bending table, comprising the following steps: 1) placing the Ge layer on the top layer of the GeOI wafer upwards or downwards on an arc-shaped bending table; 2) two cylinders 3) Slowly turn the nut connecting the pressure rods to make the GeOI wafer gradually bend along the arc-shaped table until the GeOI wafer is completely in contact 4) The curved table carrying the GeOI wafer is placed in the annealing furnace for annealing; 5) After the annealing is completed, the temperature is slowly cooled to room temperature, and the curved table carrying the GeOI wafer is taken out; 6 ) Turn the nut connected to the pressure rod, and slowly lift the pressure rod until the bent GeOI wafer returns to its original shape. The invention has the following advantages: 1) the raw material is easily obtained; 2) the production cost is low; 3) the production process is simple; 4) the process temperature range is wide; 5) the yield is high; 6) the surface roughness is small; 7) the strain effect is good; 8) Good thermal performance.

Description

Fabrication method of uniaxially strained GeOI wafer based on mechanical bending stage

technical field

The invention belongs to the technical field of microelectronics and relates to a semiconductor material manufacturing technology. Specifically, it is a new method for manufacturing uniaxially strained GeOI (Germanium On Insulator, germanium on buried insulating layer) wafers, which can significantly enhance the electron mobility and hole mobility of GeOI wafers, and improve the integration of GeOI devices and integration. The electrical and optical properties of the circuit.

Background technique

The electron and hole mobility of the semiconductor Ge are 2.8 times and 4.2 times that of Si, respectively, and its hole mobility is the highest among all semiconductors. Similar to strained Si, the carrier mobility of strained Ge is also greatly improved, and the hole mobility of buried channel strained Ge can be increased by 6-8 times. Therefore, Ge and strained Ge will be the best channel materials for Si-based CMOS devices and integrated circuits of 16 nanometers and below. Ge is also an excellent optoelectronic material, and has a very wide range of applications in detectors (visible light to near-infrared), modulators, optical waveguides, optical emitters, and solar cells.

Since the forbidden band width is only 0.67eV, the biggest weakness of Ge devices and circuits is the large leakage of the substrate. GeOI was developed to solve the substrate leakage current, and has been widely used in the manufacture of semiconductor devices and integrated circuits.

The strained GeOI, which combines the advantages of strained Ge and GeOI, provides a new solution for the development of new ultra-high-speed, low power consumption, radiation-resistant, and highly integrated silicon-based devices and chips. important application prospects.

The traditional strained GeOI is based on the biaxial compressive strain of the SOI wafer, that is, the strained Ge is grown directly on the SOI (Silic On On Insulator, silicon-on-insulator) wafer, or the SiGe with a Ge composition gradient is first grown on the SOI wafer. layer as a virtual substrate, and then epitaxially grow the required strained Ge layer on the SiGe layer. The main disadvantages of traditional strained GeOI are high dislocation density, only biaxial compressive strain, low mobility improvement, SiGe virtual substrate increases thermal overhead and manufacturing cost, and SiGe virtual substrate seriously affects the heat dissipation of devices and circuits , The critical thickness of the strained Ge layer is limited by the Ge composition, and the hole mobility improvement under high field will degenerate, etc.

C.Himcinschi proposed the fabrication technology of uniaxially strained SOI wafer in 2007, see [1] C.Himcinschi., I.Radu, F.Muster, R.SiO2gh, M.Reiche, M.Petzold, U.Go ¨ sele, SH Christiansen, Uniaxially strained silicon by wafer bonding and layertransfer, Solid-State electronics, 51(2007) 226-230; [2] C.Himcinschi, M.Reiche, R.Scholz, SHChristiansen, and U. Compressive uniaxially strained silicon on insulator by prestrained wafer bonding and layer transfer APPLIeD, PHYSICS LeTTeRS 90, 231909 (2007). The process principle and steps of this technology are shown in Figure 1 and Figure 2, and the manufacturing process steps of the uniaxial tensile strain GeOI are described as follows:

1. Thermally oxidize the 4-inch Si sheet 1 first, and then inject H ⁺ (hydrogen ions) into the oxidized sheet 1 .

2. Put the H ⁺ -injected oxide sheet 1 on the curved bending table, bend it through the external pressure rod, and fit closely with the curved table; then place the 3-inch Si sheet 2 on the curved table 4 along the same bending direction Inch injection H ⁺ oxidation sheet 1, bend it through the inner pressure rod, and it is closely attached to injection H ⁺ oxidation sheet 1;

3. Place the bending table in an annealing furnace and anneal at 200°C for 15 hours.

4. Remove the bent and bonded two Si wafers from the bending table, put them back into the annealing furnace, and anneal at 500°C for 1 hour to complete the smart peeling and finally form a uniaxially strained GeOI wafer .

The main disadvantages of this technology are: 1) The process steps are complicated: the method must go through the necessary main processes such as thermal oxidation, H ⁺ ion implantation, stripping annealing and related steps. 2) The bending temperature is limited: since the bonding and bending annealing are performed before the smart stripping, the bending annealing temperature cannot be higher than 300°C due to the limitation of the H ⁺ stripping temperature, otherwise the stripping will occur during the bending annealing process, making Si Pieces shattered. 3) Long production cycle: Additional process steps such as thermal oxidation, H ⁺ ion implantation, and stripping annealing increase the production time. 4) Low yield: This method is to use two overlapping silicon wafers for mechanical bending and bonding, and to perform high-temperature peeling in the bent state, and the silicon wafers are easily broken.

Contents of the invention

The purpose of the present invention is to overcome above-mentioned deficiencies in the prior art, propose a kind of manufacturing method of mechanically induced uniaxial strain GeOI wafer, to reduce the manufacturing cost of strained GeOI wafer, improve the heat dissipation performance of strained GeOI device and integrated circuit, insulation The performance and integration level meet the needs of the microelectronics technology field, especially ultra-high speed, low power consumption, radiation resistance and high-power devices and integrated circuits for strained GeOI wafers. Adopt the following technical solutions:

A method for manufacturing a mechanically induced uniaxial strain GeOI wafer, comprising the following steps: 1) placing the Ge layer on the top layer of the GeOI wafer upwards or downwards on an arc-shaped bending platform; 2) placing two cylindrical stainless steel pressure rods horizontally respectively At both ends of the GeOI wafer, 1cm away from the edge of the GeOI wafer; 3) Slowly turn the nut connecting the pressure rod to make the GeOI wafer gradually bend along the arc-shaped table until the GeOI wafer is completely attached to the arc-shaped table; 4 ) The arc-shaped bending table carrying the GeOI wafer is placed in an annealing furnace for annealing, and the annealing temperature can be selected arbitrarily within the range of 200°C to 900°C. For example, it can be annealed at 200°C for 10 hours, and can also be annealed at 600°C for 5 hours; 5) Slowly cool down to room temperature after annealing, and take out the curved bending table carrying the GeOI wafer; 6) Rotate the connection pressure Screw the nut of the rod, and lift the pressure rod slowly until the bent GeOI wafer returns to its original shape. The minimum annealing temperature of the bending table carrying the GeOI wafer in the annealing furnace is 200°C to ensure that the deformation of the SiO ₂ buried insulating layer in the GeOI wafer can exceed its yield strength and undergo plastic deformation during this process; the maximum The annealing temperature is 900°C, close to the melting point of Ge. But the maximum annealing temperature shall not be higher than the deformation temperature of the mechanical bending table

According to the manufacturing method, the radius of curvature of the curved bending table can be continuously changed from 1.2m to 0.35m, which corresponds to the manufacturing of uniaxially strained GeOI wafers with different strains.

In the manufacturing method, the annealing process in step 4) is: annealing at 200°C for 10 hours; or annealing at 400°C for 5 hours; or annealing at 900°C for 2.2 hours.

In the manufacturing method, the GeOI wafers are 3-inch, 4-inch, 5-inch, 6-inch, and 8-inch GeOI wafers.

Technical principle of the present invention:

The Ge layer on the top layer of the finished GeOI sheet is placed upwards on the arc-shaped table for mechanical bending, and then thermal annealed. According to the principle of material elastic-plastic mechanics, under the effect of long-term bending deformation heat treatment, the SiO2 layer and the top Ge layer on the upper neutral surface of the GeOI wafer will undergo uniaxial tensile deformation along the bending direction, and their lattice constants will become larger. That is, so-called uniaxial tensile strain occurs. At the same time, a certain amount of elastic potential energy is stored inside the GeOI wafer. When the annealing is finished and the mechanical external force is removed, under the action of this elastic potential energy, the GeOI wafer will rebound, that is, return from the bent state to the original state, as shown in Figure 3.

However, the top Ge layer in the recovered GeOI wafer retains a certain amount of tensile strain. This is because during the bending thermal annealing treatment, the appropriate annealing temperature and time are set to ensure that the applied mechanical external force can exceed the yield strength of SiO ₂ but less than the yield strength of the Si substrate, so that SiO ₂ undergoes plastic deformation, while Si substrates are always elastically deformable. The plastically deformed SiO ₂ buried insulating layer cannot fully rebound when the GeOI wafer rebounds and recovers, and still maintains a certain amount of tensile strain. However, the top Ge layer is pulled by the plastically deformed SiO ₂ buried insulating layer, and cannot fully rebound, and finally forms a uniaxial tensile strain GeOI wafer.

Similarly, if the top Ge layer of the GeOI wafer is placed downward on the arc-shaped table for mechanical bending and thermal annealing, since the top SiGe layer is at the lower part of the neutral plane of the GeOI wafer, its crystal lattice will be destroyed during bending annealing. Compression, the lattice constant becomes smaller, and finally a uniaxial compressively strained GeOI wafer can be obtained.

Compared with the existing uniaxially strained GeOI technology, the present invention has the following advantages:

1) Raw materials are easy to obtain: the present invention uses finished GeOI wafers, which can be purchased in batches at any time in the market, greatly reducing process complexity and equipment costs.

2) Low production cost: due to the simple production process and low equipment investment, the production cost is low.

3) The manufacturing process is simple: compared with existing similar technologies, there are no additional processes such as thermal oxidation, ion implantation, and high-temperature stripping, and there are only two processes of mechanical bending and thermal annealing.

4) Wide process temperature range: Compared with the annealing temperature range of 200°C to 300°C in the existing similar technology, the annealing temperature of the present invention can be arbitrarily selected from the lowest 200°C to the highest 900°C.

5) High yield rate: The existing technology uses two Si wafers for bonding bending annealing, and obtains a uniaxially strained SOI wafer by high-temperature peeling in a bent state, so the Si wafers are very easy to break. However, in the present invention, only one finished GeOI wafer is subjected to bending annealing to obtain a uniaxially strained GeOI wafer, which is not easy to be broken and thus has a high yield.

6) Small surface roughness: the present invention does not need to produce strained GeOI through a lift-off process, so the surface roughness of its top layer Ge thin film single crystal is much smaller than that of the existing similar technology.

7) Good strain effect: Compared with the existing similar technology, under the same bending degree, the strain of the present invention is high, so higher carrier mobility can be obtained.

8) Good thermal performance: Compared with traditional strained GeOI wafers based on SiGe virtual substrates, the uniaxial strained GeOI wafers produced by the present invention do not require SiGe virtual substrates, thereby greatly reducing the heat of devices and circuits. The overhead is also conducive to the heat dissipation of its devices and circuits.

Description of drawings

Figure 1 shows the principle and process steps of the existing uniaxial tensile strain GeOI;

Figure 2 shows the principle and process steps of the existing uniaxial compressive strain GeOI;

Fig. 3 is the manufacturing principle and process steps of the uniaxial tensile strain GeOI wafer of the present invention;

Fig. 4 is the manufacturing principle and process steps of the uniaxial compressively strained GeOI wafer of the present invention;

1-Si substrate, 2-SiO ₂ buried insulating layer, 3-top Ge layer.

Detailed ways

The present invention will be described in detail below in conjunction with specific embodiments.

Embodiment 1: Preparation of 3-inch uniaxially strained GeOI wafer

1. GeOI wafer selection: 3-inch (100) or (110) wafer ((100) or (110) refers to a certain crystal surface of the GeOI wafer crystal surface), Si substrate thickness 0.4mm, The SiO ₂ buried insulating layer is 500nm thick, and the top Ge layer is 500nm thick.

GeOI wafer diameter selection: the larger the diameter of the GeOI wafer, the smaller the minimum bending radius of the bend, the greater the strain of the obtained uniaxially strained GeOI wafer, and the electron migration of the final uniaxially strained GeOI wafer The enhancement of rate and hole mobility is also higher. For the uniaxially strained GeOI wafer based on the _SiO2 buried insulating layer produced in the present invention, GeOI wafers with different diameters from 3 inches to 8 inches can be selected according to the different processes of the GeOI device and circuit.

GeOI wafer crystal plane and crystal direction selection: for the tensile strained GeOI wafer made by the present invention, (100) crystal plane should be selected, and the bending direction should be selected <110> crystal direction (<110> refers to the wafer A certain crystal orientation on the surface of the wafer, which is usually the channel direction of the device), can obtain the largest increase in electron mobility. For the compressively strained GeOI wafer produced in the present invention, the (110) crystal plane should be selected, and the <100> crystal orientation should be selected for the bending direction, so as to obtain the maximum hole mobility improvement.

GeOI wafer Si substrate thickness selection: the thinner the Si substrate is, the smaller the minimum bending radius of the GeOI wafer is, and the greater the strain of the obtained uniaxial tensile strain GeOI wafer is. For the uniaxially strained GeOI wafer based on the _SiO2 buried insulating layer produced in the present invention, GeOI wafers with different Si substrate thicknesses can be selected according to the different structures and processes of the GeOI devices and circuits.

Thickness selection of Ge layer on the top layer of GeOI wafer: According to the different structures of GeOI devices and circuits, GeOI wafers with different thicknesses of Ge layer on the top layer can be selected. If the strained GeOI wafer based on _SiO buried insulating layer made by the present invention is applied to CMOS devices and circuits, then the Ge thickness of the top layer is required to be no more than 30nm; if applied to photodetectors, the Ge thickness of the top layer is required to be no less than 700nm;

GeOI wafer SiO2 buried insulating layer thickness selection: According to different structures of GeOI devices and circuits, GeOI wafers with different SiO2 insulating layer thicknesses can be selected. If the strained GeOI wafer based on the _SiO2 buried insulating layer made by the present invention is applied to CMOS devices and circuits, the SiO2 insulating layer thickness is required to be no less than 250nm; if applied to photodetectors, the SiO2 insulating layer thickness is required to be no more than 200nm;

Bending table material selection: The bending table material is mainly selected according to the annealing temperature, and it is necessary to ensure that the bending table does not deform at the highest annealing temperature. For the GeOI wafer based on the SiO ₂ buried insulating layer used in the present invention, its maximum annealing temperature is 900° C., so the material of the bending table can be high temperature-resistant ZG35Cr26Ni12 heat-resistant steel material.

2. Selection of the radius of curvature of the bending table: According to the selected GeOI wafer, the radius of curvature of the bending table is selected to be 1m. The radius of curvature of the bending table is selected according to the diameter and thickness of the GeOI wafer. Under the same GeOI wafer size, the minimum bending radius of a thin GeOI wafer is smaller than that of a thick GeOI wafer. Under the same thickness, the minimum bending radius of a large-size GeOI wafer is smaller than that of a small-size GeOI wafer. For the tensile strained GeOI wafer based on SiO2 buried insulating layer made by the present invention, the bending radius range of its 4-inch GeOI wafer is 0.50m-1.2m, and the bending radius range of its 6-inch GeOI wafer is 0.45m -1.2m, the bending radius of its 8-inch GeOI wafer ranges from 0.4m to 1.2m.

3. GeOI wafer bending process steps:

1) Place the Ge layer on the top layer of the GeOI wafer upwards (or downwards, upwards is tensile strain, as shown in Figure 3, and downwards is compressive strain, as shown in Figure 4, the same below) is placed on an arc-shaped bending table, and its bending direction is the same as <110> or <100> direction parallel;

2) Two cylindrical horizontal pressure bars on the bending table are placed horizontally at both ends of the GeOI wafer, 1 cm away from its edge;

3) Rotate the ejector nut of one of the pressure rods on the bending table to fix one end of the GeOI wafer first;

4) Slowly turn the ejector nut of another pressure rod to gradually bend the GeOI wafer along the arc-shaped bending table until the GeOI wafer is completely attached to the arc-shaped bending table.

4. Annealing process steps:

1) Annealing temperature: 200°C;

2) Heating rate: 5°C/min;

3) Annealing time: 10 hours;

4) Cooling rate: 5°C/min;

5. Unloading frame: When the furnace temperature drops to room temperature, take out the bending table. At the same time, slowly rotate the ejector nuts of the two pressure rods at both ends of the bending table to slowly lift the horizontal pressure rods at the same time until the pressure rods are completely detached from the GeOI wafer.

Through the above process steps, a 3-inch uniaxially strained GeOI wafer can be obtained.

Embodiment 2: Preparation of 4-inch uniaxially strained GeOI wafer

1. GeOI wafer selection: 4-inch (100) or (110) crystal plane, Si substrate thickness 0.55mm, SiO ₂ buried insulating layer thickness 300nm, top layer Ge layer thickness 50nm.

2. Selection of bending radius of curvature: According to the selected GeOI wafer, the radius of curvature of the bending table is selected to be 0.75m.

3. GeOI wafer bending process steps:

1) Place the top Ge layer of the GeOI wafer upwards (or downwards) on a clean stainless steel arc-shaped bending table, and its <110> or <100> direction is parallel to the bending direction, as shown in Figure 3 or Figure 4;

2) Two cylindrical horizontal pressure bars on the bending table are placed horizontally at both ends of the GeOI wafer, 1 cm away from its edge;

3) Rotate the ejector nut of one of the pressure rods on the bending table to fix one end of the GeOI wafer first;

4) Slowly turn the ejector nut of another pressure rod to gradually bend the GeOI wafer along the arc-shaped bending table until the GeOI wafer is completely attached to the arc-shaped bending table.

4. Annealing process steps:

1) Annealing temperature: 400°C;

2) Heating rate: 4°C/min;

3) Annealing time: 5 hours;

4) Cooling rate: 4°C/min;

5. Unloading frame: When the furnace temperature drops to room temperature, take out the bending table. At the same time, slowly rotate the ejector nuts of the two pressure rods at both ends of the bending table to slowly lift the horizontal pressure rods at the same time until the pressure rods are completely detached from the GeOI wafer.

Through the above process steps, a 4-inch uniaxially strained GeOI wafer can be obtained.

Embodiment 3: Preparation of 6-inch uniaxially strained GeOI wafer

1. GeOI wafer selection: 6-inch (100) or (110) crystal plane, Si substrate thickness 0.68mm, SiO2 buried insulating layer thickness 1000nm, top Ge layer thickness 1000nm.

2. Selection of bending radius of curvature: According to the selected GeOI wafer, the radius of curvature of the bending table is selected to be 0.5m.

3. GeOI wafer bending process steps:

1) Place the Ge layer on the top layer of the GeOI wafer upwards (or downwards) on an arc-shaped bending table, and its bending direction is parallel to the <110> or <100> direction, as shown in Figure 3 or Figure 4;

2) Two cylindrical horizontal pressure bars on the bending table are placed horizontally at both ends of the GeOI wafer, 1 cm away from its edge;

3) Rotate the ejector nut of one of the pressure rods on the bending table to fix one end of the GeOI wafer first;

4) Slowly turn the ejector nut of another pressure rod to gradually bend the GeOI wafer along the arc-shaped bending table until the GeOI wafer is completely attached to the arc-shaped bending table.

4. Annealing process steps:

1) Annealing temperature: 900°C;

2) Heating rate: 3°C/min;

3) Annealing time: 2.2 hours;

4) Cooling rate: 3°C/min;

5. Unloading frame: When the furnace temperature drops to room temperature, take out the bending table. At the same time, slowly rotate the ejector nuts of the two pressure rods at both ends of the bending table to slowly lift the horizontal pressure rods at the same time until the pressure rods are completely detached from the GeOI wafer.

Through the above process steps, a 6-inch uniaxially strained GeOI wafer can be obtained.

In order to make the description of the present invention clearer, many details will be described in detail below. Such as specific structure, composition, material, size, process and technology.

The arc-shaped bending table used in the present invention adopts ZG35Cr26Ni12 heat-resistant steel material, which is to ensure that the bending table does not deform at the highest annealing temperature. In addition, the bending table used in the present invention can also be made of other materials that are easy to machine, have high smoothness and high temperature resistance.

The semiconductor substrate 1 at the bottom of the strained GeOI wafer of the present invention may also be other semiconductor materials, such as all possible semiconductor materials such as Ge and GaAs.

The strained GeOI wafer top-layer semiconductor material 3 of the present invention is not limited to Ge semiconductor materials, and can also be all semiconductor materials suitable for making GeOI wafer top-layer semiconductor thin films such as Si, SiGe, and GaAs.

GeOI wafers made by any process method are suitable for making uniaxially strained GeOI wafers in the present invention, and these process methods include intelligent stripping (Smart-cut), oxygen injection isolation (SIMOX), bonding and back etching (BeGeOI), Layer transfer (eLRANT), epitaxial growth on GeOI wafers, etc.

The selection principle of bending annealing temperature and annealing time in the present invention is to ensure that the SiO2 film in the GeOI wafer structure undergoes plastic deformation during the annealing process, but the Si substrate in the GeOI wafer can only undergo elastic deformation during annealing. Therefore, according to the material thermodynamic properties of _SiO2 thin film, its minimum annealing temperature should not be lower than 200 °C. According to the characteristics of the Ge layer on the top layer of the GeOI wafer, the maximum annealing temperature can reach 900°C, which is close to the melting point of Ge. However, the maximum annealing temperature must consider the thermodynamic properties of the bending table material and cannot be higher than its deformation temperature.

The detailed description and description of the present invention are all based on the preferred experimental scheme, but those skilled in the art will understand that changes in the above and other forms and details will not deviate from the essence and scope of the present invention. For those skilled in the art, after understanding the content and principles of the present invention, they can make various modifications and changes in form and details according to the methods of the present invention without departing from the principles and scope of the present invention. But these amendments and changes based on the present invention are still within the protection scope of the claims of the present invention.

It should be understood that those skilled in the art can make improvements or changes based on the above description, and all these improvements and changes should fall within the protection scope of the appended claims of the present invention.

Claims (4)

1. A method for making a uniaxially strained GeOI wafer based on a mechanical bending table, characterized in that the GeOI wafer of the finished product is used as a raw material, only having two processes of mechanical bending and thermal annealing, and only using a bending table and an annealing furnace Two sets of equipment, including the following steps: 1) Place the Ge layer on the top layer of the GeOI wafer upwards or downwards on an arc-shaped bending table, and its minimum curvature radius is related to the size of the GeOI wafer; 2) Two cylindrical stainless steel pressure rods are respectively horizontal Place it on both ends of the GeOI wafer, 1cm away from the edge of the GeOI wafer; 3) Slowly turn the nut connecting the pressure rod to make the GeOI wafer gradually bend along the arc-shaped table until the GeOI wafer is completely attached to the arc-shaped table; 4) The curved bending table carrying the GeOI wafer is placed in an annealing furnace for annealing, the annealing temperature is between 200°C and 900°C; 5) After the annealing is completed, the temperature is slowly cooled to room temperature, and the GeOI wafer is taken out Arc-shaped bending table; 6) Turn the nut connected to the pressure bar to slowly lift the pressure bar until the bent GeOI wafer returns to its original shape. 2. The manufacturing method according to claim 1, characterized in that, the curvature radius of the bending table is 1.2m to 0.35m; the material of the bending table is ZG35Cr26Ni12 heat-resistant steel. 3. The manufacturing method according to claim 1, characterized in that the annealing temperature of the annealing process in step 4) is closely related to the annealing time, being annealing at 200°C for 10 hours; or annealing at 400°C for 5 hours hours; or anneal at 900°C for 2.2 hours. 4. The manufacturing method according to claim 1, wherein the GeOI wafer is a 3-inch, 4-inch, 5-inch, 6-inch, 8-inch GeOI wafer.