CN102437063A - Manufacturing method of flip chip with liquid salient points - Google Patents
Manufacturing method of flip chip with liquid salient points Download PDFInfo
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- CN102437063A CN102437063A CN201110382009XA CN201110382009A CN102437063A CN 102437063 A CN102437063 A CN 102437063A CN 201110382009X A CN201110382009X A CN 201110382009XA CN 201110382009 A CN201110382009 A CN 201110382009A CN 102437063 A CN102437063 A CN 102437063A
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- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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Abstract
The invention relates to a manufacturing method of a flip chip with liquid salient points. The method comprises: dams are grown around electrodes of a chip; liquid Ga-In salient points with a normal temperature are formed in regions surrounded by the dams; para position and crimping between the salient points of the chip and electrodes of a wiring plate is accurately carried out at a certain temperature and under a certain pressure; and a space between the chip and the wiring plate is filled with underfill and solidification is carried out. According to the invention, because a range of salient points is defined, an occurrence of a phenomenon of short circuit between adjacent salient points during fusing of solders according to a traditional flip chip structure can be avoided; there is no need for a high temperature environment and an occurrence of a phenomenon of device failure caused by the high temperature can be effectively avoided; the salient points are in a liquid state at a normal temperature, so that flowing tension is realized, a generated stress is small, high electrical and mechanical performances are realized and there is no mechanical damage; and the liquid salient points are contacted with electrodes well, so that high conductivity and heat conducting capability are realized.
Description
Technical field
The present invention relates to a kind of method of Flip-Chip Using; Relate more specifically to around chip electrode, generate dykes and dams; In its delimited area, form salient point with normal temperature liquid alloy Ga-In; Be crimped onto under uniform temperature and the pressure on the wiring plate electrode, carrying out the flip-chip manufacture method of filling and solidifying under the chip.
Background technology
Controlled collapsible chip connec-tion is meant the technology that on the connection pads of chip, forms salient point and be directly connected to the PCB substrate.Its technology has that packaging density is high, electric heating property good, good reliability, low cost and other advantages.In recent years, more and more urgent along with popularizing of the miniaturization of electronic equipment, particularly portable communication system to the requirement of high-density packages, thus adopt the flip chip technology (fct) of all kinds of salient points to have ample scope for one's abilities.
Shown in Figure 2 is the structure of conventional flip chip salient point, and its composition comprises: chip 1, passivation layer 2, aluminum pad 3, ubm layer UBM (Under-Bump Metallurgy) 4, salient point 5.Salient point 5 promptly is the projected electrode that on chip aluminium electrode welding zone, forms, and makes through this electrode that chip is real to be contained on the base plate for packaging such as PCB.For reaching the good adhesiveness of salient point metal 5 and aluminum pad 3 and passivation layer 2; Prevent that again salient point metal 5 and aluminum pad 3 from generating undesirable intermetallic compound, generally should under the salient point metal, prepare the multilevel metallization layer 4 that adhesion layer, diffusion impervious layer and conductive layer are arranged earlier.Typical adhesiving metal has Cr, Ti, Ni, TiN etc., and the diffusion impervious layer metal has W, Mo, Ni etc., conducting metal Au then commonly used, Cu, Pb/Sn etc., and this multiple metal layer often adopts methods such as sputter, evaporation, chemical plating, plating to accomplish.Mostly the manufacturing materials of salient point metal 5 is Au, Cu, Pb/Sn, In or their combination.The method that forms salient point 5 mainly contains galvanoplastic, electroless plating method, stud bump forming method, mould printing solder method and heat injection solder method etc.In these salient points, the Pb/Sn solder bump enjoys attention because of having outstanding advantage.Because it is hemisphere, but when flip chip bonding along with solder fusing autoregistration location, can control the degree of subsiding and the bump height of Pb/Sn scolder, so be called control collapsed chip interconnection technique (C4) again.Au bump is mainly used in the TAB (tape automated bonding) and the real dress of COG (chip on glass) of LCD driving element; The former realizes the intermetallic bonding through the pin of au bump and electrotinning, being connected of the ITO film of the latter through anisotropic conductive film (ACF) realization Au salient point and LCD.Traditional flip chip structure is at solder fusing, during adjacent bump bonding, occurs short circuit phenomenon each other easily, so the size of salient point and spacing are restricted.
At present, flexible package is so that its distribution density is high, the distribution spatial constraints is few, collapsible, the flexibility ratio advantages of higher extensively is used in applications such as the space is narrow and small, removable, collapsible.Along with the optimization step by step of product, also increasingly high to the requirement of the electric and mechanical performance of device.The appearance of liquid salient point will better guarantee the electric reliability with mechanical performance of device.Because mismatch in coefficient of thermal expansion between encapsulating material and the chip, the Stress Release when causing ambient temperature to change easily causes damage to chip.The application of liquid salient point reduces the internal stress of package parts in the process of variations in temperature, thereby reduces the damage of chip.
Summary of the invention
For addressing the above problem, the purpose of this invention is to provide a kind of Flipchip method, this method is easy to generate the problem of short circuit phenomenon in the time of can effectively solving bump bonding, and realizes less pressure point pitch.
Another object of the present invention is that the salient point for flip-chip provides a kind of new material, and this metal material is liquid at normal temperatures, and its mobile tension force can guarantee electric and mechanical connection reliably, and it is little and can not cause mechanical damage to produce stress.In the interconnected process of flip-chip crimping, do not need very high-temperature, thereby avoid chip to receive high-temperature damage.
For achieving the above object, the present invention realizes through following execution mode.
Execution mode of the present invention comprises: be used in and grow on the chip around the dykes and dams of electrode; In the dykes and dams region surrounded, form normal temperature liquid alloy Ga-In salient point; The molar ratio scope of alloying component is In 8%-16%; Ga 92%-84%, the melting range of this composition alloy are 15 ℃-20 ℃, are liquid at normal temperatures.Suitably heating with chip bump and the accurate contraposition of wiring plate electrode, imposes certain pressure under the condition of the Ga-In melting temperature that is lower than used composition, realizes its adhesion.Fill the end between chip and the wiring plate and fill glue and curing.
Description of drawings
Fig. 1 is the Ga-In binary phase diagraml;
Fig. 2 is the structural representation of conventional flip chip salient point;
Fig. 3 is the flow chart of flip-chip implementation method of the present invention;
Fig. 4 is the cutaway view that is furnished with the chip of electrode;
Fig. 5 generates the cutaway view of dykes and dams and the vertical view that dykes and dams distribute on chip;
Fig. 6 is the cutaway view that in the dykes and dams region surrounded, generates the liquid Ga-In salient point of normal temperature;
Fig. 7 is the cutaway view of chip bump and wiring plate electrode contraposition crimping;
Fig. 8 is for filling the cutaway view that fills glue and solidify in the end between chip and the wiring plate.
Embodiment
Below in conjunction with accompanying drawing technical scheme of the present invention is further described.
Fig. 1 is the Ga-In binary phase diagraml, and the present invention is used to be AB section phasor curve.
Fig. 3 is the flow chart of flip-chip implementation method of the present invention.As shown in Figure 3; Flip-chip implementation method of the present invention comprises: around chip electrode, generate dykes and dams (S11); The scope that centers at dykes and dams forms the liquid Ga-In salient point (S12) of normal temperature; With chip bump and the accurate contraposition crimping of wiring plate electrode (S13), fill the end between chip and the wiring plate and fill glue and solidify (S14).
Fig. 4 is for being furnished with the cutaway view of electrode 7 on the chip 6, the pitch of electrode can minimumly reach 25-50 μ m.
Fig. 5 left side figure is the cutaway view that on chip 6, generates dykes and dams 8 (S11), and the manufacture method of dykes and dams 8 has technologies such as hydatogenesis, plating, mould printing, and the manufacturing materials of dykes and dams 8 has silica gel, AB glue, black glue etc.The advantage of these macromolecular materials is that they have very strong adhesive capacity.Dykes and dams 8 will be used to define the forming area of salient point 9 as the retention device of flip-chip manufacturing process bumps material next.Wherein, the width of dykes and dams 8 can change according to chip electrode 7 with the spacing of height and dykes and dams 8.The right figure of Fig. 5 is the vertical view that dykes and dams 8 distribute on the chip.The flat shape of dykes and dams 8 can be circular, square, polygon etc.
Fig. 6 is the cutaway view that in the dykes and dams region surrounded, generates the liquid Ga-In salient point of normal temperature 9 (S12).The molar ratio scope of Ga-In alloying component is In 8%-16%, and Ga 92%-84%, the melting range of this composition alloy are 15 ℃-20 ℃, is liquid at normal temperatures.Liquid Ga-In arrives the dykes and dams region surrounded with the same dose drip irrigation with normal temperature, forms salient point.It is oxidized that Ga-In is prone to, so arbitrary step all will be operated in protective gas among the S12, S14.The crimping process is for fear of producing bubble, so S13 will operate under vacuum condition.
Fig. 7 is the electrode 11 of wiring plate 10 and the cutaway view of the salient point 9 contraposition crimping (S13) of chip 6.Suitably heating under the condition of the Ga-In melting temperature that is lower than used composition, this moment, salient point was solid-state.With chip bump 9 and the 11 accurate contrapositions of wiring plate electrode, press, realize its adhesion, an example is the pressure that each chip is applied 2-10kg, duration 10-20 second.
Fig. 8 is for filling the cutaway view that fills glue 12 and solidify (S14) in the end between chip 6 and the wiring plate 10.Between dykes and dams and dykes and dams, fill the end and fill glue 12, the material that glue 12 is filled at the end comprises resin, silica gel etc., and the method for filling has drip irrigation method, cast gate injection, infusion process etc.Be cured subsequently, the method for curing has UV-irradiation, heating etc.
Above content is to combine concrete execution mode to the further explain that the present invention did, and can not assert that practical implementation of the present invention is confined to these explanations.For the those of ordinary skill of technical field under the present invention, under the prerequisite that does not break away from the present invention's design, can also make some simple deduction or replace, all should be regarded as belonging to protection scope of the present invention.
Claims (9)
1. the manufacture method of a liquid salient point flip-chip is characterized in that comprising: on chip, grow around the dykes and dams of electrode; In the dykes and dams region surrounded, form the liquid Ga-In salient point of normal temperature; Under uniform temperature and pressure with chip bump and the accurate contraposition crimping of wiring plate electrode; Fill the end between chip and the wiring plate and fill glue and curing, thereby realize the encapsulation of flip-chip.
2. the method for claim 1 is characterized in that, the method for growth dykes and dams comprises on chip: hydatogenesis, plating, silk screen printing etc., the manufacturing materials of said dykes and dams is macromolecular materials, comprises silica gel, AB glue, black glue etc.
3. the method for claim 1 is characterized in that, the shape of said dykes and dams comprises circle, square and polygon etc.
4. the method for claim 1 is characterized in that, the method that generates ubm layer UBM comprises: sputter, evaporation, chemical plating, plating etc.
5. the method for claim 1 is characterized in that, Fig. 1 is the Ga-In binary phase diagraml; As shown in the figure, the molar ratio scope of two kinds of metal ingredients is among the Ga-In: In 8%16%, and Ga 92%84%; The melting range of this composition alloy is 15 ℃-20 ℃, is liquid at normal temperatures.
6. like claim 1,5 described methods, it is characterized in that, in the scope that the liquid Ga-In alloy of normal temperature drip irrigation is centered on to dykes and dams, form normal temperature liquid state salient point.
7. the method for claim 1 is characterized in that, suitably heating under the condition of the Ga-In melting temperature that is lower than used composition; This moment, salient point was solid-state; With chip bump and the accurate contraposition of wiring plate electrode,, realize its adhesion to each die stress; An example is the pressure of 2-10kg, duration 5-20 second.
8. the method for claim 1 is characterized in that, carries out filling under the chip, and the material of filling has resin, silica gel etc.The method of filling comprises: drip irrigation method, cast gate injection, infusion process etc.Be cured subsequently, the method for curing comprises: UV-irradiation, heating etc.
9. method as claimed in claim 7 is characterized in that, operation will be carried out in vacuum environment.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201110382009XA CN102437063A (en) | 2011-11-25 | 2011-11-25 | Manufacturing method of flip chip with liquid salient points |
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| CN201110382009XA CN102437063A (en) | 2011-11-25 | 2011-11-25 | Manufacturing method of flip chip with liquid salient points |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105336829A (en) * | 2015-09-28 | 2016-02-17 | 厦门市三安光电科技有限公司 | Flip chip light-emitting diode structure and manufacturing method thereof |
| CN105489727A (en) * | 2016-01-18 | 2016-04-13 | 厦门市三安光电科技有限公司 | Bonded electrode structure of flip light-emitting diode (LED) chip, and manufacturing method thereof |
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| CN101194373A (en) * | 2005-06-09 | 2008-06-04 | 飞利浦拉米尔德斯照明设备有限责任公司 | Method of removing the growth substrate of a semiconductor light-emitting device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000088883A (en) * | 1998-09-09 | 2000-03-31 | Micronics Japan Co Ltd | Electric connecting device for electronic parts and manufacture thereof |
| US20020100973A1 (en) * | 2000-06-08 | 2002-08-01 | Salman Akram | Collar positionable about a periphery of a contact pad and around a conductive structure secured to the contact pads, semiconductor device components including same, and methods for fabricating same |
| CN101194373A (en) * | 2005-06-09 | 2008-06-04 | 飞利浦拉米尔德斯照明设备有限责任公司 | Method of removing the growth substrate of a semiconductor light-emitting device |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105336829A (en) * | 2015-09-28 | 2016-02-17 | 厦门市三安光电科技有限公司 | Flip chip light-emitting diode structure and manufacturing method thereof |
| WO2017054612A1 (en) * | 2015-09-28 | 2017-04-06 | 厦门市三安光电科技有限公司 | Flip-chip light emitting diode structure and manufacturing method |
| CN105336829B (en) * | 2015-09-28 | 2018-09-11 | 厦门市三安光电科技有限公司 | Inverted light-emitting diode (LED) structure and preparation method thereof |
| US10205057B2 (en) | 2015-09-28 | 2019-02-12 | Xiamen Sanan Optoelectronics Technology Co., Ltd. | Flip-chip light emitting diode and fabrication method |
| CN105489727A (en) * | 2016-01-18 | 2016-04-13 | 厦门市三安光电科技有限公司 | Bonded electrode structure of flip light-emitting diode (LED) chip, and manufacturing method thereof |
| CN105489727B (en) * | 2016-01-18 | 2018-06-19 | 厦门市三安光电科技有限公司 | The bonding electrode structure and production method of flip LED chips |
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