CN102426855A - 8-value memory cell embedded in DRAM storage matrix, and corresponding conversion circuit thereof - Google Patents
8-value memory cell embedded in DRAM storage matrix, and corresponding conversion circuit thereof Download PDFInfo
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- CN102426855A CN102426855A CN2011102809214A CN201110280921A CN102426855A CN 102426855 A CN102426855 A CN 102426855A CN 2011102809214 A CN2011102809214 A CN 2011102809214A CN 201110280921 A CN201110280921 A CN 201110280921A CN 102426855 A CN102426855 A CN 102426855A
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Abstract
The invention discloses an 8-value memory cell embedded in a DRAM storage matrix, and a corresponding conversion circuit thereof. The 8-value memory cell is composed of 3 NMOS tubes, 2 PMOS tubes, a storage capacitor Cj and a power source. An NMOS tube Qm1 and a current source Ij form a source follower FS, wherein a drain of the NMOS tube Qm1 is connected to a direct current power supply VDC, a source electrode of the NMOS tube Qm1 is connected to one terminal of the current source Ij, the other terminal of the current source Ij is connected to a negative direct current power supply VSS, and current from the current source Ij flows from the source electrode of the NMOS tube Qm1 to the negative direct current power supply VSS. A gate electrode of the NMOS tube Qm1 is connected to one terminal of the storage capacitor Cj. The main part of the 8-value memory cell is the NMOS tube source follower. The structure of the 8-value memory cell is simple. With the 8-value memory cell, the characteristics of the DRAM storage matrix are maintained, and BMVC and MBVC are realized. The 8-value memory cell has anti-interference capability and multi-valued information recoverability.
Description
Technical field
The invention belongs to the digital integrated circuit field, specifically a kind of 8 value storage unit and relevant change-over circuit thereof that embeds the DRAM storage matrix.
Background technology
Along with the develop rapidly of MOS integrated circuit technique, integrated scale is increasing, and integrated level is increasingly high, and some shortcomings appear in VLSI (VLSI (very large scale integrated circuits)): 1. at first on the VLSI substrate, wiring but takies the silicon area more than 70%; In PLD (like FPGA and CPLD), also need there be a large amount of interconnectors able to programme (to comprise the switch that is connected able to programme; Like fuse-type switch, anti-fuse-type switch, floating boom programmed element etc.); Each logic function block or I/O are coupled together; Accomplish the circuit of specific function, wiring (comprising that programming connects switch) has accounted for the very big cost of material.The proportion that reduces wiring cost becomes important problems.2. see from the information transmission aspect, adopt multi-valued signal can reduce the line number; To every line transmitting digital information, binary signal is to carry minimum a kind of of quantity of information, and multi-valued signal carries and contains much information in binary signal.3. see from the information stores aspect; Adopt multi-valued signal can improve information storage density; Particularly utilize metal-oxide-semiconductor grid capacitance canned data (being used for dynamic RAM DRAM); Because of same capacitance stores quantity of information is many-valued bigger than two-value, many-valued DRAM can improve information storage density greatly than two-value DRAM.The development of present many-valued device is extensively carried out, and Toshiba matches through the CMOS technology of 70nm and the many-valued technology of 2bit/ unit with Sandisk company, at 146mm
2Chip on realized the memory capacity of 8Gbit; Toshiba and U.S. SanDisk have delivered the 16gbitNAND flash memory through adopting the many-valued technology in 43nm technology and 2bit/ unit to realize.The 8Gbit product of Samsung exploitation adopts the CMOS technology of 63nm and the many-valued technology of 2bit/ unit.Succeed in developing and the commercialization of 4 value storeies is important steps of many-valued research, but needs control or change the switching threshold V that manages
Tn, changing threshold method is in semiconductor fabrication process, to use multistage ion implantation technique, or controls methods such as the amount of electrons control threshold value of the grid storage of swimming.Find to have succeeding in developing as yet more than the DRAM of 4 values.
Semiconductor memory can be divided into read only memory ROM and random access memory ram.And RAM is divided into two types on ambipolar and MOS type.The bipolar RAM operating rate is high, but manufacturing process is complicated, power consumption is big, integrated level is low, is mainly used in the occasion of high speed operation.MOS type RAM is divided into two kinds of static RAM SRAM and dynamic RAM DRAM (Dynamic Random Access Memory) again.The principle of DRAM canned data is based on the charge-storage effect of metal-oxide-semiconductor grid capacitance.Since the capacity very little (a few at the most usually pico farad) of grid MM CAP, and leakage current can not definitely equal zero, so the limited time that electric charge is preserved; Lose to avoid signal stored in order in time to replenish the electric charge of missing, must replenish electric charge regularly for the grid MM CAP, usually this operation is called and refreshes or regenerate, must be aided with the refresh control circuit of necessity during DRAM work.DRAM be by big rectangle memory cell array be used for the supportive logical circuit of array read and write, and the compositions such as refresh circuit of keeping integrity of data stored.The simplest available single tube dynamic storage cell in DRAM.Storage unit is to line up matrix type structure by row, row, deciphers respectively with two decoding schemes.X is called row decoding to decoding, its output line X
iBe called word line, it chooses all storage unit of delegation in the storage matrix.Y is called column decoding, its output line Y again to decoding
jBe called bit line.Generally DRAM is designed to word length L
W(promptly a word has L in the position
WThe position, as 1,4,8 or N position), address decoder is translated output X
iAnd Y
jExport when effective, simultaneously the L of a selected word
WIndividual (as 1,4,8 or N) storage unit, make these selected storage unit carry out read-write operation, and in each sense data, accomplished recovery the original institute of storage unit deposit data through the read/write control circuit.The input and output of DRAM read-write control circuit control data information.The control signal of outer bound pair storer has read signal R
D, write signal W
RWith chip selection signal C
SOr the like.The figure place of the inputoutput data of DRAM has 1, and 2,4 or N position.Except that the multidigit input and output, reduce the number of device pin when improving integrated level, the mode that high capacity DRAM usually adopts 1 input, 1 output and address timesharing to import has input buffer, output buffer and output latch etc. accordingly.
Prior art and existing problems:
1. the many-valued storage unit that in two-value DRAM storage matrix, embeds more than 4 values is difficult, and two-value data is by the having and do not have and decide of the electric charge of MM CAP, and is easy to read and write; Multi-valued signal is read and is write and will distinguish magnitude; Conventional amplifier forms serious distortion easily to multi-valued signal; Conventional sensor amplifier method is difficult to read multi-valued signal; 8 values that very difficult realization can embed two-value DRAM storage matrix and the storage unit circuit of K value DRAM arbitrarily, discovery has succeeding in developing more than the DRAM of 4 values as yet.Many-valued storage unit major part is a NMOS pipe source follower; Structure is extremely simple; Under the prerequisite that keeps the original characteristics of two-value DRAM, in order to embed more than the many-valued storage unit of 4 values among the two-value DRAM, can not be by the many-valued memory cell structure of the simple consideration of traditional approach; Many-valued storage unit and the problem that two-value DRAM storage matrix matches be must consider simultaneously, two-value-many-valued change-over circuit and many-valued-two-value change-over circuit comprised.
2. realizing multivalued circuit; Comprise in realization two-value-many-valued change-over circuit and the many-valued-two-value change-over circuit that prior art control metal-oxide-semiconductor threshold value has very big shortcoming: 1. can only control the amplitude of threshold value, can not realize the interval character of opening of metal-oxide-semiconductor threshold; As require metal-oxide-semiconductor only when input just conducting in the voltage range of regulation; Claim that this voltage range is between zone, similar have only metal-oxide-semiconductor conducting when importing in the height interval, and only when input metal-oxide-semiconductor conducting when hanging down the interval.Multivalued gate must have the metal-oxide-semiconductor of multiple unlatching character, just can make circuit structure the simplest, yet only controls the technology of threshold amplitude at present, makes the multivalued circuit structural difference very big, and complex structure influences its realization.2. control the amplitude limited (because of ion implantation concentration is limited) of threshold value, unlatching resolution is very low; And control the performance that threshold amplitude regular meeting changes metal-oxide-semiconductor in the technology, for example the sharp increase that causes cutting off electric current is returned in the reduction of threshold voltage, the V that the adjustment of threshold voltage is influential, stable with stability to the performance of pipe
TnAnd V
TpExtremely important.To many-valued memory, the amount of electrons of injecting the grid that swims is a continually varying, needs the control of very fine ground, and each threshold voltage level does not still reach quasi-stationary state.Therefore the voltage-type multivalued circuit is not more than 4 value circuit at present, and more multivalued circuit is used difficulty.3. need increase ion and inject extra procedure, can only in semiconductor fabrication process, control threshold value, both increase process complexity, can not control threshold value by the user in the back again, or non-programmable to threshold users.
Summary of the invention
The present invention seeks to disclose a kind of 8 value storage unit and relevant change-over circuit thereof of the DRAM of embedding storage matrix, wherein the relevant change-over circuit of 8 value storage unit comprises 2-8 change-over circuit BMVC and 8-2 change-over circuit MBVC.
Above-mentioned purpose realizes through following technical scheme:
1. 8 value storage unit circuits of a kind of DRAM of embedding storage matrix of the present invention are achieved in that referring to circuit shown in Figure 28 value storage unit circuits of described embedding DRAM storage matrix are by 3 NMOS pipe Q
M1, Q
M2, Q
M4, 2 PMOS pipe Q
M3, Q
M5With MM CAP C
jAnd power supply is formed; In 8 value storage unit circuits, manage Q
M1With current source I
jConstitute source follower F
S: pipe Q
M1Drain electrode meet direct supply V
DC, V
DC=1.8V, pipe Q
M1Source electrode meet current source I
jAn end, this junction is F
SOutput D
Mij, I
jThe negative direct supply V of another termination
SS, V
SS=-3.5V, I
jElectric current is by pipe Q
M1Source electrode flow to V
SSPipe Q
M1Grid meet MM CAP C
jAn end, this junction is F
SInput D
MCij, capacitor C
jAnother termination V
SSIn 8 value storage unit circuits, manage Q
M2And Q
M3, and Q
M4And Q
M5Constitute cmos transmission gate separately: pipe Q
M2And Q
M3Drain electrode join, source electrode also joins, manages Q
M4And Q
M5Drain electrode join, source electrode also joins, manages Q
M2And Q
M4Grid meet capable selection wire X
0i, pipe Q
M3And Q
M5Grid meet X
0iNon-
Manage Q in 2 cmos transmission gates
M2And Q
M3Constitute and import transmission gate TG into
1, pipe Q
M4And Q
M5Constitute and spread out of transmission gate TG
2: TG
1Input meet sense bit line Y
WRj, TG
1Output meet F
SInput D
MCij, TG
2Input meet F
SOutput D
Mij, TG
2Output meet sense bit line Y
RDjAs row selection wire X
0iDuring for high level, transmission gate TG
1And TG
2Conducting, write bit line 8 value signal Y
WRjTransmission gate TG through conducting
1Be transferred to F
SInput D
MCij, also promptly be transferred to pipe Q
M1Grid, with 8 value signal D
MCijDeposit MM CAP C in
j, the message pick-up function of completion 8 value storage unit circuits; Then as row selection wire X
0iDuring for low level, transmission gate TG
1And TG
2End capacitor C
jWith the external world be direct current open circuit, MM CAP C
j8 value signal D of storage
MCijRemain unchanged, accomplish the information storage function of 8 value storage unit circuits; Capacitor C
j8 value signal D of storage
MCijThrough F
SForm 8 corresponding value source output D
Mij, X appears instantly constantly once more
0iDuring for high level, transmission gate TG
2Conducting is with C
jStorage signal D
MCij8 corresponding value signal D
MijTG through conducting
2Outwards output, the message sending function of completion 8 value storage unit circuits; 8 value storage unit circuits except that the read and write of accomplishing 8 value canned datas, are also accomplished refreshing of 8 value canned datas through read-write control circuit.
2. the 2-8 change-over circuit BMVC of 8 value storage unit of a kind of DRAM of the embedding storage matrix that draws according to 8 value storage unit circuits of the above-described a kind of DRAM of embedding storage matrix, as shown in Figure 4: by 7 door f
J7～f
J1, 7 PMOS pipe Q
A7～Q
A1With 6 silicon diode D
A7～D
A2And the power supply composition, BMVC has 32 values input b
J+2, b
J+1, b
jWith 18 value write bit line output Y
WRj7 door f
J7～f
J1The output logic formula be:
Promptly the door f
J7Be to be input as b
J+2, b
J+1, b
jSheffer stroke gate, the door f
J6Be to be input as b
J+2, b
J+1Sheffer stroke gate, the door f
J5Be to be input as b
J+2, b
jSheffer stroke gate, the door f
J4Be to be input as b
J+2Not gate, the door f
J3Be to be input as b
J+1, b
jSheffer stroke gate, the door f
J2Be to be input as b
J+1Not gate, the door f
J1Be to be input as b
jNot gate; The WV of Sheffer stroke gate and not gate is V
DC, V
DC=1.8V; Pipe Q
A7～Q
A1Grid meets f separately
J7～f
J1, diode D
A7～D
A2Positive pole take over Q separately
A6～Q
A1Drain electrode, diode D
A7～D
A2Negative pole take over Q separately
A7～Q
A2Drain electrode, Q
A7Drain electrode meet current source I
jAn end, this junction is write bit line output Y
WRj, I
jAnother termination negative supply voltage V
SS, V
SS=-3.5V, I
jElectric current is by Y
WRjFlow to V
SSPipe Q
A7～Q
A1Source electrode meet supply voltage V
DC, V
DC=1.8V, the diode current flow pressure drop is V
dThe input/output relation of BMVC is: 1. as input b
J+2b
J+1b
j=111 o'clock, f
J7=0, pipe Q
A7Conducting, Y
WRjOutput voltage V
YWRj=V
DC, presentation logic 7; 2. as input b
J+2b
J+1b
j=110 o'clock, f
J7=1 and f
J6=0, pipe Q
A7End pipe Q
A6Conducting, V
YWRj=V
DC-V
d, presentation logic 6; 3. as input b
J+2b
J+1b
j=101 o'clock, f
J7=f
J6=1 and f
J5=0, pipe Q
A7, Q
A6End pipe Q
A5Conducting, V
YWRj=V
DC-2V
d, presentation logic 5; 4. as input b
J+2b
J+1b
j=001 o'clock, f
J7=f
J6=f
J5=f
J4=f
J3=f
J2=1 and f
J1=0, pipe Q
A7～Q
A2End pipe Q
A1Conducting, V
YWRj=V
DC-6V
d, presentation logic 1; 5. as input b
J+2b
J+1b
j=000 o'clock, f
J7=f
J6=f
J5=f
J4=f
J3=f
J2=f
J1=1, all manage Q
A7～Q
A1All end V
YWRj=V
SS, presentation logic 0; Binary numeral 000～111 corresponding decimal system number is 0～7, as input b
J+2b
J+1b
j=000～111 o'clock, Y
WRj Output voltage V
YWRj8 logic level v (0)～v (7) is arranged, and presentation logic 0～7 separately, v (0)=V
SS, v (k)=V
DC-(7-k) V
d, k=1～7;
3. the 8-2 value change-over circuit MBVC of 8 value storage unit of a kind of DRAM of the embedding storage matrix that draws according to 8 value storage unit circuits of the above-described a kind of DRAM of embedding storage matrix, as shown in Figure 5: by 4 band general formula variable threshold PMOS pipe G
B0mj, G
B1mj, G
B2mj, G
B3mj, 3 high general formula variable threshold PMOS pipe G
H4mj, G
H5mj, G
H6mjWith 3 resistance R
0mj, R
1mj, R
2mjForm, MBVC has 18 value sense bit line input Y
RDjWith 32 value output m
J+2, m
J+1, m
j7 pipe G
B0mj～G
B3mjAnd G
H4mj～G
H6mjSource electrode all meet power supply V
DC, V
DC=1.8V; 4 pipe G
B0mj～G
B3mjGrid respectively hang oneself band logical-band resistance variable threshold circuit meets Y
RDj, 3 pipe G
H4mj～G
H6mjThe grid high pass-low pass variable threshold circuit of respectively hanging oneself meet Y
RDj, pipe G
H4mjDrain electrode and resistance R
2mjAn end be connected, this junction is as 2 value output m
J+2, resistance R
2mjOther end ground connection; 2 pipe G
B0mj, G
H5mjDrain electrode and resistance R
1mjAn end be connected, this junction is as 2 value output m
J+1, resistance R
1mjOther end ground connection; 4 pipe G
H6mjAnd G
B1mj～G
B3mjDrain electrode and resistance R
0mjAn end be connected, this junction is as 2 value output m
j, resistance R
0mjOther end ground connection; 7 pipe G
H4mj～G
H6mjAnd G
B0mj～G
B3mjSatisfy: 1. manage G
H4mjAt Y
RDjInput is merely logic 4～7 o'clock conducting, otherwise ends, and promptly manages G
H4mjHigh pass threshold th
J4For comprising the high interval of logic level v (4); 2. manage G
H5mjAt Y
RDjInput is merely logic conducting in 6,7 o'clock, otherwise ends, and promptly manages G
H5mjHigh pass threshold th
J5For comprising the high interval of logic level v (6); 3. manage G
H6mjAt Y
RDjConducting when input is merely logic 7, otherwise end, G promptly managed
H6mjHigh pass threshold th
J6For comprising the high interval of logic level v (7); 4. manage G
B0mjAt Y
RDjInput is merely logic conducting in 2,3 o'clock, otherwise ends, and promptly manages G
B0mjThe logical threshold tb of band
J0For between the zone that only comprises 2 logic level v (2), v (3); 5. manage G
B1mjAt Y
RDjConducting when input is merely logic level 1, otherwise end, G promptly managed
B1mjThe logical threshold tb of band
J0For between the zone that only comprises logic level v (1); 6. manage G
B2mjAt Y
RDjConducting when input is merely logic level 3, otherwise end, G promptly managed
B2mjThe logical threshold tb of band
J0For between the zone that only comprises logic level v (3); 7. manage G
B3mjAt Y
RDjConducting when input is merely logic level 5, otherwise end, G promptly managed
B3mjThe logical threshold tb of band
J0For between the zone that comprises logic level v (5); The input/output relation of MBVC is: Y is worked as in (1)
RDjWhen being input as logic 7, pipe G
H4mj, G
H5mj, G
H6mjConducting, output m
J+2m
J+1m
j=111; (2) work as Y
RDjWhen being input as logic 6, pipe G
H4mj, G
H5mjConducting, other pipe ends, output m
J+2m
J+1m
j=110; (3) work as Y
RDjWhen being input as logic 5, pipe G
H4mj, G
B3mjConducting, other pipe ends, output m
J+2m
J+1m
j=101; (4) work as Y
RDjWhen being input as logic 4, pipe G
H4mjConducting, other pipe ends, output m
J+2m
J+1m
j=100; (5) work as Y
RDjWhen being input as logic 3, pipe G
B0mj, G
B2mjConducting, other pipe ends, output m
J+2m
J+1m
j=011; (6) work as Y
RDjWhen being input as logic 2, pipe G
B0mjConducting, other pipe ends, output m
J+2m
J+1m
j=010; (7) work as Y
RDjWhen being input as logical one, pipe G
B1mjConducting, other pipe ends, output m
J+2m
J+1m
j=001; (8) work as Y
RDjWhen being input as logical zero, all pipes all end, output m
J+2m
J+1m
j=000; Also promptly work as Y
RDjBe input as logical zero～7 o'clock, draw corresponding two-value and be output as 000～111.
8 value storage unit and relevant change-over circuit thereof that the present invention embeds the DRAM storage matrix also have some technical characterictics like this:
(1) the described a kind of relevant change-over circuit that embeds 8 value storage unit of DRAM storage matrix of above 1-3, V
DCOr=1.5V, V
SSOr=-4.0V.
(2) the described a kind of relevant change-over circuit that embeds 8 value storage unit of DRAM storage matrix of above 1-3, current source I
jOr be resistance R
j
8 value storage unit major parts are NMOS pipe source followers, and structure is extremely simple, under the prerequisite that keeps DRAM storage matrix characteristics, realize BMVC and MBVC, can be to X
iBe high level and Y
iFor low level row refresh, to X
iAnd Y
iAll be that the row of high level carry out that write and read is double to be refreshed; BMVC and MBVC have good quantification shaping operation, as MM CAP C
jWhen change in voltage is little, be easy to recover prime information, have antijamming capability and multilevel information recovery capability.Be mainly used in FPGA, CPLD, half or formulate VLSI and other digital IC technical fields such as ASIC and storer entirely.
Description of drawings
Fig. 1. embed the circuit diagram of 2 value DRAM storage matrix for first kind of 8 value storage unit of the present invention;
Fig. 2. be first kind of 8 value storage unit M of the present invention
IjCircuit diagram;
Fig. 3. be current source I among Fig. 2
jUse resistance R instead
jSecond kind of 8 value storage unit M
IjCircuit diagram;
Fig. 4. be the circuit diagram of a kind of 2-8 value change-over circuit BMVC of the present invention;
Fig. 5. be the circuit diagram of a kind of 8-2 value change-over circuit MBVC of the present invention;
Fig. 6. a kind of PMOS pipe racks relevant for the present invention leads to-band resistance variable threshold circuit and graphical diagram;
Fig. 7. be first kind of relevant PMOS pipe high pass-low pass variable threshold circuit and graphical diagram of the present invention;
Fig. 8. be second kind of relevant PMOS pipe high pass-low pass variable threshold circuit and graphical diagram of the present invention;
Fig. 9. be existing a kind of many accurate mirror-image constant flow source circuit diagrams of output and graphical diagram;
Figure 10. the circuit that embeds 2 value DRAM storage matrix for 8 value storage unit shown in Figure 1 is at X
iAnd Y
jDuring for high level, b
J+2, b
J+1, b
j, Y
WRj, Y
RDj, m
J+2, m
J+1, m
jSuccessively discrete up and down oscillogram;
Figure 11. for 2-8 value change-over circuit BMVC shown in Figure 4 at X
iAnd Y
jDuring for high level, b
J+2, b
J+1, b
j, f
J7, f
J6, f
J5, f
J4, f
J3, f
J2, f
jSuccessively discrete up and down oscillogram;
Figure 12. for 2-8 value change-over circuit BMVC shown in Figure 4 at X
iAnd Y
jDuring for high level, Y
WRj, D
MCij, f
J7, f
J6, f
J5, f
J4, f
J3, f
J2, f
J1Successively discrete up and down oscillogram;
Figure 13. for 8-2 value change-over circuit MBVC shown in Figure 5 at X
iAnd Y
jDuring for high level, D
Mij, Y
RDj, th
J4, th
J5, tb
J0, tb
J1, tb
J2, tb
J3, th
J6Successively discrete up and down oscillogram;
Figure 14. for being that 8-2 value change-over circuit MBVC shown in Figure 5 is at X
iAnd Y
jDuring for high level, m
J+2, m
J+1, m
j, th
J4, th
J5, tb
J0, tb
J1, tb
J2, tb
J3, th
J6Successively discrete up and down oscillogram;
Figure 15. for band shown in Figure 6 leads to-is with reference voltage V in the resistance variable threshold circuit
Ref1And V
Ref0Get 4 class values: 2.2V and 3.85V, 2.2V and 3.3V, 2.2V and 2.2V, 3.3V and 2.2V successively, pipe Q
5The output of drain electrode is followed successively by tb
J0, tb
J1, tb
J2, tb
J3, input V
xInput and output oscillogram during for triangular wave bin;
Figure 16. for band shown in Figure 6 leads to-is with reference voltage V in the resistance variable threshold circuit
Ref1And V
Ref0Get 4 class values: 2.2V and 3.85V, 2.2V and 3.3V, 2.2V and 2.2V, 3.3V and 2.2V successively, pipe Q
5The output of grid is followed successively by t/b
J0, t/b
J1, t/b
J2, t/b
J3, input V
xInput and output oscillogram during for triangular wave bin;
Figure 17. be reference voltage V in high pass shown in Figure 7-low pass variable threshold circuit
Ref1Be followed successively by 3.85V, 2.2V, V in high pass shown in Figure 8, the low pass variable threshold circuit
Ref0Be followed successively by 1.65V and 3.3V, 4 kinds with reference to pipe Q under the voltage
5The output of drain electrode is followed successively by t/h
J4, t/h
J5, th
J5, th
J6, input V
xInput and output oscillogram during for triangular wave bin;
Figure 18. be reference voltage V in high pass shown in Figure 7-low pass variable threshold circuit
Ref1Be followed successively by 3.85V, 2.2V, V in high pass shown in Figure 8-low pass variable threshold circuit
Ref0Be followed successively by 1.65V and 3.3V, 4 kinds with reference to pipe Q under the voltage
5The output of grid is followed successively by th
J4, th
J5, t/h
J5, t/h
J6, input V
xInput and output oscillogram during for triangular wave bin;
Figure 19. embed the circuit diagram of 2 value DRAM storage matrix for the 2nd kind of 8 value storage unit of the present invention;
Embodiment
The concrete description of contents of the present invention is following:
(1) by total inventive concept unified design 8 value storage unit circuits and two kinds of circuit that are closely related (comprising 2-8 change-over circuit BMVC and 8-2 change-over circuit MBVC) thereof, shows like Fig. 2～5; 8 value storage unit circuit major parts are that NMOS pipe source follower shows like Fig. 2 and Fig. 3; Structure is extremely simple; It is to realize under the constant basically prerequisite of former DRAM storage matrix structure keeping that this 8 value storage unit circuit embeds the DRAM storage matrix; Outer input and output remain 2 value informations, and the storage of 8 value storage unit circuits is 8 value informations; Embed in the DRAM storage matrix in order to accomplish 8 value storage unit circuits; Except designing 8 value storage unit circuits; Design that must unified design inseparable with 2-8 change-over circuit BMVC and 8-2 change-over circuit MBVC interdependence, like Fig. 1 and shown in Figure 19, otherwise; It is absolutely not realization that the open-and-shut 8 value storage unit of structure embed the DRAM storage matrix, and showing must be by total inventive concept unified design 8 value storage unit circuits and indivisible BMVC and MBVC; If the unified design that does not have BMVC and MBVC to match embeds 8 value storage unit circuits and loses feasibility, for example; BMVC and MBVC design are improper, might be worth lost part multilevel information in the storage unit circuits 8, thus the feasibility of losing; By a unified design of total inventive concept is the main and outstanding characteristics of the present invention, and these characteristics are main with information characteristic, comprise the multilevel information storage; Receive, transmission and multilevel information conversion etc., the DRAM input and output are two value informations; What 8 value storage unit circuits were stored is 8 value informations, and the two information type is inconsistent, so the conversion between 2 value informations and 8 value informations is the prerequisite of 8 value storage unit circuit work.Attention: storage unit circuit is simple in structure, and quantity is very big, and BMVC and MBVC structure are remarkable, and its quantity should be lacked as far as possible; Can not storage unit circuit, BMVC and MBVC be classified as a kind of integrated circuit (their quantity does not wait), otherwise (imposing quantity to equate), cost is high and impracticable; 8 value storage unit circuits, BMVC and MBVC spatially quantitatively are three kinds of circuit of different interdependence, and they are indivisible integral body by information characteristics, can only be by the unified three kinds of circuit that are closely related that design of total inventive concept.V in the DRAM storage array shown in Figure 1
DC=1.8V, V
SS=-3.5V, V
DRead-write control circuit in the empty frame in=0V bottom is revised on Figure 19 basis to some extent; V in the another kind of DRAM storage array shown in Figure 19
DC=5.5V, V
SS=0V, V
D=4V, top selection wire X
iDistinguish to some extent with Fig. 1, also distinguish to some extent with Fig. 1 in the empty frame in bottom.
(2) 8 value storage unit circuit storage unit circuits of the present invention show like Fig. 2 and Fig. 3, have multilevel information storage, receive and send three functions: 1. message pick-up: as row selection wire X
0iDuring for high level, transmission gate TG
1Conducting, write bit line 8 value signal Y
WRjBe transferred to F
SInput D
MCij, also be about to 8 value signal D
MCijDeposit MM CAP C in
j(annotate: TG
1And TG
2Be cmos transmission gate, but cmos transmission gate transmitted in both directions signal, so TG
1During conducting, no matter capacitor C
jThe former information size of depositing all can make write bit line Y
WRjThe undistorted capacitor C that is sent to of 8 value informations
j, C
jReceive undistorted 8 value information D
MCij, show that 8 value storage unit circuits have the message pick-up function; 2. information stores: as row selection wire X
0iDuring for low level, transmission gate TG
1End TG
1And F
SThe direct current resistance of input is almost infinity, C
jWith the external world be direct current open circuit, C
j8 value signal D of storage
MCijRemain unchanged, show that 8 value storage unit circuits have information storage function; 3. information is sent: source follower F
SVoltage amplification factor near 1, F
SExcept direct current offset △ was arranged, the input and output waveform was approaching, F to input in output
SBe input as C
j8 value signal D of storage
MCij, through F
SForm the 8 value output signal D that waveform is close
Mij, X appears instantly constantly once more
0iDuring for high level, TG
2Conducting is with C
jSignal stored D
MCij8 corresponding value signal D
MijTG through conducting
2Outwards output shows that 8 value storage unit circuits have message sending function; Annotate: X
iAnd Y
iHigh level and the low level nearly V that respectively does for oneself
DCWith 0; Because of TG
1And TG
2Be transmission 8 value signals, TG
1And TG
2The control signal amplitude is consistent with 8 value signal amplitudes, so by row selection wire X
iProduce the capable selection wire X of the amplification of another homophase
0i, X
0iHigh level and the low level nearly V that respectively does for oneself
DCAnd V
SSFor simplifying the logic behavior descriptive statement, only write X sometimes
iAnd X
0iOne of, omit another.
(3) 8 value storage unit circuits of the present invention can be accomplished the refresh function of 8 value canned datas in addition through the write functionality of read-write control circuit completion 8 value canned datas, referring to Fig. 1, as row selection wire X
iBe high level (X then
0iBe high level), from storage matrix, choose all storage unit circuits (the transmission gate TG of this delegation
1And TG
2Conducting); As column selection line Y
jBe high level, from the above-mentioned delegation that chooses, select the L of these row again
WThe position storage unit circuit, word length L
W>=3, make these selected cells through the read/write control circuit, logical with data I/O termination; Preferably get L
WBe 3 integral multiple (L
W=3P), then begin by the binary number lowest order, per 3 is one group; The P group has one 8 value storage unit circuit by every winding shown in Figure 1, a BMVC and a MBVC altogether; The total P of these row 8 value storage unit circuits, P BMVC and P MBVC promptly embed P 8 value storage unit circuits; If L
W(L when not being 3 integral multiple
W=3P+r), except that embedding P 8 value storage unit circuits, still (control signal of the NMOS gate pipe that the transmission of 2 value informations is used is X with former 2 value storage unit circuits in remaining r position (r＜3)
i).Each provisional capital embeds 8 value storage unit circuits as stated above, and general the employing pressed X
iFor the delegation of high level refreshes, to X
iBe high level and Y
iFor low level row refresh, to X
iAnd Y
iAll be that the row of high level carry out that write and read is double to be refreshed.
Embodiment 1:2-8 value change-over circuit BMVC realizes the explanation of function.
Embodiment 2:8-2 value change-over circuit MBVC realizes the explanation of function.
Referring to Fig. 5, consider pipe G
B0mj～G
B3mjGrid logical through being with-band resistance variable threshold circuit meets input Y
RDj, pipe G
H4mj～G
H6mjGrid through high pass-low pass variable threshold circuit connect the input Y
RDj, wherein manage G
H4mjAt Y
RDjBe input as logic 4～7 o'clock conducting, pipe G
H5mjAt Y
RDjBe input as logic conducting in 6,7 o'clock, pipe G
H6mjAt Y
RDjConducting when input is merely logic 7, pipe G
B0mjAt Y
RDjInput is merely logic conducting in 2,3 o'clock, pipe G
B1mjAt Y
RDjConducting when input is merely logic level 1, pipe G
B2mjAt Y
RDjConducting when input is merely logic level 3, pipe G
B3mjAt Y
RDjOutput m is also considered in conducting when input is merely logic level 5
J+2Take over G
H4mjDrain electrode, output m
J+1Meet G
H5mjAnd G
B0mjDrain electrode, output m
jMeet G
B1mj, G
B2mj, G
B3mjAnd G
H6mjDrain electrode, the source electrode of all pipes all meets V
DC, V
DC=1.8V as long as a pipe conducting is wherein arranged, promptly should drain and the source electrode conducting by pipe, and this pipe drain electrode output is exactly high level (1 level), so the input/output relation of MBVC is: Y is worked as in (1)
RDjWhen being input as logic 7, pipe G
H4mj, G
H5mj, G
H6mjConducting, output m
J+2m
J+1m
j=111; (2) work as Y
RDjWhen being input as logic 6, pipe G
H4mj, G
H5mjConducting, other pipe ends, output m
J+2m
J+1m
j=110; (3) work as Y
RDjWhen being input as logic 5, pipe G
H4mj, G
B3mjConducting, other pipe ends, output m
J+2m
J+1m
j=101; (4) work as Y
RDjWhen being input as logic 4, pipe G
H4mjConducting, other pipe ends, output m
J+2m
J+1m
j=100; (5) work as Y
RDjWhen being input as logic 3, pipe G
B0mj, G
B2mjConducting, other pipe ends, output m
J+2m
J+1m
j=011; (6) work as Y
RDjWhen being input as logic 2, pipe G
B0mjConducting, other pipe ends, output m
J+2m
J+1m
j=010; (7) work as Y
RDjWhen being input as logical one, pipe G
B1mjConducting, other pipe ends, output m
J+2m
J+1m
j=001; (8) work as Y
RDjWhen being input as logical zero, all pipes all end, output m
J+2m
J+1m
j=000; Expression Y
RDjInput logic 0～7 o'clock draw corresponding two-value output 000～111.Annotate: corresponding band leads to-is with in resistance variable threshold circuit and the high pass-low pass variable threshold circuit gets V
DC=1.8V, V
SS=-3.5V, V
D=0V.
Embodiment 3: to the explanation of Pspice computer simulation waveform Figure 10～14 of Fig. 3～5.
Figure 10 be 8 value storage unit embed 2 value DRAM storage matrix circuit at X
iAnd Y
jDuring for high level, b
J+2, b
J+1, b
j, Y
WRj, Y
RDj, m
J+2, m
J+1, m
jSuccessively discrete up and down in order oscillogram is found out by figure, as the input b of BMVC
J+2b
J+1b
jDuring=000～111 (top 3 waveforms), BMVC exports Y
WRjBe 8 value signals 0～8 (the 4th waveforms), the Y that this 8 value signal draws through 8 value storage unit
RDj(the 5th waveform), Y
RDjBe input to MBVC, last MBVC output m
J+2m
J+1m
j=000～111 (following 3 waveforms), MBVC have 32 value output m
J+2m
J+1m
j3 the 2 value input b of waveform and BMVC
J+2b
J+1b
jWaveform is identical; Annotate: X
iAnd Y
jHigh level and the low level nearly V that respectively does for oneself
DCWith 0; Because of TG
1And TG
2Be transmission 8 value signals, TG
1And TG
2The control signal amplitude is consistent with 8 value signal amplitudes, so by X
iProduce the capable selection wire X of the amplitude increase of another homophase
0i, X
0iHigh level and the low level V that respectively does for oneself
DCAnd V
SSAs row selection wire X
iWhen being high level, corresponding X
0iAlso be high level, for easy, accompanying drawing is all by X
iFor high-low level is explained.
Figure 11 for 2-8 value change-over circuit BMVC at X
iAnd Y
jDuring for high level, b
J+2, b
J+1, b
j, f
J7, f
J6, f
J5, f
J4, f
J3, f
J2, f
jSuccessively discrete up and down oscillogram; Input b as BMVC
J+2b
J+1b
jDuring=000～111 (top 3 waveforms), find out 7 door f among the BMVC by Figure 11
J7, f
J6, f
J5, f
J4, f
J3, f
J2, f
jOutput waveform (following 7 waveforms), f
J7～f
J1Receive pipe Q separately
A7～Q
A1Grid; Figure 12 for 2-8 value change-over circuit BMVC at X
iAnd Y
jDuring for high level, Y
WRj, D
MCij, f
J7, f
J6, f
J5, f
J4, f
J3, f
J2, f
J1Successively discrete up and down oscillogram, pipe Q
A7～Q
A1At f
J7～f
J1Under the effect of (following 7 waveforms), Y
WRjOutput has 8 logic level v (0)～v (7) (top the 1st waveform), and counterlogic 0～7 separately, simultaneously Y
WRjBe transferred to F
SInput D
MCij, D
MCij8 identical logic levels (top the 2nd waveform) are arranged; Figure 13 for 8-2 value change-over circuit MBVC at X
iAnd Y
jDuring for high level, D
Mij, Y
RDj, th
J4, th
J5, tb
J0, tb
J1, tb
J2, tb
J3, th
J6Successively discrete up and down oscillogram, D
MCijThrough F
SForm the 8 value emitter-base bandgap gradings output D that waveform is close
Mij(top the 1st waveform), D
MijTG through conducting
2Outwards export Y
RDj, Y
RDjWaveform and D
MijWaveform identical (top the 2nd waveform); MBVC is at Y
RDjEffect generates 4 logical threshold signal tb of band down
J0, tb
J1, tb
J2, tb
J3(following the 2nd～5 waveform reciprocal) generates 3 high pass threshold signal th
J4, th
J5, th
J6(the 3rd, 4 waveforms of positive number and following the 1st waveform reciprocal); Figure 14 for 8-2 value change-over circuit MBVC at X
iAnd Y
jDuring for high level, m
J+2, m
J+1, m
j, th
J4, th
J5, tb
J0, tb
J1, tb
J2, tb
J3, th
J6Successively discrete up and down oscillogram is at threshold signal th
J4, th
J5, tb
J0, tb
J1, tb
J2, tb
J3, th
J6Effect is (following the 1st～7 waveform reciprocal) down, draws MBVC output m
J+2, m
J+1, m
jWaveform (top the 1st～3 waveform); Can find out that MBVC exports m
J+2, m
J+1, m
jWaveform and above-mentioned BMVC input b
J+2, b
J+1, b
jWaveform be identical, show that BMVC converts the input of 32 values into 8 value signal Y
WRj, this 8 value signal deposits 8 value storage unit in, and 8 value storage unit produce Y
RDj, MBVC converts 8 value signals into 32 value signals again.
Embodiment 4:PMOS pipe racks leads to-is with the explanation of resistance and high pass-low pass variable threshold circuit function:
Referring to PMOS pipe racks shown in Figure 6 logical-band resistance variable threshold circuit (Fig. 6,7,8 direct supply V
DC=5.5V, V
SS=0V, V
D=4.0V), V
Ex1=V
Ref1-V
DC+ V
Tn1+ | V
Tp2|, V
Ex0=V
Ref0-V
DC-V
Tn3-| V
Tp4|, 1. work as V
Ex1＞V
x-V
DC＞V
Ex0When (between zone), pipe Q
1, Q
2Branch road and pipe Q
3, Q
4The branch road full cut-off, Q
B1Conducting is (V between zone
Ex0, V
Ex1); Be connected to band and lead to-be with the PMOS pipe Q that hinders the variable threshold circuit
B1Be called band general formula variable threshold PMOS pipe, tb=(V
Ex0, V
Ex1), claim that tb is the logical threshold of band; 2. work as V
Ex1＞V
x-V
DC＞V
Ex0When (between zone), Q
1, Q
2Branch road and Q
3, Q
4Branch road has a branch road conducting, Q
R0End, otherwise, do not satisfy V
Ex1＞V
x-V
DC＞V
Ex0When (outer between zone), Q
R0Conducting; Be connected to band and lead to-be with the PMOS pipe Q that hinders the variable threshold circuit
R0Be called band resistance formula variable threshold PMOS pipe, t/b=(V
Ex0, V
Ex1), claiming that t/b is band resistance threshold, logical threshold tb of band and band resistance threshold t/b are distinguished by symbol ' b ' and '/b '.
Referring to first kind of PMOS pipe high pass-low pass variable threshold circuit shown in Figure 7, work as V
x-V
DC＞V
Ex1When (high interval), pipe Q
1, Q
2The branch road conducting, Q
H1Conducting, Q
L0End; Be connected to the PMOS pipe Q of high pass-low pass variable threshold circuit
H1Be called high general formula variable threshold PMOS pipe, th=(＞V
Ex1), th is called the high pass threshold, is connected to the PMOS pipe Q of high pass-low pass variable threshold circuit
L0Be called low general formula variable threshold PMOS pipe, t/h=(＜V
Ex1), t/h is called the low pass threshold, and high pass threshold th and low pass threshold t/h are distinguished by symbol ' h ' and '/h '.Referring to second kind of PMOS pipe high pass-low pass variable threshold circuit shown in Figure 8, work as V
x-V
DC≤V
Ex0When (low interval), pipe Q
3, Q
4The branch road conducting, Q
L0Conducting, Q
H1End; Be connected to the PMOS pipe Q of high pass-low pass variable threshold circuit
H1And Q
L0The high pass of respectively calling oneself formula and low general formula variable threshold PMOS pipe, th=(＞V
Ex0), t/h=(＜V
Ex0), t/h is called the low pass threshold.Annotate: above-mentioned band leads to threshold, band resistance threshold, direct supply V in high pass threshold and the low pass threshold
DC=5.5V, V
SS=0V, V
D=4.0V, V
DC-V
SS=5.5V, this moment, the substrate of PMOS pipe met supply voltage V
DC(being maximum potential), the substrate ground connection (being minimum noble potential) of NMOS pipe; General V
xBe the input voltage of (0V) relatively, if get V
DC=1.8V, V
SS=-3.5V, V
D=0V, V
DC-V
SS=5.3V, then the substrate of PMOS pipe meets supply voltage V
DC(being maximum potential), the substrate of NMOS pipe meets V
SS(being minimum noble potential), reference voltage range and threshold interval also change into will be at V
DCAnd V
SSBetween value.
The logical threshold of band, band resistance threshold, high pass threshold and low pass threshold comprise voltage range and open two attributes of character, are marked with symbol tb at the metal-oxide-semiconductor grid, t/b, th or t/h represent its attribute.For simplification is write, the threshold control signal of metal-oxide-semiconductor grid is used threshold signal tb, and threshold signal t/b, threshold signal th or threshold signal t/h represent, add the threshold control signal that ' threshold signal ' represented this grid before the promptly above-mentioned symbol.Change V
Ref1Make V
Ex1Change V
Ex1=V
Ref1-V
DC+ V
Tn1+ | V
Tp2|) can not realize V little
SS-V
DC+ V
Tn1+ | V
Tp2| upper threshold value V
Ex1Change V
Ref0Make V
Ex0Change V
Ex0=V
Ref0-V
DC-V
Tn3-| V
Tp4| can not realize greater than-V
Tn3-| V
Tp4| lower threshold value V
Ex0, often need to be used with two kinds of PMOS pipe high pass-low pass variable threshold circuit.R in Fig. 6～8
1Available constant current source I
1Replace (electric current I
1By V
DCFlow to pipe Q
1And Q
3Drain electrode), annotate: resistance R among the figure
0Also available NMOS pipe Q
0Replace (Q
0Grid meets Q
5Grid, Q
0Drain electrode meets Q
5Drain electrode, Q
0Source electrode meets V
D, promptly replace back Q
0And Q
5Constitute the CMOS phase inverter).
Embodiment 5: to Fig. 6, and the explanation of 7,8 Pspice computer simulation waveform Figure 15～18.
The PMOS pipe racks leads to-band resistance variable threshold circuit diagram 6 (V among Fig. 6,7,8
DC=5.5V, V
SS=0V, V
D=4.0V), at reference voltage V
Ref1And V
Ref0Get 4 class values: 2.2V and 3.85V, 2.2V and 3.3V, 2.2V and 2.2V, 3.3V and 2.2V successively, input V
xDuring for triangular wave bin, threshold signal tb
J0, tb
J1, tb
J2, tb
J3Pspice computer simulation waveform show like 4 curves in Figure 15 top; Threshold signal t/b
J0, t/b
J1, t/b
J2, t/b
J3Pspice computer simulation waveform be 4 curves in Figure 16 top, Figure 15 and Figure 16 curve bottom is triangular wave bin, all curves tops (maximal value) are near V
DCWith relative V
DCRange of decrease V
x-V
DCJust to V
TpBe as the criterion and distinguish negative pulse and positive pulse, V
TpBe PMOS pipe Q
R0And Q
B1Threshold value; Be lower than V in 4 curves in Figure 15 top
DCNegative pulse all be in linear rising area of triangular wave bin or the linear district that descends, show Q
B1(V between zone
Ex1＞V
x-V
DC＞V
Ex0) conducting; In 4 curves in Figure 16 top near V
DCPositive pulse all be in linear rising area of triangular wave bin or the linear district that descends, show Q
R0(V between zone
Ex1＞V
x-V
DC＞V
Ex0) end, the band that satisfies is logical, belt-resistance function.
In Figure 15 and Figure 16, as threshold signal tb
J0, tb
J1, tb
J2, tb
J3T be worth relative V constantly
DCRange of decrease V
x-V
DCBe lower than V
Tp, then should constantly corresponding PMOS pipe Q
B1Conducting; As threshold signal t/b
J0, t/b
J1, t/b
J2, t/b
J3T be worth relative V constantly
DCRange of decrease V
x-V
DCBe lower than V
Tp, then should constantly corresponding PMOS pipe Q
R0Conducting; V
TpBe PMOS pipe Q
R0And Q
B1Threshold value.As input V
xDuring for triangular wave bin, pipe Q
R0And Q
B1The input difference V constantly of conducting just
x-V
DCInstantaneous value is V respectively just
Ex0And V
Ex1, can find the V under each reference voltage successively by Figure 15 and Figure 16
Ex0And V
Ex1Measured value is :-2.95V and-2.0V ,-3.45V and-2.0V ,-4.45V and-2.0V ,-4.45V and-0.85V.Under each reference voltage, press V
Ex0And V
Ex1Value computing formula V
Ex1=V
Ref1-V
DC+ V
Tn1+ | V
Tp2| and V
Ex0=V
Ref0-V
DC-V
Tn3-| V
Tp4| theory of computation value draws V
Ex0And V
Ex1Theoretical value is followed successively by :-2.8V and-2.15V ,-3.35V and-2.15V ,-4.45V and-2.15V ,-4.45V and-1.05V.Theoretical value and measured value are approaching, and minute differences (0.2V in) is arranged, minute differences be since in the circuit metal-oxide-semiconductor actual threshold with the change of grid reference voltage minor alteration is arranged.
(this circuit structure is the Q that leaves out among Fig. 6 to first kind of PMOS pipe high pass-low pass variable threshold circuit diagram 7 of the present invention
3, Q
4Branch road also exchanges V
Out0And V
Out1Draw), reference voltage V
Ref1Be followed successively by 3.85V, 2.2V, (this circuit structure is the Q that leaves out among Fig. 6 to second kind of PMOS pipe high pass-low pass variable threshold circuit diagram 8
1, Q
2Branch road draws), in Fig. 7 and Fig. 6, get V
DC=5.5V, V
SS=0V, V
D=4V, reference voltage V
Ref0Be followed successively by 1.65V and 3.3V, 4 kinds with reference to pipe Q under the voltage
5Low pass that drain electrode is corresponding and high pass output form threshold signal t/h successively
J4, t/h
J5And th
J6, th
J7, 4 kinds with reference to pipe Q under the voltage
5High pass that grid is corresponding and low pass output form threshold signal th successively
J4, th
J5And t/h
J6, t/h
J7, as input V
xDuring for triangular wave bin, Pspice computer simulation threshold signal t/h
J4, t/h
J5, th
J6, th
J7Waveform shows like 4 curves in Figure 17 top; Pspice computer simulation threshold signal th
J4, th
J5, t/h
J6, t/h
J7Waveform shows like 4 curves in Figure 18 top; Figure 17 and Figure 18 curve bottom is triangular wave bin, and all curve tops (maximal value) are near V
DCWith relative V
DCRange of decrease V
x-V
DCJust to V
TpBe as the criterion and distinguish negative pulse and positive pulse, be lower than V in the 3rd, 4 curves of Figure 17 and the 1st, 2 curves of Figure 18
DCNegative pulse all be in triangular wave bin high interval (covering triangular wave pulse top all divides), show Q
H1In the interval conducting of high pass, be lower than V in the 1st, 2 curves of Figure 17 and the 3rd, 4 curves of Figure 18
DCNegative pulse all be in triangular wave bin low interval (all dividing at the bottom of covering the triangular wave pulse), show Q
L0In low interval conducting; The high pass, the lowpass function that satisfy.
In Figure 17 and Figure 18, as threshold signal th
J4, th
J5, th
J6, th
J7T be worth relative V constantly
DCRange of decrease V
x-V
DCBe lower than V
Tp, then should constantly corresponding PMOS pipe Q
H1Conducting; As threshold signal t/h
J4, t/h
J5, t/h
J6, t/h
J7T be worth relative V constantly
DCRange of decrease V
x-V
DCBe lower than V
Tp, then should constantly corresponding PMOS pipe Q
L0Conducting; V
TpBe PMOS pipe Q
L0And Q
H1Threshold value.As input V
xDuring for triangular wave bin, pipe V
L0And V
H1The input difference V constantly of conducting just
x-V
DCInstantaneous value is V respectively just
Ex0And V
Ex1, can find the V under each reference voltage successively by Figure 17 and Figure 18
Ex1Measured value is :-0.32V and-2.02V, V
Ex0Measured value is :-5.0V and-3.42V.Under each reference voltage, press V
Ex0And V
Ex1Value computing formula V
Ex1=V
Ref1-V
DC+ V
Tn1+ | V
Tp2| and V
Ex0=V
Ref0-V
DC-V
Tn3-| V
Tp4| theory of computation value draws V
Ex1Theoretical value is followed successively by :-0.5V and-2.15V, V
Ex0Theoretical value is followed successively by :-5.0V and-3.35V.Show that theoretical value and measured value are approaching, the two has minute differences (in the 0.2V).
Embodiment 6: the explanation that Fig. 1 is carried out write and read and refreshes.
1. write: work as X
iAnd Y
jAll be high level, and read-write control signal R/W meet Y when being low level
jWith R/W with door output z
WrjBe high level, NMOS manages G
4, j+2, G
4, j+1, G
4, jConducting, G
5, j+2, G
5, j+1, G
5, jEnd data input DI
J+2, DI
J+1, DI
jWarp and door G
2, j+2, G
2, j+1, G
2, jWith or the door G
1, j+2, G
1, j+1, G
1, jForm 3 binary signal b
J+2, b
J+1, b
j, be input to BMVC, produce write bit line 8 value signals output Y by BMVC
WRj, because of transmission gate TG
1Conducting, 8 value signal Y
WRjBe transferred to F
SInput D
MCij, also promptly store capacitor C into
j
2. read double refreshing: work as X
i, Y
jWhen all being high level, with C with R/W
jSignal stored D
MCij8 corresponding value signal D
MijTG through conducting
2To sense bit line Y
RDjTransmission produces 32 value output m by 8-2 value change-over circuit MBVC again
J+2, m
J+1, m
j, Yin Feimen exports z
RdjBe high level, 2 value output m
J+2, m
J+1, m
jNMOS through conducting manages G on the one hand
5, j+2, G
5, j+1, G
5, jForm data output DO
J+2, DO
J+1, DO
j, on the one hand through with door G
3, j+2, G
3, j+1, G
3, jWith or the door G
1, j+2, G
1, j+1, G
1, jForm 32 value input b
J+2, b
J+1, b
j, produce 8 new value output Y by 2-8 change-over circuit BMVC
WRjY
WRjTG through conducting
2To C
jCharging refreshes;
3. refresh: work as X
iBe high level, Y
jWhen being low level, no matter what level R/W is, output z
WrjAnd z
GjLow level, not gate output z
RdjBe high level, similar said process is accomplished refresh function, and this moment, NMOS managed G
4, j+2, G
4, j+1, G
4, jAnd G
5, j+2, G
5, j+1, G
5, jEnd, with outer data input DI
J+2, DI
J+1, DI
jWith data output DO
J+2, DO
J+1, DO
jBreak off.In fact, input and output DI
J+2, DI
J+1, DI
jAnd DO
J+2, DO
J+1, DO
jBut step-by-step merges, and a line (I/O line) is merged in every input and output.
Embodiment 7: other explanation.
Fig. 9 is existing a kind of many output accurate mirror current source (constant current source) circuit diagrams and graphical diagram, for reducing power consumption and improving performance etc., its constant current source I
jElectric current is got smaller value (like the constant current source I among Fig. 2 and Fig. 4
j), used diode is a silicon diode, the conducting electric current is got smaller value (like 45 μ A); For obtaining the different reference voltage V of a sequence
Ref, can be used on V
DCAnd V
SSOr the bleeder circuit that (by common method) connects the series connection of a plurality of resistance between ground realizes, also can be used on direct supply and V
SSOr the bleeder circuit of the indirect a plurality of diodes in ground (or field-effect diode) series connection realizes (method that connects of similar battery commonly used series connection), because reference voltage all is to output to the metal-oxide-semiconductor grid, output DC stream is almost 0, so implement easily.Usually, door f
J7～f
J1With logical formula f
J7～f
J1Be 2 expression-forms of same function element, the same function of realization; Door f
J7～f
J1Be with door symbolic representation, formula f
J7～f
J1Be to represent with logical formula, and f
J7～f
J1Be exactly logical formula f
J7～f
J1Output (promptly the door f
J7～f
J1Output), add ' door ' before it and ' formula ' can be distinguished a f
J7～f
J1With logical formula f
J7～f
J1(adding English alphabet before it and adding Chinese character has same purpose, but the latter is understandable); Write so easily, otherwise symbol is too many, on the contrary inconvenience; For writing conveniently, can other loaded down with trivial details symbol of similar processing.The quantity of information of two value informations is minimum, and the quantity of information of multilevel information then than higher, is used capacitor C
jThe storage multilevel information is extremely lower than storage two-value information costs.Common capacitor C
jStoring value information is to wait 8 value signals of ladder, makes voltage follower F
SOutput might be lost multilevel information, its former because: if C
jReceive a desired voltage follower F
SAInput, F
SAThe voltage amplification factor perseverance be 1, no direct current offset, F
SAInput and output voltage identical, i.e. F
SAOutput and capacitor C
jThe multilevel information of storage is identical.And the virtual voltage follower (F among the present invention
S) voltage amplification factor less than 1, and direct current offset △ is arranged, show like Fig. 2 and Fig. 3, work as capacitor C
jThe storage signal logical value is 1, C
jVoltage makes F during less than △
SBe output as 0, i.e. F
SInput/output information is inequality; For avoiding F
SOutput information is lost, and design BMVC output is the multi-valued signal (offering the storage unit circuit input) that increases, and the multi-valued signal that increases is through F
SWhat exported the back is the non-ladder multi-valued signal that waits, and further designs MBVC, should be with this non-multi-valued signal conversion binary signal that waits ladder.
Claims (7)
1. 8 value storage unit circuits that embed the DRAM storage matrix is characterized in that: 8 value storage unit circuits of described embedding DRAM storage matrix are managed Q by 3 NMOS
M1, Q
M2, Q
M4, 2 PMOS pipe Q
M3, Q
M5With MM CAP C
jAnd power supply is formed; In 8 value storage unit circuits, manage Q
M1With current source I
jConstitute source follower F
S: pipe Q
M1Drain electrode meet direct supply V
DC, V
DC=1.8V, pipe Q
M1Source electrode meet current source I
jAn end, this junction is F
SOutput D
Mij, I
jThe negative direct supply V of another termination
SS, V
SS=-3.5V, I
jElectric current is by pipe Q
M1Source electrode flow to V
SSPipe Q
M1Grid meet MM CAP C
jAn end, this junction is F
SInput D
MCij, capacitor C
jAnother termination V
SSIn 8 value storage unit circuits, manage Q
M2And Q
M3, and Q
M4And Q
M5Constitute cmos transmission gate separately: pipe Q
M2And Q
M3Drain electrode join, source electrode also joins, manages Q
M4And Q
M5Drain electrode join, source electrode also joins, manages Q
M2And Q
M4Grid meet capable selection wire X
0i, pipe Q
M3And Q
M5Grid meet X
0iNon-
Manage Q in 2 cmos transmission gates
M2And Q
M3Constitute and import transmission gate TG into
1, pipe Q
M4And Q
M5Constitute and spread out of transmission gate TG
2: TG
1Input meet sense bit line Y
WRj, TG
1Output meet F
SInput D
MCij, TG
2Input meet F
SOutput D
Mij, TG
2Output meet sense bit line Y
RDjAs row selection wire X
0iDuring for high level, transmission gate TG
1And TG
2Conducting, write bit line 8 value signal Y
WRjTransmission gate TG through conducting
1Be transferred to F
SInput D
MCijAlso promptly be transferred to pipe Q
M1Grid, with 8 value signal D
MCijDeposit MM CAP C in
j, the message pick-up function of completion 8 value storage unit circuits; Then as row selection wire X
0iDuring for low level, transmission gate TG
1And TG
2End capacitor C
jWith the external world be direct current open circuit, MM CAP C
j8 value signal D of storage
MCijRemain unchanged, accomplish the information storage function of 8 value storage unit circuits; Capacitor C
j8 value signal D of storage
MCijThrough F
SForm 8 corresponding value source output D
Mij, X appears instantly constantly once more
0iDuring for high level, transmission gate TG
2Conducting is with C
jStorage signal D
MCij8 corresponding value signal D
MijTG through conducting
2Outwards output, the message sending function of completion 8 value storage unit circuits; 8 value storage unit circuits except that the read and write of accomplishing 8 value canned datas, are also accomplished refreshing of 8 value canned datas through read-write control circuit.
2. the 2-8 change-over circuit BMVC of 8 value storage unit of a kind of DRAM of embedding storage matrix that 8 value storage unit circuits of a kind of DRAM of embedding storage matrix according to claim 1 draw is characterized in that: described 2-8 value change-over circuit BMVC is by 7 door f
J7～f
J1, 7 PMOS pipe Q
A7～Q
A1With 6 silicon diode D
A7～D
A2And the power supply composition, BMVC has 32 values input b
J+2, b
J+1, b
jWith 18 value write bit line output Y
WRj7 door f
J7～f
J1The output logic formula be:
Promptly the door f
J7Be to be input as b
J+2, b
J+1, b
jSheffer stroke gate, the door f
J6Be to be input as b
J+2, b
J+1Sheffer stroke gate, the door f
J5Be to be input as b
J+2, b
jSheffer stroke gate, the door f
J4Be to be input as b
J+2Not gate, the door f
J3Be to be input as b
J+1, b
jSheffer stroke gate, the door f
J2Be to be input as b
J+1Not gate, the door f
J1Be to be input as b
jNot gate, the WV of Sheffer stroke gate and not gate is V
DC, V
DC=1.8V; Pipe Q
A7～Q
A1Grid meets f separately
J7～f
J1, diode D
A7～D
A2Positive pole take over Q separately
A6～Q
A1Drain electrode, diode D
A7～D
A2Negative pole take over Q separately
A7～Q
A2Drain electrode, Q
A7Drain electrode meet current source I
jAn end, this junction is write bit line output Y
WRj, I
jAnother termination negative supply voltage V
SS, V
SS=-3.5V, I
jElectric current is by Y
WRjFlow to V
SSPipe Q
A7～Q
A1Source electrode meet supply voltage V
DC, V
DC=1.8V, the diode current flow pressure drop is V
dThe input/output relation of BMVC is: 1. as input b
J+2b
J+1b
j=111 o'clock, f
J7=0, pipe Q
A7Conducting, Y
WRjOutput voltage V
YWRj=V
DC, presentation logic 7; 2. as input b
J+2b
J+1b
j=110 o'clock, f
J7=1 and f
J6=0, pipe Q
A7End pipe Q
A6Conducting, V
YWRj=V
DC-V
d, presentation logic 6; 3. as input b
J+2b
J+1b
j=101 o'clock, f
J7=f
J6=1 and f
J5=0, pipe Q
A7, Q
A6End pipe Q
A5Conducting, V
YWRj=V
DC-2V
d, presentation logic 5; 4. as input b
J+2b
J+1b
j=001 o'clock, f
J7=f
J6=f
J5=f
J4=f
J3=f
J2=1 and f
J1=0, pipe Q
A7～Q
A2End pipe Q
A1Conducting, V
YWRj=V
DC-6V
d, presentation logic 1; 5. as input b
J+2b
J+1b
j=000 o'clock, f
J7=f
J6=f
J5=f
J4=f
J3=f
J2=f
J1=1, all manage Q
A7～Q
A1All end V
YWRj=V
SS, presentation logic 0; Binary numeral 000～111 corresponding decimal system number is 0～7, as input b
J+2b
J+1b
j=000～111 o'clock, Y
WRjOutput voltage V
YWRj8 logic level v (0)～v (7) is arranged, and presentation logic 0～7 separately, v (0)=V
SS, v (k)=V
DC-(7-k) V
d, k=1～7.
3. the 2-8 change-over circuit BMVC of 8 value storage unit of a kind of DRAM of embedding storage matrix that 8 value storage unit circuits of a kind of DRAM of embedding storage matrix according to claim 1 draw is characterized in that: described 8-2 change-over circuit MBVC is by 4 band general formula variable threshold PMOS pipe G
B0mj, G
B1mj, G
B2mj, G
B3mj, 3 high general formula variable threshold PMOS pipe G
H4mj, G
H5mj, G
H6mjWith 3 resistance R
0mj, R
1mj, R
2mjForm, MBVC has 18 value sense bit line input Y
RDjWith 32 value output m
J+2, m
J+1, m
j7 pipe G
B0mj～G
B3mjAnd G
H4mj～G
H6mjSource electrode all meet power supply V
DC, V
DC=1.8V; 4 pipe G
B0mj～G
B3mjGrid respectively hang oneself band logical-band resistance variable threshold circuit meets Y
RDj, 3 pipe G
H4mj～G
H6mjThe grid high pass-low pass variable threshold circuit of respectively hanging oneself meet Y
RDj, pipe G
H4mjDrain electrode and resistance R
2mjAn end be connected, this junction is as 2 value output m
J+2, resistance R
2mjOther end ground connection; 2 pipe G
R0mj, G
H5mjDrain electrode and resistance R
1mjAn end be connected, this junction is as 2 value output m
J+1, resistance R
1mjOther end ground connection; 4 pipe G
H6mjAnd G
B1mj～G
B3mjDrain electrode and resistance R
0mjAn end be connected, this junction is as 2 value output m
j, resistance R
0mjOther end ground connection; 7 pipe G
H4mj～G
H6mjAnd G
B0mj～G
B3mjSatisfy: 1. manage G
H4mjAt Y
RDjInput is merely logic 4～7 o'clock conducting, otherwise ends, and promptly manages G
H4mjHigh pass threshold th
J4For comprising the high interval of logic level v (4); 2. manage G
H5mjAt Y
RDjInput is merely logic conducting in 6,7 o'clock, otherwise ends, and promptly manages G
H5mjHigh pass threshold th
J5For comprising the high interval of logic level v (6); 3. manage G
H6mjAt Y
RDjConducting when input is merely logic 7, otherwise end, G promptly managed
H6mjHigh pass threshold th
J6For comprising the high interval of logic level v (7); 4. manage G
B0mjAt Y
RDjInput is merely logic conducting in 2,3 o'clock, otherwise ends, and promptly manages G
B0mjThe logical threshold tb of band
J0For between the zone that only comprises 2 logic level v (2), v (3); 5. manage G
B1mjAt Y
RDjConducting when input is merely logic level 1, otherwise end, G promptly managed
B1mjThe logical threshold tb of band
J0For between the zone that only comprises logic level v (1); 6. manage G
B2mjAt Y
RDjConducting when input is merely logic level 3, otherwise end, G promptly managed
B2mjThe logical threshold tb of band
J0For between the zone that only comprises logic level v (3); 7. manage G
B3mjAt Y
RDjConducting when input is merely logic level 5, otherwise end, G promptly managed
B3mjThe logical threshold tb of band
J0For between the zone that comprises logic level v (5); The input/output relation of MBVC is: Y is worked as in (1)
RDjWhen being input as logic 7, pipe G
H4mj, G
H5mj, G
H6mjConducting, output m
J+2m
J+1m
j=111; (2) work as Y
RDjWhen being input as logic 6, pipe G
H4mj, G
H5mjConducting, other pipe ends, output m
J+2m
J+1m
j=110; (3) work as Y
RDjWhen being input as logic 5, pipe G
H4mj, G
B3mjConducting, other pipe ends, output m
J+2m
J+1m
j=101; (4) work as Y
RDjWhen being input as logic 4, pipe G
H4mjConducting, other pipe ends, output m
J+2m
J+1m
j=100; (5) work as Y
RDjWhen being input as logic 3, pipe G
B0mj, G
B2mjConducting, other pipe ends, output m
J+2m
J+1m
j=011; (6) work as Y
RDjWhen being input as logic 2, pipe G
B0mjConducting, other pipe ends, output m
J+2m
J+1m
j=010; (7) work as Y
RDjWhen being input as logical one, pipe G
B1mjConducting, other pipe ends, output m
J+2m
J+1m
j=001; (8) work as Y
RDjWhen being input as logical zero, all pipes all end, output m
J+2m
J+1m
j=000; Also promptly work as Y
RDjBe input as logical zero～7 o'clock, draw corresponding two-value and be output as 000～111.
4. a kind of 8 value storage unit circuits that embed the DRAM storage matrix according to claim 1 is characterized in that: V
DCOr=1.5V, V
SSOr=-4.0V.
5. the relevant change-over circuit that draws according to 8 value storage unit circuits of claim 2 or the 3 described a kind of DRAM of embedding storage matrix is characterized in that: V
DCOr=1.5V, V
SSOr=-4.0V.
6. a kind of 8 value storage unit circuits that embed the DRAM storage matrix according to claim 1 is characterized in that: current source I in the described storage unit circuit
jOr be resistance R
j
7. the relevant change-over circuit that draws according to 8 value storage unit circuits of claim 2 or the 3 described a kind of DRAM of embedding storage matrix is characterized in that: described current source I
jOr be resistance R
j
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| CN201110280921.4A CN102426855B (en) | 2011-10-24 | 2011-10-24 | 8-value memory cell embedded in DRAM storage matrix, and corresponding conversion circuit thereof |
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|---|---|---|---|
| CN201110280921.4A CN102426855B (en) | 2011-10-24 | 2011-10-24 | 8-value memory cell embedded in DRAM storage matrix, and corresponding conversion circuit thereof |
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| CN102426855B CN102426855B (en) | 2014-04-02 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106205672A (en) * | 2015-05-26 | 2016-12-07 | 爱思开海力士有限公司 | Memory Device |
| CN104333367B (en) * | 2014-10-01 | 2017-05-03 | 黑龙江大学 | K-value and ten-value signal controlled data distributor and data selector |
| CN106664078A (en) * | 2014-09-03 | 2017-05-10 | 德州仪器公司 | Low leakage shadow latch-based multi-threshold cmos sequential circuit |
| CN113409843A (en) * | 2021-05-14 | 2021-09-17 | 成都华微电子科技有限公司 | SRAM dynamic array power supply control circuit |
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|---|---|---|---|---|
| EP0643393A2 (en) * | 1993-09-10 | 1995-03-15 | Kabushiki Kaisha Toshiba | Semiconductor memory device having voltage booster circuit |
| CN102436847A (en) * | 2011-09-15 | 2012-05-02 | 黑龙江大学 | PMOS (P-channel Metal Oxide Semiconductor) pipe band-pass-band-stop changeable threshold circuit and PMOS pipe high-pass-low-pass changeable threshold circuit |
-
2011
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0643393A2 (en) * | 1993-09-10 | 1995-03-15 | Kabushiki Kaisha Toshiba | Semiconductor memory device having voltage booster circuit |
| CN102436847A (en) * | 2011-09-15 | 2012-05-02 | 黑龙江大学 | PMOS (P-channel Metal Oxide Semiconductor) pipe band-pass-band-stop changeable threshold circuit and PMOS pipe high-pass-low-pass changeable threshold circuit |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106664078A (en) * | 2014-09-03 | 2017-05-10 | 德州仪器公司 | Low leakage shadow latch-based multi-threshold cmos sequential circuit |
| CN106664078B (en) * | 2014-09-03 | 2020-12-08 | 德州仪器公司 | Multi-threshold CMOS (complementary Metal oxide semiconductor) sequential circuit based on low-leakage shadow latch |
| CN104333367B (en) * | 2014-10-01 | 2017-05-03 | 黑龙江大学 | K-value and ten-value signal controlled data distributor and data selector |
| CN106205672A (en) * | 2015-05-26 | 2016-12-07 | 爱思开海力士有限公司 | Memory Device |
| CN106205672B (en) * | 2015-05-26 | 2020-12-25 | 爱思开海力士有限公司 | Memory device |
| CN113409843A (en) * | 2021-05-14 | 2021-09-17 | 成都华微电子科技有限公司 | SRAM dynamic array power supply control circuit |
| CN113409843B (en) * | 2021-05-14 | 2023-05-16 | 成都华微电子科技股份有限公司 | SRAM dynamic array power supply control circuit |
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|---|---|
| CN102426855B (en) | 2014-04-02 |
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