CN102426852A - Method and system for reading information of memory array cell - Google Patents
Method and system for reading information of memory array cell Download PDFInfo
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- CN102426852A CN102426852A CN2011103918115A CN201110391811A CN102426852A CN 102426852 A CN102426852 A CN 102426852A CN 2011103918115 A CN2011103918115 A CN 2011103918115A CN 201110391811 A CN201110391811 A CN 201110391811A CN 102426852 A CN102426852 A CN 102426852A
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Abstract
The invention provides a method and a system for reading information of a memory array cell. Multiple continuous bit lines comprising bit lines of a cell to be read are simultaneously gated, a first reading voltage is applied to one bit line of the memory cell to be read, a second reading voltage which is higher than the first reading voltage is applied to the other bit line of the memory cell to be read, and a voltage equal to the second reading voltage is applied to multiple continuous bit lines adjacent to the bit line which is applied with the second reading voltage, so there is no potential difference between two ends of the multiple memory cells adjacent to the bit line applied with the higher reading voltage, thereby a current leakage problem caused by adjacent memory cells is avoided, and the memory information reading precision of the memory cell is improved.
Description
Technical field
The present invention relates to area information storage, particularly relate to a kind of cells of memory arrays information-reading method and system.
Background technology
The core of whole storer is the array that storage unit constitutes; The read method of location information is referring to Fig. 1 in the array; Storage unit is an example with common metal-oxide-semiconductor, and each storage unit (cell) has three ports, and one of them is a control port; The grid that is equivalent to common metal-oxide-semiconductor, all the other two ports are equivalent to the source electrode and the drain electrode of common metal-oxide-semiconductor.The control port of storage unit connects word line, and the control port with delegation's storage unit connects same word line WL1 in the array, and word line potential is just realized the unlatching of storage unit and shutoff.Source electrode with delegation's storage unit in the storage array joins end to end with drain electrode in order, and the source electrode of two adjacent storage unit and drain electrode are connected on the bit line.When storage unit was in opening, equivalence was a resistance; When storage unit institute canned data is " 0 " or when " 1 ", its resistance value is different.Therefore,, need apply potential difference (PD), the canned data of the electric current that reading flow is crossed storage unit in just can reading cells at the two ends that are read storage unit for canned data in the reading cells.
During information in the reading cells; Low level generation circuit or electric current read circuit and are connected through the bit line strobe unit with the bit line of storage array; The bit line strobe unit is equivalent to an electrical switch; By the bit line in the bit line gating control signal control bit line selection exchange device gating storage array, the bit line that makes gating and low level produce circuit or electric current and read circuit and be connected.Storage unit cell2 is an example among Fig. 1 to read; Word line WL1 level is that high back storage unit cell2 opens; Conventional storage array information-reading method is two bit lines BLa and the BLa+1 that gating storage unit cell2 source electrode is connected with drain electrode; Make bit line BLa and BLa+1 be connected respectively that low level produces circuit and electric current reads circuit; Apply respectively at bit line BLa and BLa+1 and to read low-voltage and to read high voltage, the electric potential difference at storage unit cell2 two ends causes flowing through the current Ib it of storage unit, and the current value that flows through storage unit cell2 is designated as Ibit.Read electric current I and read circuit by electric current and read, read the current value that reads that circuit reads and be designated as I, when I=Ibit, canned data in this current value of reading reflection storage unit.
But; During information in reading cells cell2; On bit line BLa and BLa+1, apply respectively and read low-voltage and read high voltage, with bit line BLa+1 adjacent bit lines BLa+2, do not apply voltage on the BLa+3 equipotential line; Produce the moment that circuit and electric current read circuit working in low level; Source electrode and drain electrode two ends at storage unit cell3, cell4 etc. produce electric potential difference, can on storage unit cell3, cell4 etc., produce Leakage Current Ileak, and this Leakage Current value is designated as Ileak.The value that electric current reads the electric current I that circuit reads is I=Ibit+Ileak; Wherein, Having only Ibit is the reflection of canned data among the storage unit cell2; So leakage current makes and to read the canned data situation that electric current I can not accurately reflect cell2, this might cause the information read error, make storer to read precision not high.
Summary of the invention
It is the existing not high problem of cells of memory arrays information-reading method precision that the present invention solves.
For addressing the above problem, the invention provides a kind of cells of memory arrays information-reading method, comprise,
Gating is read the word line of storage unit; Many continuous bit lines of gating storage array, wherein
Apply first respectively at said two bit lines that are read storage unit and read voltage and second reading power taking pressure, said second reading power taking pressure is higher than first and reads voltage; Apply the voltage that equates with said second reading power taking pressure simultaneously with the adjacent continuous many bit lines of bit line that apply said second reading power taking pressure;
Relatively be read the electric current and the predetermined current value that produce on the storage unit and confirm the said canned data that is read storage unit.
Correspondingly, the present invention also provides a kind of cells of memory arrays information reading system, comprises that memory cell array, low level produce circuit, electric current reads circuit, bit line strobe unit and word line strobe unit, also comprises a plurality of voltage follower circuits,
Said voltage follower circuit reads circuit with said electric current identical voltage is provided, and is higher than said low level and produces the voltage that circuit produces; Said low level generation circuit, electric current read circuit synchronouss working with voltage follower circuit;
Said word line strobe unit gating is read the word line of storage unit; Said bit line strobe unit is according to many continuous bit lines of the said storage array of bit line gating control signal while gating;
Said low level produces circuit and is connected with a bit line that is read cells of memory arrays through the bit line strobe unit; Said electric current reads circuit and is connected with another root bit line that is read cells of memory arrays through the bit line strobe unit; The input termination electric current of a plurality of voltage follower circuits reads the voltage output end of circuit, and the output terminal of each voltage follower circuit reads the adjacent continuous many bit lines of the bit line of circuit and connects with the electric current that is connected that is read storage unit respectively through the bit line strobe unit.
Compared with prior art, the present invention has advantage:
The invention provides a kind of cells of memory arrays information-reading method; The technical scheme that adopts is the many continuous bit lines that the while gating comprises the bit line that is read the unit; Wherein, Apply first at a said bit line that is read storage unit and read voltage, another root bit line apply be higher than first read voltage the second reading power taking press; Apply the adjacent continuous many bit lines of bit line that the second reading power taking presses and apply the voltage that equates with said second reading power taking pressure with the said storage unit that is read; Relatively be read produce on the storage unit read electric current and predetermined current value, confirm the said canned data that is read storage unit.Compare with the read schemes of routine; Apply the many adjacent continuous bit lines of bit line of pressing and apply equal second reading power taking and press being read storage unit than the second reading power taking; There is not potential difference (PD) in a plurality of storage unit two ends adjacent with being read storage unit; Avoided consecutive storage unit to produce the problem of leakage current, the canned data that has improved storage unit reads precision.
Description of drawings
Shown in accompanying drawing, above-mentioned and other purpose, characteristic and advantage of the present invention will be more clear.Reference numeral identical in whole accompanying drawings is indicated identical part.Painstakingly do not draw accompanying drawing, focus on illustrating purport of the present invention by physical size equal proportion convergent-divergent.
Fig. 1 reads the synoptic diagram of a storage unit for existing cells of memory arrays information-reading method;
Fig. 2 reads the synoptic diagram of a storage unit for cells of memory arrays information-reading method of the present invention;
Fig. 3 produces circuit diagram for the low level of cells of memory arrays information-reading method of the present invention;
Fig. 4 reads circuit diagram for the electric current of cells of memory arrays information-reading method of the present invention;
Fig. 5 reads the voltage clamp cell schematics of circuit for the electric current of cells of memory arrays information-reading method of the present invention;
Fig. 6 is the voltage follower circuit synoptic diagram of cells of memory arrays information-reading method of the present invention;
Fig. 7 connects synoptic diagram for the bit line strobe unit of cells of memory arrays information-reading method of the present invention;
Fig. 8 is applied in the synoptic diagram of whole storage array for cells of memory arrays information-reading method of the present invention;
Fig. 9 is a cells of memory arrays information reading system synoptic diagram of the present invention.
Embodiment
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
Set forth a lot of details in the following description so that make much of the present invention, implement but the present invention can also adopt other to be different from alternate manner described here, so the present invention has not received the restriction of following disclosed specific embodiment.
Secondly, the present invention combines synoptic diagram to be described in detail, and when the embodiment of the invention was detailed, for ease of explanation, said synoptic diagram was an example, and it should not limit the scope of the present invention's protection at this.
Said as background technology; Conventional storage array information-reading method is to read low-voltage being read to apply on the bit line of storage unit; Apply on another root bit line and read high voltage; Do not apply any signal with applying high-tension bit line on adjacent other bit lines, applying high-tension moment for the bit line that is read storage unit, there is electric potential difference in the two ends of the storage unit of the many piece bit lines connections not applying any signal adjacent with the bit line that is connected high voltage signal; Be read the unit with the word line of the storage unit of delegation by gating; These word lines are equivalent to a resistance by the storage unit of gating, can on these storage unit, produce leakage current, like this electric current read electric current that circuit reads be flow through the electric current that is read storage unit and adjacent other storage unit Leakage Current and.But; Only flow through the electric current that is read storage unit and be only the reflection that this is read canned data in the storage unit, the Leakage Current that produces on adjacent other storage unit with being read storage unit might cause being read the canned data read error of storage unit.Therefore existing storage array information-reading method make cells of memory arrays to read precision not high.
In order to improve the precision that reads of cells of memory arrays information-reading method; The present invention proposes the method that a kind of new cells of memory arrays information reads; Technical scheme is when reading cells information; Many continuous bit lines of while gating storage array; Applying the voltage that equates with being read the adjacent continuous many bit lines of bit line that storage unit applies high voltage, eliminate and be read the generation of Leakage Current on the storage unit adjacent memory unit, improved the precision that reads of cells of memory arrays information-reading method.Describe the process that reads of the present invention in detail through concrete embodiment below.
Referring to Fig. 2; Present embodiment has proposed a kind of cells of memory arrays information-reading method; Adopt two voltage follower circuits to provide and be read the voltage that bit line that storage unit applies high voltage equates, word line gating control signal is read the word line WL of storage unit Celln+1 through word line strobe unit gating in the present embodiment, and bit line gating control signal is through bit line strobe unit four continuous bit line BLn, BLn+1, BLn+2 and BLn+3 of gating storage array simultaneously; Make bit line BLn apply low first and read voltage; This first reads voltage and produces circuit by low level and produce, and bit line BLn+1 applies the second reading power taking and presses, the second reading power taking press be higher than first read voltage should; Read circuit by electric current and produce, bit line BLn+2 and BLn+3 apply the voltage that voltage follower circuit produces.Electric current on the reading cells Celln+1, and with preset reference current value relatively, can draw canned data among the storage unit Celln+1.The effect of voltage follower circuit is to follow the storage unit that is read to apply the voltage that an end is pressed in the second reading power taking, and the bit-line voltage that is attached thereto is arrived and the identical magnitude of voltage of second reading power taking pressure.When storage unit Celln+1 was read, the voltage of storage unit Celln+2 and Celln+3 equated, so can not produce Leakage Current, can not go up the electric current that reads that produces to storage unit Celln+1 and impact.Therefore the cells of memory arrays information-reading method of present embodiment can guarantee the precision that reads on the storage unit Celln+1.
The method of a present embodiment gating 4 continuous bit lines of storage array; Can more continuous bit lines of gating; Wherein, Apply first of low level generation circuit generation at a bit line that is read storage unit and read voltage, another root bit line applies electric current and reads the second reading power taking pressure that circuit produces; Be read storage unit and apply the adjacent continuous many bit lines of bit line that the second reading power taking presses and apply the voltage that equates with second reading power taking pressure that voltage follower circuit provides simultaneously.
First of present embodiment reads voltage and produces the circuit generation by low level; The basic structure that low level produces circuit can be a MOS transistor, and circuit connecting mode is referring to Fig. 3, MOS transistor source class 1 ground connection; Drain electrode 2 connects bit line through the bit line strobe unit, and grid 3 connects control end.When control end is opened, the MOS transistor conducting, drain electrode 2 is changed to low level through the bit line that the bit line strobe unit connects; When control end was closed, MOS transistor ended, and drain electrode 2 is floating empty through the bit line that the bit line strobe unit connects.
The second reading power taking of present embodiment is pressed by electric current and is read the circuit generation; Electric current reads circuit can be a sense amplifier or pseudo-sense amplifier; Referring to Fig. 4; Its basic structure comprises two PMOS current mirrors 4, electric current decision unit and the voltage clamp unit that is connected with analog power VDDA; It is that a bit line that is read storage unit 5 applies high voltage that a mirror image branch of the current mirror of wherein being made up of the PMOS transistor 4 connects behind the voltage clamp unit through the bit line strobe unit; The bit line current potential that is read storage unit 5 simultaneously is fixed on setting voltage value Vdp by the voltage clamp unit, and another root bit line that is read storage unit 5 applies level through the bit line strobe unit and produces the low-voltage that circuit (not illustrating in the drawings) produces, and another mirror image branch of current mirror 4 is connected with current source A one end through sensing points C; The other end ground connection of current source, said decision unit is connected on the sensing points C.
The decision unit that the electric current of present embodiment reads circuit can adopt phase inverter; The input end of said phase inverter is connected the sensing points C that electric current reads circuit; The mirror image that electric current I is read in the output of the output terminal of said phase inverter reads the comparative result of the preset reference current value that electric current I m and current source A provide, and this comparative result reflects canned data among storage unit Celln+1.
The voltage clamp unit that the electric current of present embodiment reads circuit can comprise phase inverter and nmos pass transistor; Referring to Fig. 5, wherein, the source electrode 12 of nmos pass transistor is the input end of voltage clamp unit; Drain electrode 13 is the output terminal of said voltage clamp unit; Also be the voltage output end that electric current reads circuit, drain electrode 13 is connected with the input end of phase inverter 10, and the output terminal of phase inverter 10 is connected with the grid of nmos pass transistor 11.
The basic structure of voltage follower circuit can comprise an operational amplifier, and is as shown in Figure 6, and the output terminal 22 of operational amplifier is connected with inverting input 21, make amplifier output terminal 22 voltage just and the voltage of in-phase input end 20 be consistent.The input end 20 of operational amplifier is the input end of voltage follower circuit, is connected the voltage output end that electric current reads circuit, and the voltage of output terminal 22 outputs of operational amplifier is applied on the bit line through the bit line strobe unit.As shown in Figure 2, when read operation, voltage follower circuit can carry out synchronous charging for connected bit line BLn+2 and BLn+3 follow bit line BLn+1, and the voltage of bit line BLn+2 and BLn+3 is equated with bit line BLn+1.
In addition, the voltage follower circuit in the present embodiment can also comprise control end, referring to Fig. 6, and voltage follower circuit work when control end 23 is high level, the voltage that output terminal 22 outputs equate with in-phase input end 20; When control end 23 was low level, voltage follower circuit was closed and is not worked, and output terminal 22 output voltages are zero.
In the cells of memory arrays information-reading method of present embodiment; Many continuous bit lines of gating storage array are realized according to the gating control signal by the bit line strobe unit; The bit line strobe unit is the pith that the cells of memory arrays information-reading method of present embodiment is realized; The bit line strobe unit is the circuit arrangement of control bit line and other sensing circuits (reading circuit like electric current) annexation; Gating control signal through the preparatory decoding scheme of bit line strobe unit produces is controlled, and is equivalent to an electrical switch.The elementary cell of bit line strobe unit is a MOS transistor, and the source electrode of MOS transistor is connected bit line and sensing circuit respectively with drain electrode, and grid connects bit line gating control signal.
In actual memory array unit information reading system, the bit line strobe unit has multiple structure, and the bit line strobe unit of present embodiment can adopt the gating structure of a bit line of a gating control signal gating.Strobe unit connects synoptic diagram when cells of memory arrays information reads among Fig. 7; The bit line strobe unit comprises a plurality of MOS transistor M1, M2, M3...; Bit line gating control signal S1 gating MOS transistor M1, the bit line BLn of storage array produce circuit through MOS transistor M1 with low level and are connected; Bit line gating control signal S2 gating MOS transistor M2, the bit line BLn+1 of storage array reads circuit through MOS transistor M2 with electric current and is connected; Bit line gating control signal S3 gating MOS transistor M3, the bit line BLn+2 of storage array is connected with voltage follower circuit through MOS transistor M3; Bit line gating control signal S4 gating MOS transistor M4, the bit line BLn+3 of storage array is connected with voltage follower circuit through MOS transistor M4.
It is as shown in Figure 8 that the method for present embodiment is applied to whole storage array; The storage array that a plurality of storage unit are formed; Word line WLn controls opening and shutting off of the capable storage unit of n; Word line WLm controls opening and shutting off of the capable storage unit of m, and preparatory four continuous MOS transistors of making of the gating control signal gating bit line gating that produces of decoding scheme make in the storage array an other end conducting of four continuous bit lines and strobe unit; These four continuous bit lines can be arranged in any position of storage array; By gating, perhaps bit line BLm, BLm+1, BLm+2 and BLm+3 are by gating like bit line BLn, BLn+1, BLn+2 and BLn+3, and strobe unit makes four continuous bit lines apply low level generation circuit respectively, electric current reads circuit and two voltages that voltage follower circuit produces.
The present invention also provides a kind of storage array information reading system, referring to Fig. 9, comprises that memory cell array, low level produce circuit, electric current reads circuit, bit line strobe unit, word line strobe unit and a plurality of voltage follower circuit, wherein,
Low level produces circuit, electric current and reads circuit and provide circuit to pass through the bit line strobe unit with a plurality of pseudo-voltages to be connected with the continuous many bit lines of storage array;
The bit line strobe unit is connected with the bit line of storage array; The word line strobe unit is connected with the word line of storage array;
It is identical that voltage follower circuit and electric current read the voltage that circuit provides, and is higher than low level and produces the voltage that circuit provides; Low level generation circuit, electric current read circuit synchronouss working with voltage follower circuit;
Low level produces circuit and is connected with a bit line that is read cells of memory arrays through the bit line strobe unit; Electric current reads circuit and is connected with another root bit line that is read cells of memory arrays through the bit line strobe unit; The input termination electric current of a plurality of voltage follower circuits reads the voltage output end of circuit, and the output terminal of each voltage follower circuit reads the adjacent continuous many bit lines of the bit line of circuit and connects with the electric current that is connected that is read storage unit respectively through the bit line strobe unit.
The structure of bit line strobe unit can comprise a plurality of MOS transistors; The grid of a MOS transistor only connects a said bit line gating control signal; Source electrode only connects a bit line, and drain electrode connects low level generation circuit, voltage follower circuit or electric current and reads circuit.
Electric current reads circuit can be a sense amplifier or pseudo-sense amplifier; Its basic structure comprises PMOS current mirror, electric current decision unit and the voltage clamp unit that is connected with analog power VDDA; A mirror image branch of the current mirror of wherein being made up of the PMOS transistor connects the bit line that is read storage unit through the bit line strobe unit after connecting the voltage clamp unit, and a bit line current potential that is read storage unit simultaneously is fixed on setting voltage value Vdp by the voltage clamp unit; Another mirror image branch of current mirror is connected with an end of current source through sensing points, the other end ground connection of current source, and said decision unit is connected on the sensing points.Wherein, decision unit can adopt phase inverter, and the input end of said phase inverter is connected the sensing points that electric current reads circuit, and the output terminal outgoing mirror of said phase inverter looks like to read the comparing result of the preset reference current value that electric current and current source A provide; The voltage clamp unit can comprise phase inverter and nmos pass transistor; The source electrode of nmos pass transistor is the input end of voltage clamp unit; Drain electrode is the output terminal of said voltage clamp unit, and drain terminal is connected with the input end of phase inverter, and the output terminal of phase inverter is connected with the grid of nmos pass transistor.
The basic structure of voltage follower circuit can comprise an operational amplifier; The output terminal of operational amplifier is connected with inverting input; The input end of operational amplifier is connected the voltage output end that electric current reads circuit, and the output terminal of operational amplifier is connected on the bit line through the bit line strobe unit.Voltage follower circuit can also comprise a control end, voltage follower circuit work when control end is high level, and voltage follower circuit was closed and is not worked when control end was low level.
When carrying out cells of memory arrays information read operation; Word line gating control signal is read the word line of storage unit through word line strobe unit gating; Bit line gating control signal is read the continuous many bit lines of storage unit through bit line strobe unit gating; Wherein, low level generation circuit is connected with a bit line that is read cells of memory arrays through the bit line strobe unit; Electric current reads circuit and is connected with another root bit line that is read cells of memory arrays through the bit line strobe unit; A plurality of voltage follower circuits read the adjacent continuous many bit lines of the bit line of circuit and connect with the electric current that is connected that is read storage unit respectively through the bit line strobe unit.Low level produces circuit, electric current reads circuit and synchronously the bit line that is connected separately charged with voltage follower circuit, and electric current reads circuit and reads the electric current that is read storage unit, confirms that this is read canned data in the storage unit.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.
Though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention.Any those of ordinary skill in the art; Do not breaking away under the technical scheme scope situation of the present invention; All the method for above-mentioned announcement capable of using and technology contents are made many possible changes and modification to technical scheme of the present invention, or are revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical scheme of the present invention, all still belongs in the scope of technical scheme protection of the present invention any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (11)
1. a cells of memory arrays information-reading method is characterized in that, comprising:
Gating is read the word line of storage unit; Many continuous bit lines of gating storage array, wherein
Apply first respectively at said two bit lines that are read storage unit and read voltage and second reading power taking pressure, said second reading power taking pressure is higher than first and reads voltage; Apply the voltage that equates with said second reading power taking pressure simultaneously with the adjacent continuous many bit lines of bit line that apply said second reading power taking pressure;
Relatively be read the electric current and the predetermined current value that produce on the storage unit and confirm the said canned data that is read storage unit.
2. cells of memory arrays information-reading method according to claim 1 is characterized in that, said applying simultaneously with said second reading power taking with the adjacent continuous many bit lines of bit line that apply said second reading power taking pressure presses the voltage that equates to be:
The in-phase input end of operational amplifier is imported said second reading power taking and is pressed; Through being that the bit line that is connected the output terminal of operational amplifier applies the voltage that equates with said second reading power taking pressure after the operational amplifier computing, the inverting input of said operational amplifier is connected output terminal.
3. cells of memory arrays information-reading method according to claim 1 and 2 is characterized in that, many continuous bit lines of said gating storage array are:
A plurality of gating control signals are controlled a plurality of MOS transistor conductings; Wherein, The source electrode and drain electrode conducting of a MOS transistor of a gating control signal control make the bit line of the source electrode that is connected a MOS transistor apply said low-voltage, high voltage or the pseudo-voltage that is connected drain electrode.
4. cells of memory arrays information-reading method according to claim 1 and 2 is characterized in that, saidly applies first at a said bit line that is read storage unit and reads voltage and be:
The source electrode of the MOS transistor of control source ground is that said bit line applies first and reads voltage with the drain electrode conducting.
5. cells of memory arrays information-reading method according to claim 1 and 2 is characterized in that, saidly applies the second reading power taking at a said bit line that is read storage unit and presses and to be:
Supply voltage is that said second reading power taking is pressed through comprising behind of 2 transistorized current mirrors of PMOS by the voltage clamp circuit clamper, and said second reading power taking pressed is applied to a said bit line that is read storage unit.
6. cells of memory arrays information-reading method according to claim 5 is characterized in that, the said electric current and the predetermined current value that produce on the storage unit of relatively being read confirms that the said canned data that is read storage unit is:
Read in and be read the electric current that reads that storage unit applies bit line that the second reading power taking presses, comprising:
Be read the electric current that produces on the storage unit another generation image current at said current mirror;
Said image current and said predetermined current value compare, and obtain the said canned data that is read storage unit through the decision circuit judgement that comprises phase inverter.
7. cells of memory arrays information-reading method according to claim 1 and 2 is characterized in that, applies adjacent continuous two bit lines of bit line that the second reading power taking presses and applies with said second reading power taking and press the voltage that equates with the said storage unit that is read.
8. a cells of memory arrays information reading system comprises that memory cell array, low level produce circuit, electric current reads circuit, bit line strobe unit and word line strobe unit, it is characterized in that, also comprises a plurality of voltage follower circuits,
Said voltage follower circuit reads circuit with said electric current identical voltage is provided, and is higher than said low level and produces the voltage that circuit produces; Said low level generation circuit, electric current read circuit synchronouss working with voltage follower circuit;
Said word line strobe unit gating is read the word line of storage unit; Said bit line strobe unit is according to many continuous bit lines of the said storage array of bit line gating control signal while gating;
Said low level produces circuit and is connected with a bit line that is read cells of memory arrays through the bit line strobe unit; Said electric current reads circuit and is connected with another root bit line that is read cells of memory arrays through the bit line strobe unit; The input termination electric current of a plurality of voltage follower circuits reads the voltage output end of circuit, and the output terminal of each voltage follower circuit reads the adjacent continuous many bit lines of the bit line of circuit and connects with the electric current that is connected that is read storage unit respectively through the bit line strobe unit.
9. cells of memory arrays information reading system according to claim 8 is characterized in that said voltage follower circuit comprises an operational amplifier,
The in-phase input end of said operational amplifier connects the voltage output end that electric current reads circuit, and the output terminal of operational amplifier is connected on the bit line through the bit line strobe unit; The output terminal of said operational amplifier is connected with inverting input.
10. cells of memory arrays information reading system according to claim 9 is characterized in that said operational amplifier comprises control end,
When said control end was high level, the output end voltage of said operational amplifier equated with in-phase input end voltage;
When control end was low level, the output terminal of said operational amplifier was floating empty.
11. described according to Claim 8-10 cells of memory arrays information reading system; It is characterized in that; Said bit line strobe unit comprises a plurality of MOS transistors; A said bit line gating control signal connects the grid of a said MOS transistor, and a said bit line connects the source electrode of a said MOS transistor, and low level produces circuit, voltage follower circuit or electric current and reads the drain electrode that circuit connects said MOS transistor.
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| CN106997317A (en) * | 2015-10-02 | 2017-08-01 | 希捷科技有限公司 | Read by detecting leakage current and sensing the quick soft data of time |
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| CN105023611A (en) * | 2014-04-29 | 2015-11-04 | 爱思开海力士有限公司 | EPROM cell array, method of operating the same, and memory device including the same |
| CN105023611B (en) * | 2014-04-29 | 2019-12-06 | 爱思开海力士有限公司 | EPROM cell array, method of operating the same, and memory device including the same |
| CN106095037A (en) * | 2015-04-30 | 2016-11-09 | 联发科技股份有限公司 | Processing equipment and corresponding control methods |
| CN106095037B (en) * | 2015-04-30 | 2019-01-01 | 联发科技股份有限公司 | Processing equipment and corresponding control methods |
| CN104979012B (en) * | 2015-08-07 | 2019-04-19 | 上海华虹宏力半导体制造有限公司 | Memory circuit |
| CN104979012A (en) * | 2015-08-07 | 2015-10-14 | 上海华虹宏力半导体制造有限公司 | Memory circuit |
| CN106997317B (en) * | 2015-10-02 | 2021-05-07 | 希捷科技有限公司 | Fast soft data read by detecting leakage current and sensing time |
| CN106997317A (en) * | 2015-10-02 | 2017-08-01 | 希捷科技有限公司 | Read by detecting leakage current and sensing the quick soft data of time |
| CN106356095B (en) * | 2016-09-13 | 2019-11-15 | 中国科学院微电子研究所 | A kind of read operation method and device for nonvolatile memory |
| CN106356095A (en) * | 2016-09-13 | 2017-01-25 | 中国科学院微电子研究所 | Read operation method and device for nonvolatile storage |
| CN107886993A (en) * | 2017-10-27 | 2018-04-06 | 中国科学院上海微系统与信息技术研究所 | A kind of method of testing and test circuit of memory cell load voltage |
| CN108511021A (en) * | 2018-03-26 | 2018-09-07 | 上海华虹宏力半导体制造有限公司 | A kind of virtual ground flash memory reading circuit |
| CN108511021B (en) * | 2018-03-26 | 2020-10-27 | 上海华虹宏力半导体制造有限公司 | Virtual ground flash memory reading circuit |
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| CN102426852B (en) | 2015-03-04 |
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