CN107886993A - A kind of method of testing and test circuit of memory cell load voltage - Google Patents
A kind of method of testing and test circuit of memory cell load voltage Download PDFInfo
- Publication number
- CN107886993A CN107886993A CN201711022722.7A CN201711022722A CN107886993A CN 107886993 A CN107886993 A CN 107886993A CN 201711022722 A CN201711022722 A CN 201711022722A CN 107886993 A CN107886993 A CN 107886993A
- Authority
- CN
- China
- Prior art keywords
- memory cell
- voltage
- test
- bit
- cell load
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C2029/5004—Voltage
Landscapes
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Tests Of Electronic Circuits (AREA)
- Static Random-Access Memory (AREA)
Abstract
The present invention provides a kind of method of testing and test circuit of memory cell load voltage, including for entering the memory array of row information storage；The buffering isolated location being parallel on the bit line of memory array, bit-line voltage when obtaining memory cell operation in memory array from the output end of buffering isolated location, and the bit-line voltage that will be read is isolated with test lead, reduce influence of the electric capacity of test lead introducing to the bit-line voltage to be read, and then improve the accuracy of test result.The present invention tests voltage during memory cell operation using the voltage follower circuit structure in parallel with bit line, voltage follower output voltage approximation input voltage amplitude, and be in high-impedance state to front stage circuits, it is in low resistive state to late-class circuit, thus play " isolation " effect；During the phase-changing memory unit being selected by bit line input operation, voltage follower can test out the voltage by memory cell, improve testing progress and test obtains the voltage drop of memory cell.
Description
Technical field
The present invention relates to microelectronic, method of testing and test electricity more particularly to a kind of memory cell load voltage
Road.
Background technology
Phase change memory technology be based on Ovshinsky late 1960s (Phys.Rev.Lett., 21,1450
1453,1968) beginning of the seventies, (Appl.Phys.Lett., 18,254 phase-change thin films 257,1971) proposed can apply to phase
What the conception of change storage medium was set up, be a kind of cheap, stable performance memory device.Phase transition storage can be done
In silicon wafer substrate, its critical material is recordable phase-change thin film, heating electrode material, heat-insulating material and extraction electrode material
Study hotspot also just around its device technology deploy：The physical mechanism research of device, includes how to reduce device material etc..Phase transformation
The general principle of memory is to be acted on using electric impulse signal on device cell, make phase-change material amorphous state and polycrystalline state it
Between reversible transition occurs, low-resistance during high resistant and polycrystalline state during by differentiating amorphous state, it is possible to achieve write-in, the erasing of information
And read operation.
Phase transition storage is because with high speed reading, high erasable number, non-volatile, component size is small, low in energy consumption, anti-
The advantages that strong motion and radioresistance, thought most possibly to substitute current flash memories to form by International Semiconductor Industry Association
For future memory main product and at first as the device of commercial product.
Reading and writing, the wiping operation of phase transition storage are exactly to apply different in width and the voltage or electricity of height on device cell
Signal pulse stream：Operation (RESET) is wiped, when adding a short and strong pulse signal to make the phase-change material temperature liter in device cell
It is high to after more than fusion temperature, then by quick cooling so as to realizing phase-change material polycrystalline state to amorphous conversion, i.e. one state
To the conversion of " 0 " state；Write operation (SET), it is raised to phase-change material temperature when applying long and moderate strength a pulse signal
Under fusion temperature, on crystallization temperature after, and keep a period of time promote nucleus growth, so as to realize amorphous state to polycrystalline state
Conversion, i.e. " 0 " state to one state conversion；Read operation, it is very weak when adding a state to phase-change material not have an impact
Pulse signal after, its state is read by the resistance value of measurement device unit.
In order to accurately test phase transition storage operating parameter and its performance, the voltage drop of phase-changing memory unit and electric current are
Important test parameter, as shown in figure 1, in the prior art, testing electricity of the phase-change memory cell in operation in phase transition storage 1
The method that stream and voltage typically use the test voltage of oscillograph 2, but this method of testing can be by the electric capacity in the oscillograph 2
It is incorporated on the bit line of phase-change memory cell, the operation to phase-change memory cell impacts, and even results in operation failure, and
This method can not measure to the voltage drop of chip internal phase-change memory cell.There is also same for other kinds of memory
The problem of.
A kind of therefore, it is necessary to voltage ginseng when establishing accurate and convenient method of testing to test memory cell operation
Number.
The content of the invention
In view of the above the shortcomings that prior art, it is an object of the invention to provide a kind of memory cell load voltage
Method of testing and test circuit, for solving to test in the prior art present in voltage parameter when phase-change memory cell operates
The problems such as accuracy is poor, stability is low.
In order to achieve the above objects and other related objects, the present invention provides a kind of test side of memory cell load voltage
Method, the method for testing of the memory cell load voltage comprise at least：
Operation is written and read to the memory cell in memory array, will be carrying out where the memory cell of read-write operation
Bit-line voltage test after buffering is isolated is read, and isolates the electric capacity for reducing test lead introducing to the memory cell by buffering
Bit-line voltage influence, and then improve test result accuracy.
Preferably, the amplitude of signal after buffering isolation and the ratio of the amplitude of the bit-line voltage of the memory cell are 1.
It is highly preferred that buffering isolation is realized by way of voltage follow.
In order to achieve the above objects and other related objects, the present invention provides a kind of test electricity of memory cell load voltage
Road, the test circuit of the memory cell load voltage comprise at least：
Memory array, it is used for the storage into row information；
Isolated location is buffered, is parallel on the bit line of the memory array, from the output end of the buffering isolated location
Obtain bit-line voltage when memory cell in the memory array operates, and the bit-line voltage that will be read and test lead every
From, influence of the reduction test lead to the bit-line voltage to be read, and then improve the accuracy of test result.
Preferably, the memory array includes the phase-change memory cell that n rows m row are arranged in the form of an array, wherein, n, m
Respectively it is more than zero natural number.
Preferably, the memory array includes the variable-resistance memory unit that n rows m row are arranged in the form of an array, wherein, n, m
Respectively it is more than zero natural number.
Preferably, the input impedance of the buffering isolated location is not more than 10 Europe not less than 1 kilo-ohm, output impedance.
It is highly preferred that the buffering isolated location is voltage follower, the normal phase input end of the voltage follower and institute
The bit line connection of memory array is stated, the output end of the inverting input of the voltage follower and the voltage follower connects
Connect.
Preferably, the voltage follower is realized using operational amplifier.
It is highly preferred that the operational amplifier is realized using transistor or integrated chip.
As described above, the method for testing and test circuit of the memory cell load voltage of the present invention, have below beneficial to effect
Fruit：
Bit-line voltage and survey of the method for testing and test circuit of the memory cell load voltage of the present invention in memory cell
Examination increases voltage follower between end, high input-impedance stage of the voltage follower as whole circuit, can mitigate to signal source
Influence, while the bit-line voltage of memory cell when being written and read operation can be tested out.
Brief description of the drawings
Fig. 1 is shown as the principle schematic of memory cell load voltage method of testing of the prior art.
Fig. 2 is shown as the structural representation of the test circuit of the memory cell load voltage of the present invention.
Component label instructions
1 phase transition storage
2 oscillographs
3 memory arrays
4 buffering isolated locations
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through specific realities different in addition
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
Refer to Fig. 2.It should be noted that the diagram provided in the present embodiment only illustrates the present invention's in a schematic way
Basic conception, the component relevant with the present invention is only shown in schema then rather than according to component count during actual implement, shape
And size is drawn, kenel, quantity and the ratio of each component can be a kind of random change during its actual implementation, and its assembly layout
Kenel may also be increasingly complex.
As shown in Fig. 2 the present invention provides a kind of test circuit of memory cell load voltage, the memory cell load electricity
The test circuit of pressure comprises at least：
Memory array 3 and buffering isolated location 4.
As shown in Fig. 2 the memory array 3 is used for the storage into row information.
Specifically, the memory array 3 includes the phase-change memory cell that n rows m row are arranged in the form of an array, wherein, n, m
Respectively it is more than zero natural number, in actual applications, a phase transition storage list is comprised at least in the memory array 3
Member.As shown in Fig. 2 row control signal is word-line signal WL, row transmission signal is bit line signal BL, and the same time only has a word
Line and a bit line conducting, the phase-changing memory unit include phase change resistor and gate tube, wherein, the one of the phase change resistor
End connection bit line BL, the other end connect the drain terminal of the gate tube, and the grid end of the gate tube connects wordline WL, source ground connection.
In practical application, the memory array 3 can be resistance-variable storing device array, be not limited with the present embodiment.
As shown in Fig. 2 the buffering isolated location 4 is parallel on the bit line of the memory array 3, from the buffer compartment
Bit-line voltage when being operated from memory cell in the output end acquisition memory array 3 of unit 1, and the bit line that will be read
Voltage is isolated with test lead, reduces influence of the test lead to the bit-line voltage to be read, and then improve the accuracy of test result.
Specifically, in the present embodiment, a buffering isolated location 4 is all connected with each bit line, bit line is only shown in Fig. 2
The buffering isolated location 4 is connected on BL0, the buffering isolated location 4 connected on other bit lines is not shown.The buffering isolation
Unit 4 is in high-impedance state to front stage circuits, is in low resistive state to late-class circuit, thus " isolation " work is played to front stage circuit
With in the present embodiment, the input impedance of the buffering isolated location 4 is not more than 10 Europe not less than 1 kilo-ohm, output impedance, can
Needed to do specific setting according to actual parameter, be not limited with the present embodiment.
More specifically, in the present embodiment, the buffering isolated location 4 is voltage follower, the voltage follower
Normal phase input end is connected with the bit line of the memory array 3, the inverting input of the voltage follower and the voltage with
Connected with the output end of device, form backfeed loop.The voltage follower can use feedback factor for 1 homophase input amplifier
Realize, the amplifier welds to be formed using transistor, can also use integrated chip.In the present embodiment, using integrated computation
Amplifier forms voltage follower to realize the function of voltage follow.Due to the high gain characteristics of operational amplifier in itself, with collection
The voltage follower formed into amplifier has high input impedance, hardly draws electric current from signal source, while have extremely low
Output impedance, hardly internally cause voltage drop during to load output current, Ui=Uo, wherein, Ui is the memory
The voltage of memory cell is selected in array 3, Uo is the voltage that test lead is read.Oscillograph 3 is loaded into the buffer compartment
Voltage when output end from unit 4 can be obtained by phase-change memory cell operation, and does not influence to operate.
As shown in Fig. 2 the present invention also provides a kind of method of testing of memory cell load voltage, in the present embodiment, institute
State test circuit of the method for testing of memory cell load voltage based on the memory cell load voltage to realize, comprise at least：
Operation is written and read to the memory cell in the memory array 3, the storage list of read-write operation will be carrying out
The test after buffering isolation of bit-line voltage where first is read, and the electric capacity that reduction test lead introducing is isolated by buffering is deposited to described
The influence of the bit-line voltage of storage unit, and then improve the accuracy of test result.
Specifically, the amplitude of signal after buffering isolation and the ratio of the amplitude of the bit-line voltage of the memory cell are 1,
That is Ui=Uo, wherein, Ui is the voltage that memory cell is selected in the memory array 3, and Uo is the electricity that test lead is read
Pressure.In the present embodiment, buffering isolation is realized by the way of voltage follow, voltage follower can significantly reduce input electricity
The size of appearance, guarantee is provided for the input waveform of high-quality；Meanwhile voltage follower output voltage approximation input voltage amplitude,
And be in high-impedance state to front stage circuits, it is in low resistive state to late-class circuit, thus play " isolation " effect.
Bit-line voltage and survey of the method for testing and test circuit of the memory cell load voltage of the present invention in memory cell
Examination increases voltage follower between end, high input-impedance stage of the voltage follower as whole circuit, can mitigate to signal source
Influence, while the bit-line voltage of memory cell when being written and read operation can be tested out, and it is single to obtain chip internal storage
The voltage drop of member.
In summary, present invention offer a kind of method of testing and test circuit of memory cell load voltage, including for
Enter the memory array of row information storage；The buffering isolated location being parallel on the bit line of the memory array, delay from described
Rush bit-line voltage when memory cell operates in the output end acquisition memory array of isolated location, and the position that will be read
Line voltage is isolated with test lead, reduces influence of the electric capacity of test lead introducing to the bit-line voltage to be read, and then improve test
As a result accuracy.The method of testing and test circuit of the memory cell load voltage of the present invention use voltage follower and bit line
Circuit structure in parallel tests voltage during memory cell operation, voltage follower output voltage approximation input voltage amplitude,
And be in high-impedance state to front stage circuits, it is in low resistive state to late-class circuit, thus play " isolation " effect；Inputted and grasped by bit line
When making selected phase-changing memory unit, voltage follower can test out the voltage by memory cell, raising test into
Spend and test to obtain the voltage drop of memory cell.So the present invention effectively overcomes various shortcoming of the prior art and has height
Spend industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (10)
- A kind of 1. method of testing of memory cell load voltage, it is characterised in that the test side of the memory cell load voltage Method comprises at least：Operation is written and read to the memory cell in memory array, bit line where the memory cell of read-write operation being carrying out Voltage test after buffering is isolated is read, and isolates the position for reducing the electric capacity of test lead introducing to the memory cell by buffering The influence of line voltage, and then improve the accuracy of test result.
- 2. the method for testing of memory cell load voltage according to claim 1, it is characterised in that：Letter after buffering isolation Number the ratio of amplitude of bit-line voltage of amplitude and the memory cell be 1.
- 3. the method for testing of memory cell load voltage according to claim 1 or 2, it is characterised in that：By voltage with With mode realize buffering isolation.
- A kind of 4. test circuit of memory cell load voltage, it is characterised in that the test electricity of the memory cell load voltage Road comprises at least：Memory array, it is used for the storage into row information；Isolated location is buffered, is parallel on the bit line of the memory array, is obtained from the output end of the buffering isolated location Bit-line voltage when memory cell operates in the memory array, and the bit-line voltage that will be read is isolated with test lead, is subtracted Influence of the small test lead to the bit-line voltage to be read, and then improve the accuracy of test result.
- 5. the test circuit of memory cell load voltage according to claim 4, it is characterised in that：The memory array The phase-change memory cell arranged in the form of an array including n rows m row, wherein, n, m are respectively the natural number more than zero.
- 6. the test circuit of memory cell load voltage according to claim 4, it is characterised in that：The memory array The variable-resistance memory unit arranged in the form of an array including n rows m row, wherein, n, m are respectively the natural number more than zero.
- 7. the test circuit of memory cell load voltage according to claim 4, it is characterised in that：The buffering isolation is single The input impedance of member is not more than 10 Europe not less than 1 kilo-ohm, output impedance.
- 8. the test circuit of the memory cell load voltage according to claim 4 or 7, it is characterised in that：The buffer compartment It is voltage follower from unit, the normal phase input end of the voltage follower is connected with the bit line of the memory array, described The inverting input of voltage follower is connected with the output end of the voltage follower.
- 9. the test circuit of memory cell load voltage according to claim 4, it is characterised in that：The voltage follower Realized using operational amplifier.
- 10. the test circuit of memory cell load voltage according to claim 9, it is characterised in that：The operation amplifier Device is realized using transistor or integrated chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711022722.7A CN107886993A (en) | 2017-10-27 | 2017-10-27 | A kind of method of testing and test circuit of memory cell load voltage |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711022722.7A CN107886993A (en) | 2017-10-27 | 2017-10-27 | A kind of method of testing and test circuit of memory cell load voltage |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107886993A true CN107886993A (en) | 2018-04-06 |
Family
ID=61782743
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711022722.7A Pending CN107886993A (en) | 2017-10-27 | 2017-10-27 | A kind of method of testing and test circuit of memory cell load voltage |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107886993A (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5973571A (en) * | 1997-02-27 | 1999-10-26 | Nec Corporation | Semiconductor integrated circuit having a phase locked loop |
| US20060170433A1 (en) * | 2005-02-01 | 2006-08-03 | Samsung Electronics Co., Ltd. | Semiconductor test circuit |
| CN102004197A (en) * | 2009-09-02 | 2011-04-06 | 三星电子株式会社 | Method for measuring a resistance of resist memory device and the resistance measuring system |
| CN102426848A (en) * | 2011-11-30 | 2012-04-25 | 中国科学院微电子研究所 | Method and system for reading information of storage array unit |
| CN102426852A (en) * | 2011-11-30 | 2012-04-25 | 中国科学院微电子研究所 | Method and system for reading information of storage array unit |
| CN102831935A (en) * | 2012-05-18 | 2012-12-19 | 华中科技大学 | Pulse I-V (intravenous) characteristic testing method and device of phase change memory unit |
-
2017
- 2017-10-27 CN CN201711022722.7A patent/CN107886993A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5973571A (en) * | 1997-02-27 | 1999-10-26 | Nec Corporation | Semiconductor integrated circuit having a phase locked loop |
| US20060170433A1 (en) * | 2005-02-01 | 2006-08-03 | Samsung Electronics Co., Ltd. | Semiconductor test circuit |
| CN102004197A (en) * | 2009-09-02 | 2011-04-06 | 三星电子株式会社 | Method for measuring a resistance of resist memory device and the resistance measuring system |
| CN102426848A (en) * | 2011-11-30 | 2012-04-25 | 中国科学院微电子研究所 | Method and system for reading information of storage array unit |
| CN102426852A (en) * | 2011-11-30 | 2012-04-25 | 中国科学院微电子研究所 | Method and system for reading information of storage array unit |
| CN102831935A (en) * | 2012-05-18 | 2012-12-19 | 华中科技大学 | Pulse I-V (intravenous) characteristic testing method and device of phase change memory unit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Gill et al. | Ovonic unified memory-a high-performance nonvolatile memory technology for stand-alone memory and embedded applications | |
| CN108092658B (en) | Logic circuit operation method | |
| CN102067234B (en) | Method for writing to resistance-change non-volatile memory elements, and resistance-change non-volatile memory device | |
| CN108475519A (en) | Including memory and its device and method of operation | |
| CN107799133A (en) | Sensing amplifier, storage device and include its system | |
| TWI447729B (en) | Static random access memory and methods for static random access memory | |
| CN106356090B (en) | Phase transition storage reading circuit and its method for reading data | |
| CN106205684B (en) | A kind of phase transition storage reading circuit and reading method | |
| CN103390432A (en) | Architecture, system and method for testing resistive type memory | |
| US20100188894A1 (en) | In-situ resistance measurement for magnetic random access memory (mram) | |
| US9659641B2 (en) | On-chip resistance measurement circuit and resistive memory device including the same | |
| TWI523014B (en) | Select device for cross point memory structures | |
| CN104303234B (en) | Storage circuit | |
| CN105931665B (en) | Phase change memory reading circuit and method | |
| TW525160B (en) | Magneto-resistive memory and its reading-out method | |
| Fieback et al. | Testing resistive memories: Where are we and what is missing? | |
| CN102831935B (en) | Pulse I-V (intravenous) characteristic testing method and device of phase change memory unit | |
| CN110289028A (en) | Control signal generator for sense amplifier and the memory devices including it | |
| CN108335715A (en) | Nonvolatile semiconductor memory member and its operating method | |
| CN110289037A (en) | Nonvolatile storage reading circuit and reading method | |
| US9672888B2 (en) | Apparatuses and methods for setting a signal in variable resistance memory | |
| CN107886993A (en) | A kind of method of testing and test circuit of memory cell load voltage | |
| CN100585728C (en) | Word line voltage compensation method for write current in phase change memory array | |
| Gupta et al. | Design exploration of IGZO diode based VCMA array design for Storage Class Memory Applications | |
| Kang et al. | Readability challenges in deeply scaled STT-MRAM |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20180406 |