CN102426826A - Display controller, display device, display system and method for controlling display device - Google Patents

Display controller, display device, display system and method for controlling display device Download PDF

Info

Publication number
CN102426826A
CN102426826A CN2011103394764A CN201110339476A CN102426826A CN 102426826 A CN102426826 A CN 102426826A CN 2011103394764 A CN2011103394764 A CN 2011103394764A CN 201110339476 A CN201110339476 A CN 201110339476A CN 102426826 A CN102426826 A CN 102426826A
Authority
CN
China
Prior art keywords
during
display device
signal line
signal
pixel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2011103394764A
Other languages
Chinese (zh)
Other versions
CN102426826B (en
Inventor
柳俊洋
宫本拓治
村井淳人
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Publication of CN102426826A publication Critical patent/CN102426826A/en
Application granted granted Critical
Publication of CN102426826B publication Critical patent/CN102426826B/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G09G2310/062—Waveforms for resetting a plurality of scan lines at a time
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/08—Details of image data interface between the display device controller and the data line driver circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal
    • G09G5/008—Clock recovery

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

In one embodiment of the present invention, a display controller includes a stable pixel writing period in one horizontal period in a display device, the stable pixel writing period being a period during which a voltage outputted from a gate driver is at a high level. The display controller also includes a first stable pixel writing period determination circuit which determines, by using a reference signal independent from the frame rate in the display device, the stable pixel writing period during which the voltage is at the high level. Thus, the display controller can be provided in which, regardless of whether and how the frame rate is changed, the stable pixel writing period can be of a target length.

Description

Display controller, display device, display system and method for controlling display device
Application of the present invention is that international application no is PCT/WO2008/029546; International filing date is on June 8th, 2007; The application number that gets into the China national stage is 200780029423.4, and name is called the dividing an application of application for a patent for invention of " display controller, display device, display system and method for controlling display device ".
Technical field
The present invention relates to control display device display controller, utilize display device that display controller controls and the display system that constitutes by display device and display controller.
Background technology
Liquid crystal indicator just is being widely used the display element into televisor or graphic alphanumeric display etc.Wherein, Especially each display pixel is provided with thin film transistor (TFT) (Thin Film Transistor; Below be called TFT) etc. the liquid crystal indicator of on-off element; Even the quantity of display pixel increases, the display image of the excellence that also can obtain between adjacent display pixels, not crosstalk, therefore noticeable especially.
Such liquid crystal indicator is shown in figure 24; Constitute its major part by display panels 500 and driving circuit portion; Display panels 500 maintains liquid-crystal composition between the pair of electrodes substrate, and on the outside surface of each electrode base board, is pasted with Polarizer respectively.
Tft array substrate as one of them electrode base board; Be on transparent insulating substrates 100 such as glass, mutually orthogonal many data signal line S (1), S (2) ... S (i) ... S (N) and scan signal line G (1), G (2) ... G (j) ... G (M) forms the ranks shape.And, at each cross part of these data signal lines and scan signal line, form the on-off element 102 that constitutes by the TFT that is connected with pixel electrode 103, and alignment films is set they almost coverings all sidedly, form tft array substrate.
On the other hand, identical as the counter substrate of another electrode base board with tft array substrate, be on transparent insulating substrates such as glass, on whole, stack gradually opposite electrode 101 and form with alignment films.Then; Utilize scan signal line drive circuit 300, data signal wire driving circuit 200 that is connected with each data signal line that is connected with each scan signal line of the display panels of formation like this and the opposite electrode driving circuit COM that is connected with opposite electrode, form above-mentioned driving circuit portion.
Scan signal line drive circuit 300 is shown in figure 25, forms by the 300a of shift LD portion that constitutes of M bistable multivibrator of series connection and according to the SS 300b that the output of each bistable multivibrator is switched.
Being enough to make TFT to input terminal VD1 of each SS 300b input is the gate turn-on voltage (Vgh voltage) of on-state, and being enough to make TFT to another input terminal VD2 input is the grid off voltage (Vgl voltage) of off-state.Thereby data-signal (GSP) is transferred to bistable multivibrator successively according to clock signal (GCK), and exports to SS 300b successively.SS 300b responds to this; Selecting to make TFT in a scan period (TH) is the Vgh voltage of on-state; And output to scan signal line G (1), G (2) ... G (j) ... G (M), then to scan signal line G (1), G (2) ... G (j) ... It is off-state Vgl voltage that G (M) output makes TFT.By means of this action, can with output to from data signal wire driving circuit 200 separately data signal line S (1), S (2) ... S (i) ... The vision signal of S (N) writes in each corresponding pixel.
And the scan signal line drive circuit that patent documentation 1 is put down in writing utilizes following circuit to generate above-mentioned VD1 voltage.That is to say that this circuit is shown in figure 26, by the resistance R cnt and the capacitor Ccnt that are used for carrying out charging and discharging, the switch SW 1 and the switch SW 2 that are used for controlling the inverter INV of this charging and discharging and are used for switching charging and discharging constitute.A terminal to switch SW1 applies signal voltage Vdd.This signal voltage Vdd has that to be enough to make above-mentioned TFT be the DC voltage of Vgh voltage of the level of on-state.Another terminal of this switch SW 1 is connected with the end of resistance R cnt, also is connected with the end of capacitor Ccnt.The other end of above-mentioned resistance R cnt is through above-mentioned switch SW 2 ground connection.The switch control of this switch SW 2 is carried out according to the Stc signal via inverter INV input.This Stc signal is synchronous a scan period, also carries out the switch control of above-mentioned switch SW 1.
At the Stc signal is under the situation of high level, and switch SW 1 is an on-state, for this switch SW 2, owing to apply low level via inverter INV, so switch SW 2 is an off-state.On the contrary, be under the low level situation at the Stc signal, switch SW 1 is an off-state, at this moment, for switch SW 2, owing to apply high level via inverter INV, so switch SW 2 is an on-state.
The output signal VD1 that in this circuit, generates is connected with the input terminal VD1 of the scan signal line drive circuit 300 shown in Figure 25.Shown in figure 27, the Stc signal is the clock signal during the control grid negative edge, is and a scan period (TH) synperiodic signal.
At the Stc signal is between high period, because switch SW 1 be on-state, and switch SW 2 be off-state, exports to the input terminal VD1 of scan signal line drive circuit 300 as the voltage of level Vgh so export VD1.On the contrary, be between low period at the Stc signal, switch SW 1 is an off-state, and switch SW 2 is on-state, and the electric charge that is held among the capacitor Ccnt is through resistance R cnt discharge, and voltage level descends gradually.As a result, output signal VD1a is a sawtooth wave shown in figure 27.
If will be transferred to the input terminal VD1 of scan signal line drive circuit 300 by the output signal VD1 that foregoing circuit generates; Then shown in the VG (j) of Figure 27, the negative edge of scan signal line (outputing to the negative edge of the open-grid voltage of scan signal line) might be easy to generate sloping waveform.As stated, utilize above-mentioned sawtooth wave, make scan signal line have the slope, thereby can control this slope according to the signal delay transport property of scan signal line.Thereby the parasitic capacity that parasitism is present on the scan signal line is caused, and the level that in pixel potential, produces moves in display surface roughly even.
Patent documentation 1: Japanese publication communique " spy opens 2003-345317 communique (open day: put down on Dec 3rd, 15) "
Patent documentation 2: Japanese publication communique " spy opens flat 6-3647 communique (open day: put down on January 14th, 6) "
Summary of the invention
Yet, in the technology that above-mentioned patent documentation 1 is put down in writing, be to control GS signal (Stc signal through the Dot Clock signal is counted; The grid ramp signal) during the grid slope (Vgh reduce during).Therefore, the Dot Clock signal also can change under the situation of refresh rate changing, thus exist can't with pixel is stable write during during (between the Vgh period of output) and the grid slope (during the Vgh reduction) be set at expectation during problem.
That is to say, have following problem, promptly pixel is stable write during during (between the Vgh period of output) and the grid slope (Vgh reduce during) understand and change corresponding to refresh rate.
Specifically, change refresh rate exactly, making it is the situation of 60Hz from refresh rate shown in Figure 28, becomes the situation that refresh rate shown in Figure 29 is 40Hz.If to set 811CK be that pixel is stable write during (between the Vgh period of output), then shown in figure 28, be under the situation of 60Hz at refresh rate; Pixel is stable write during (between the Vgh period of output) be 16.9 microseconds; (Vgh reduce during) is 10 microseconds during the grid slope, and is under the situation of 40Hz at refresh rate, and be shown in figure 29; Pixel is stable write during (between the Vgh period of output) be 25.3 microseconds, (Vgh reduce during) is 15 microseconds during the grid slope.Promptly; When refresh rate changes; Corresponding to this variation, pixel is stable write during during (between the Vgh period of output) and the grid slope (Vgh reduce during) can change, during can't making that pixel is stable and writing during (between the Vgh period of output) and the grid slope (during the Vgh reduction) be expectation value.
In addition, Figure 30 be expression to refresh rate be Dot Clock signal frequency, clock count value, Hsync cycle, the pixel of situation of situation and the 40Hz of 60Hz stablize write during (between the Vgh period of output; During the GS_High; The gate turn-on width) and during the grid slope (during Vgh reduces; During the GS_Low; Grid slope width) form that compares.Shown in this table,,, then also change during respectively if refresh rate is different because during writing with Dot Clock signal deciding pixel is stable during (between the Vgh period of output) and the grid slope (Vgh reduce during).
The present invention makes in view of the above problems, its purpose be to provide a kind of can irrespectively make that pixel is stable with the variation of refresh rate (frame frequency) and write during and/or be the display controller of expectation value, display device and display system during the grid slope.
In order to address the above problem; Display controller of the present invention; Display device to having a plurality of pixels, video signal cable, scan signal line and scan signal line drive circuit is controlled; Wherein, the said pixel of said vision signal alignment provides data-signal, and said scan signal line and said video signal cable are arranged in a crossed manner; Said scan signal line drive circuit to said scan signal line output scanning signal to drive said scan signal line; This display controller is characterised in that, in a horizontal period of above-mentioned display device, have be stable the writing of pixel of high level from the voltage level of said scanning signals line drive circuit output during; Have and use and the irrelevant reference signal of the frame frequency of above-mentioned display device, determine that above-mentioned voltage level is to determine parts during stable the writing of pixel during stable the writing of pixel of high level.
In addition, in order to address the above problem method for controlling display device of the present invention; Display device to having a plurality of pixels, video signal cable, scan signal line and scan signal line drive circuit is controlled; Wherein, the said pixel of said vision signal alignment provides data-signal, and said scan signal line and said video signal cable are arranged in a crossed manner; Said scan signal line drive circuit to said scan signal line output scanning signal to drive said scan signal line; This display-apparatus control method is characterised in that, in a horizontal period of above-mentioned display device, have be stable the writing of pixel of high level from the voltage level of said scanning signals line drive circuit output during; And the irrelevant reference signal of the frame frequency of utilization and above-mentioned display device, determine that above-mentioned voltage level is stable the writing of pixel of high level during.
If the employing said structure then uses and the irrelevant reference signal of frame frequency, decide voltage level to be stable the writing of pixel of high level (Vgh voltage) during.Thereby during can determining irrespectively that pixel is stable and write with frame frequency.Therefore, can with the variation of frame frequency irrespectively with pixel is stable write during decision be expectation value.
In addition, comparatively ideally be, in display controller of the present invention, even frame frequency changes, above-mentioned pixel is stable write during the decision parts also can keep during stable the writing of above-mentioned pixel of temporary transient decision.
In addition; In order to address the above problem, display controller of the present invention is controlled the display device with a plurality of pixels, video signal cable, scan signal line and scan signal line drive circuit; Wherein, The said pixel of said vision signal alignment provides data-signal, and said scan signal line and said video signal cable are arranged in a crossed manner, said scan signal line drive circuit to said scan signal line output scanning signal to drive said scan signal line; This display controller is characterised in that; In a horizontal period of above-mentioned display device, have be stable the writing of pixel of high level from the voltage level of said scanning signals line drive circuit output during, have frame frequency according to above-mentioned display device; The count value of the Dot Clock signal of above-mentioned display device is changed, thereby determine that above-mentioned voltage level is to determine parts during stable the writing of pixel during stable the writing of pixel of high level.
Also have; In order to address the above problem, method for controlling display device of the present invention is controlled the display device with a plurality of pixels, video signal cable, scan signal line and scan signal line drive circuit; Wherein, The said pixel of said vision signal alignment provides data-signal, and said scan signal line and said video signal cable are arranged in a crossed manner, said scan signal line drive circuit to said scan signal line output scanning signal to drive said scan signal line; This display-apparatus control method is characterised in that
In a horizontal period of above-mentioned display device; Have be stable the writing of pixel of high level from the voltage level of said scanning signals line drive circuit output during; And according to the frame frequency of above-mentioned display device; The count value of the Dot Clock signal of above-mentioned display device is changed, thereby during determining that above-mentioned voltage level is stable the writing of pixel of high level.
If adopt said structure and method, then according to the frame frequency of display device, the count value of the Dot Clock signal of display device is changed, thereby during the decision voltage level is stable the writing of pixel of high level.Therefore,, in this variation, the count value of Dot Clock signal is changed, during can controlling at random also that pixel is stable and writing even under the situation that frame frequency changes.
In addition, comparatively ideally be that display-apparatus control method of the present invention is even frame frequency changes during stable the writing of above-mentioned pixel that also can keep temporary transient decision.
If the employing said structure, even then above-mentioned pixel is stable write during decision parts frame frequency change also the above-mentioned pixel of keeping temporary transient decision is stable write during.Therefore, even frame frequency changes, during also can fixed pixel writing.Thereby, can make the charge rate of pixel certain, and can prevent on showing, to give the user with uncomfortable sensation.
In addition, comparatively ideally be, in display controller of the present invention, above-mentioned pixel is stable write during the decision parts change corresponding to the kind of above-mentioned display device during making that above-mentioned pixel is stable and writing.
In addition, comparatively ideally be that in display-apparatus control method of the present invention, the kind corresponding to above-mentioned display device during making that above-mentioned pixel is stable and writing changes.
If the employing said structure, pixel is stable to be changed corresponding to the kind of display device during writing.Therefore, can set suitable pixel and write each display device during.
In addition; Comparatively ideal is that in display controller of the present invention, also tool is according to the kind of above-mentioned display device; The decision above-mentioned pixel that parts determined was stable during distribution write by above-mentioned pixel is stable write during, the register during any in preestablishing during these.
In addition, comparatively ideally be, in display-apparatus control method of the present invention, according to the kind of above-mentioned display device, during distributing that above-mentioned pixel is stable and writing, and during in preestablishing during these any.
If the employing said structure then also has the kind according to above-mentioned display device, during distributing that the decision above-mentioned pixel that parts determined is stable during writing by pixel is stable and writing, and the register during in deciding during these through setting any.Therefore, can utilize register to preestablish that pixel is stable to write during.That is to say, utilize simple parts, during just can setting that the decision pixel that parts determined is stable during writing by pixel is stable and writing.
In addition, comparatively ideal is that in display controller of the present invention, the kind of above-mentioned display device is to be arranged at the size condition of the panel in the above-mentioned display device or the resolution condition of above-mentioned display device at least.
In addition, comparatively ideal is that in display-apparatus control method of the present invention, the kind of above-mentioned display device is to be arranged at the size condition of the panel in the above-mentioned display device or the resolution condition of above-mentioned display device at least.
In addition, comparatively ideal is that display device of the present invention has the control assembly of being controlled by above-mentioned any display controller.
In addition, comparatively ideally be that display system of the present invention constitutes by above-mentioned any display controller with by the display device of this display controller control.
In addition, in order to address the above problem display controller of the present invention; Display device to having a plurality of pixels, video signal cable, scan signal line and scan signal line drive circuit is controlled; Wherein, the said pixel of said vision signal alignment provides data-signal, and said scan signal line and said video signal cable are arranged in a crossed manner; Said scan signal line drive circuit to said scan signal line output scanning signal to drive said scan signal line; This display controller is characterised in that, in a horizontal period of above-mentioned display device, has during the grid slope that the voltage level of said scanning signals line drive circuit output reduces; Have and use and the irrelevant reference signal of the frame frequency of above-mentioned display device, determine to determine parts during the grid slope during the grid slope that above-mentioned voltage level reduces.
In addition, in order to address the above problem display-apparatus control method of the present invention; Display device to having a plurality of pixels, video signal cable, scan signal line and scan signal line drive circuit is controlled; Wherein, the said pixel of said vision signal alignment provides data-signal, and said scan signal line and said video signal cable are arranged in a crossed manner; Said scan signal line drive circuit to said scan signal line output scanning signal to drive said scan signal line; This display-apparatus control method is characterised in that, in a horizontal period of above-mentioned display device, has during the grid slope that the voltage level of said scanning signals line drive circuit output reduces; Use and the irrelevant reference signal of the frame frequency of above-mentioned display device, determine during the grid slope of above-mentioned voltage level reduction.
If the employing said structure uses and the irrelevant reference signal of frame frequency, during the grid slope that the decision voltage level reduces.Thereby, can irrespectively determine the grid slope with frame frequency during.Therefore, can irrespectively make with the variation of frame frequency and be expectation value during the grid slope.
In addition, in order to address the above problem display device of the present invention; Display device to having a plurality of pixels, video signal cable, scan signal line and scan signal line drive circuit is controlled, and wherein, the said pixel of said vision signal alignment provides data-signal; Said scan signal line and said video signal cable are arranged in a crossed manner; To drive said scan signal line, this display controller is characterised in that said scan signal line drive circuit to said scan signal line output scanning signal
In a horizontal period of above-mentioned display device, have during the grid slope that the voltage level of said scanning signals line drive circuit output reduces,
Have frame frequency, the count value of the Dot Clock signal of above-mentioned display device is changed, thereby determine to determine parts during the grid slope during the grid slope that above-mentioned voltage level reduces according to above-mentioned display device.
In addition; In order to address the above problem, display-apparatus control method of the present invention is controlled the display device with a plurality of pixels, video signal cable, scan signal line and scan signal line drive circuit; Wherein, The said pixel of said vision signal alignment provides data-signal, and said scan signal line and said video signal cable are arranged in a crossed manner, said scan signal line drive circuit to said scan signal line output scanning signal to drive said scan signal line; This display-apparatus control method is characterised in that; In a horizontal period of above-mentioned display device, have during the grid slope that the voltage level of said scanning signals line drive circuit output reduces, according to the frame frequency of above-mentioned display device; The count value of the Dot Clock signal of above-mentioned display device is changed, thereby determine during the grid slope of above-mentioned voltage level reduction.
If adopt said structure and method, then according to the frame frequency of display device, the count value of the Dot Clock signal of display device is changed, thereby during the grid slope that the decision voltage level reduces.Therefore, even under the situation that frame frequency changes, in this variation, change, also can at random control during the grid slope through the count value that initiatively makes the Dot Clock signal.
In addition, comparatively ideal is that in display controller of the present invention, even frame frequency changes, the decision parts also can be kept during the above-mentioned grid slope of temporary transient decision during the above-mentioned grid slope.
In addition, comparatively ideally be, in display-apparatus control method of the present invention, even frame frequency changes during the above-mentioned grid slope that also can keep temporary transient decision.
If the employing said structure, can stationary plane in the reduction amount of flicker and Δ V, even the frame frequency variation also can prevent the generation of glimmering.
In addition, comparatively ideally be that in display controller of the present invention, the decision parts make that the kind according to above-mentioned display device changes during the above-mentioned grid slope during the above-mentioned grid slope.
In addition, comparatively ideally be in display-apparatus control method of the present invention, to make that the kind according to above-mentioned display device changes during the above-mentioned grid slope.
If the employing said structure can change during the grid slope according to the kind of display device.Therefore, can set suitable grid slope to each display device during.
In addition; Comparatively ideal is in display controller of the present invention, also to have the kind according to above-mentioned display device; Distribution by above-mentioned grid slope during during decision the above-mentioned grid slope that parts determined, and the register during in preestablishing during these any.
In addition, comparatively ideally be, in display-apparatus control method of the present invention,, distribute during the above-mentioned grid slope according to the kind of above-mentioned display device, and during in preestablishing during these any.
If the employing said structure then has the kind according to above-mentioned display device, distribute by during the decision above-mentioned grid slope that parts determined during the grid slope, and the register during in deciding during these through setting any.Therefore, utilize register can preestablish during the grid slope.That is to say, utilize simple parts just can set by during the decision grid slope that parts determined during the grid slope.
In addition, comparatively ideal is that in display controller of the present invention, the kind of above-mentioned display device is to be arranged at the size condition of the panel in the above-mentioned display device or the resolution condition of above-mentioned display device at least.
In addition, comparatively ideal is that in display-apparatus control method of the present invention, the kind of above-mentioned display device is to be arranged at the size condition of the panel in the above-mentioned display device or the resolution condition of above-mentioned display device at least.
In addition, comparatively ideal is that display device of the present invention has the control assembly of being controlled by above-mentioned any display controller.
In addition, comparatively ideally be that display system of the present invention constitutes by above-mentioned any display controller with by the display device of this display controller control.
In addition; In order to address the above problem; Display controller of the present invention; Display device to having a plurality of pixels, video signal cable, scan signal line, on-off element and scan signal line drive circuit is controlled, and wherein, the said pixel of said vision signal alignment provides data-signal; Said scan signal line and said video signal cable are arranged in a crossed manner; Said on-off element is arranged on the intersection point of said scan signal line and said video signal cable, and to drive said scan signal line, this display controller is characterised in that said scan signal line drive circuit to said scan signal line output scanning signal; In a horizontal period of above-mentioned display device; Have during being stable the writing of pixel of high level from the voltage level of said scanning signals line drive circuit output, during the grid slope that the voltage level of said scanning signals line drive circuit output reduces and from the voltage level of said scanning signals line drive circuit output be low level on-off element between the off period, have and use and the first irrelevant reference signal of frame frequency, determine parts during stable the writing of pixel of decision voltage level during to be that the above-mentioned pixel of high level is stable write; And the second irrelevant reference signal of use and frame frequency, so that above-mentioned pixel is stable during writing terminal is determined to determine parts during the grid slope during the above-mentioned grid slope as ground, top.
In addition; In order to address the above problem; Display-apparatus control method of the present invention is controlled the display device with a plurality of pixels, video signal cable, scan signal line, on-off element and scan signal line drive circuit, wherein; The said pixel of said vision signal alignment provides data-signal; Said scan signal line and said video signal cable are arranged in a crossed manner, and said on-off element is arranged on the intersection point of said scan signal line and said video signal cable, said scan signal line drive circuit to said scan signal line output scanning signal to drive said scan signal line; This display-apparatus control method is characterised in that; In a horizontal period of above-mentioned display device, have during being stable the writing of pixel of high level from the voltage level of said scanning signals line drive circuit output, during the grid slope that the voltage level of said scanning signals line drive circuit output reduces and from the voltage level of said scanning signals line drive circuit output be low level on-off element between the off period, use and the first irrelevant reference signal of frame frequency; During the decision voltage level is stable the writing of above-mentioned pixel of high level
Use and the second irrelevant reference signal of frame frequency, with above-mentioned pixel is stable during writing terminal as the above-mentioned grid of decision slope, ground, top during, and between the off period, make above-mentioned on-off element stop to move at above-mentioned on-off element.
If the employing said structure then uses and the first irrelevant reference signal of frame frequency, the decision pixel is stable write during, and equally with pixel is stable during writing terminal as top, use and the second irrelevant reference signal of frame frequency, during the decision grid slope.Thereby during can setting respectively irrespectively that pixel is stable and write with the variation of frame frequency and be expectation value during the grid slope.And, in the invention of method, the non-pixel in a horizontal period is stable write during during the non-again grid slope (from the terminal during the grid slope till reset with next horizontal-drive signal during), make on-off element stop to move.That is to say, in a horizontal period, during setting respectively that pixel is stable and writing and be arbitrary value during the grid slope, and, then force the action of shutdown switch element for during remaining.Thereby during can setting respectively irrespectively that pixel is stable and write with the variation of frame frequency and be expectation value during the grid slope.
In addition; Display controller of the present invention; Display device to having a plurality of pixels, video signal cable, scan signal line, on-off element and scan signal line drive circuit is controlled; Wherein, The said pixel of said vision signal alignment provides data-signal; Said scan signal line and said video signal cable are arranged in a crossed manner, and said on-off element is arranged on the intersection point of said scan signal line and said video signal cable, said scan signal line drive circuit to said scan signal line output scanning signal to drive said scan signal line; This display controller is characterised in that; In a horizontal period of above-mentioned display device, have during being stable the writing of pixel of high level from the voltage level of said scanning signals line drive circuit output, during the grid slope that the voltage level of said scanning signals line drive circuit output reduces and from the voltage level of said scanning signals line drive circuit output be low level on-off element between the off period to have frame frequency according to above-mentioned display device; The count value of the Dot Clock signal of above-mentioned display device is changed, thereby determine that above-mentioned voltage level is to determine parts during stable the writing of pixel during stable the writing of pixel of high level; And, the count value of the Dot Clock signal of above-mentioned display device is changed according to the frame frequency of above-mentioned display device, so that above-mentioned pixel is stable during writing terminal is determined to determine parts during the grid slope during the above-mentioned grid slope as ground, top.
In addition; Display-apparatus control method of the present invention; Display device to having a plurality of pixels, video signal cable, scan signal line, on-off element and scan signal line drive circuit is controlled, and wherein, the said pixel of said vision signal alignment provides data-signal; Said scan signal line and said video signal cable are arranged in a crossed manner; Said on-off element is arranged on the intersection point of said scan signal line and said video signal cable, and to drive said scan signal line, this display-apparatus control method is characterised in that said scan signal line drive circuit to said scan signal line output scanning signal; In a horizontal period of above-mentioned display device; Have during being stable the writing of pixel of high level from the voltage level of said scanning signals line drive circuit output, during the grid slope that the voltage level of said scanning signals line drive circuit output reduces and from the voltage level of said scanning signals line drive circuit output be low level on-off element between the off period,, the count value of the Dot Clock signal of above-mentioned display device is changed according to the frame frequency of above-mentioned display device; Thereby during determining that above-mentioned voltage level is stable the writing of pixel of high level; Also, the count value of the Dot Clock signal of above-mentioned display device is changed, during above-mentioned pixel is stable during writing terminal is determined above-mentioned grid slope as ground, top according to the frame frequency of above-mentioned display device; Between the off period, make above-mentioned on-off element stop action at above-mentioned on-off element.
If adopt said structure and method, according to the frame frequency of display device, the count value of the Dot Clock signal of display device is changed, thereby the decision pixel is stable write during and during the grid slope.Therefore,, in this variation, the count value of Dot Clock signal is changed, during can controlling arbitrarily respectively also that pixel is stable and writing and during the grid slope even under the situation that frame frequency changes.
In addition, comparatively ideally be, in display controller of the present invention, even frame frequency changes, above-mentioned pixel is stable write during the decision parts also can keep during stable the writing of above-mentioned pixel of temporary transient decision.
In addition, comparatively ideally be, in display-apparatus control method of the present invention, even frame frequency changes during stable the writing of above-mentioned pixel that also can keep temporary transient decision.
If the employing said structure, even then frame frequency changes, above-mentioned pixel is stable write during the decision parts also can keep during stable the writing of above-mentioned pixel of temporary transient decision.Therefore, even frame frequency changes, during also can fixed pixel writing.Thereby, can make the charge rate of pixel certain, and make the user that uncomfortable sensation arranged on can preventing to show.
In addition, comparatively ideal is that in display controller of the present invention, even frame frequency changes, the decision parts also can be kept during the above-mentioned grid slope of temporary transient decision during the above-mentioned grid slope.
In addition, comparatively ideally be, in display-apparatus control method of the present invention, even frame frequency changes during the above-mentioned grid slope that also can keep temporary transient decision.
If the employing said structure, then can stationary plane in the reduction amount of flicker and Δ V, even the frame frequency variation also can prevent the generation of glimmering.
In addition, comparatively ideally be, in display controller of the present invention, above-mentioned pixel is stable write during the decision parts change according to the kind of above-mentioned display device during making that above-mentioned pixel is stable and writing.
In addition, comparatively ideally be that in display-apparatus control method of the present invention, the kind according to above-mentioned display device during making that above-mentioned pixel is stable and writing changes.
If the employing said structure, then pixel is stable changes according to the kind of display device during writing.Therefore, can set suitable pixel and write each display device during.
In addition, comparatively ideally be that in display controller of the present invention, the decision parts make that the kind according to above-mentioned display device changes during the above-mentioned grid slope during the above-mentioned grid slope.
In addition, comparatively ideally be in display-apparatus control method of the present invention, to make that the kind according to above-mentioned display device changes during the above-mentioned grid slope.
If the employing said structure then can change according to the kind of display device during the grid slope.Therefore, can set suitable grid slope to each display device during.
In addition; Comparatively ideal is in display controller of the present invention, also to have the kind according to above-mentioned display device; The decision above-mentioned pixel that parts determined was stable during distribution write by above-mentioned pixel is stable write during, and the register during in preestablishing during these any.
In addition, comparatively ideally be, in display-apparatus control method of the present invention, according to the kind of above-mentioned display device, during distributing that above-mentioned pixel is stable and writing, and during in preestablishing during these any.
If the employing said structure then also has the kind according to above-mentioned display device, during distributing that the decision above-mentioned pixel that parts determined is stable during writing by pixel is stable and writing, and the register during in deciding during these through setting any.Therefore, utilize register can preestablish that pixel is stable to write during.That is to say, the decision pixel that parts determined is stable during utilizing simple parts just can set to write by pixel is stable write during.
In addition; Comparatively ideal is in display controller of the present invention, also to have the kind according to above-mentioned display device; Distribution by above-mentioned grid slope during during decision the above-mentioned grid slope that parts determined, and the register during in preestablishing during these any.
In addition, comparatively ideally be, in display-apparatus control method of the present invention,, distribute during the above-mentioned grid slope according to the kind of above-mentioned display device, and during in preestablishing during these any.
If the employing said structure then also has the kind according to above-mentioned display device, distribute by during the decision above-mentioned grid slope that parts determined during the grid slope, and the register during in deciding during these through setting any.Therefore, utilize register, can preestablish during the grid slope.That is to say, utilize simple parts just can set by during the decision grid slope that parts determined during the grid slope.
In addition, comparatively ideal is that in display controller of the present invention, the kind of above-mentioned display device is to be arranged at the size condition of the panel in the above-mentioned display device or the resolution condition of above-mentioned display device at least.
In addition, comparatively ideal is that in display-apparatus control method of the present invention, the kind of above-mentioned display device is to be arranged at the size condition of the panel in the above-mentioned display device or the resolution condition of above-mentioned display device at least.
In addition, comparatively ideal is that display device of the present invention has the control assembly of being controlled by above-mentioned any display controller.
In addition, comparatively ideally be that display system of the present invention constitutes by above-mentioned any display controller with by the display device of this display controller control.
Other purpose of the present invention, characteristic and advantage can be well understood to from the content shown in following.In addition, advantage of the present invention also can be clear and definite from the following explanation of carrying out with reference to accompanying drawing.
Description of drawings
Fig. 1 is the block diagram of the display system in the expression embodiment 1.
Fig. 2 is the circuit diagram of the inner structure of the scan signal line drive circuit in the expression embodiment 1.
Fig. 3 representes embodiment 1, is that the expression refresh rate is the sequential chart of Dot Clock signal, horizontal-drive signal (Hsync), GOE signal, VG (j), VG (j+1) and VG (j+2) under the situation of 60Hz.
Fig. 4 representes embodiment 1, is that the expression refresh rate is the sequential chart of Dot Clock signal, horizontal-drive signal (Hsync), GOE signal, VG (j), VG (j+1) and VG (j+2) under the situation of 40Hz.
Fig. 5 representes embodiment 1, is the form that (pixel stablize write during) compares during expression is Dot Clock signal frequency, clock count value, horizontal-drive signal cycle, GOE signal _ high level width and the TGON under the situation of situation and 40Hz of 60Hz to refresh rate.
Fig. 6 representes embodiment 1, be register with TGON during (pixel is stable write during) corresponding form.
Fig. 7 representes the comparative example of embodiment 1, is that the expression refresh rate is the sequential chart of Dot Clock signal, horizontal-drive signal (Hsync), GOE signal, VG (j), VG (j+1) and VG (j+2) under the situation of 60Hz.
Fig. 8 representes the comparative example of embodiment 1, is that the expression refresh rate is the sequential chart of Dot Clock signal, horizontal-drive signal (Hsync), GOE signal, VG (j), VG (j+1) and VG (j+2) under the situation of 40Hz.
Fig. 9 representes the comparative example of embodiment 1, is the form that (pixel stablize write during) compares during expression is Dot Clock signal frequency, clock count value, horizontal-drive signal cycle, GOE signal _ high level width and the TGON under the situation of situation and 40Hz of 60Hz to refresh rate.
Figure 10 is the circuit diagram of the inner structure of the scan signal line drive circuit in the expression embodiment 2.
Figure 11 is the circuit diagram of the inner structure of the VD1 generative circuit among expression Figure 10.
Figure 12 is the block diagram of the display system in the expression embodiment 2.
Figure 13 representes embodiment 2, is that the expression refresh rate is the sequential chart of Dot Clock signal, horizontal-drive signal (Hsync), GS signal, VD1, VG (j), VG (j+1) and VG (j+2) under the situation of 60Hz.
Figure 14 representes embodiment 2, is that the expression refresh rate is the sequential chart of Dot Clock signal, horizontal-drive signal (Hsync), GS signal, VD1, VG (j), VG (j+1) and VG (j+2) under the situation of 40Hz.
Figure 15 representes embodiment 2, is that expression is between the high period of Dot Clock signal frequency, clock count value, Hsync cycle, grid ramp signal under the situation of situation and 40Hz of 60Hz (between the GS_ high period to refresh rate; During pixel writes) and the low period of grid ramp signal between (GOE_ low level width; During the grid slope) form that compares.
Figure 16 representes embodiment 2, is between register and grid ramp signal low period (during the GSL; During the grid slope) corresponding form.
Figure 17 is the block diagram of the display controller of expression embodiment 3.
Figure 18 representes figure shown in Figure 17 or the GOE signal generating circuit structure that door constitutes.
Figure 19 is the circuit diagram of inner structure of the scan signal line drive circuit of expression embodiment 3.
Figure 20 representes embodiment 3, is that the expression refresh rate is the sequential chart of Dot Clock signal, horizontal-drive signal (Hsync), G_ON signal, GS ' signal, GOE signal, VD1, VG (j), VG (j+1) and VG (j+2) under the situation of 60Hz.
Figure 21 representes embodiment 3, is that the expression refresh rate is the sequential chart of Dot Clock signal, horizontal-drive signal (Hsync), G_ON signal, GS ' signal, GOE signal, VD1, VG (j), VG (j+1) and VG (j+2) under the situation of 40Hz.
Figure 22 representes embodiment 3, is that expression is the form that Dot Clock signal frequency, clock count value, horizontal-drive signal (Hsync), G_ON signal _ high level width (pixel write during), GS ' signal _ high level width (during the grid slope) and GOE signal _ low level width (grid off period) under the situation of situation and 40Hz of 60Hz compare to refresh rate.
Figure 23 is the circuit diagram of inner structure of the VD1 generative circuit of expression embodiment 3.
Figure 24 is the key diagram of the structure of the existing liquid crystal indicator of expression.
Figure 25 is the key diagram of the structure example of the existing scan signal line drive circuit of expression.
Figure 26 is the circuit diagram of the inner structure of the existing VD1 generative circuit of expression.
Figure 27 is the oscillogram of the major part of expression Figure 26.
Figure 28 representes prior art, is that the expression refresh rate is the sequential chart of Dot Clock signal, horizontal-drive signal (Hsync), GS signal, VD1, VG (j), VG (j+1) and VG (j+2) under the situation of 60Hz.
Figure 29 representes prior art, is that the expression refresh rate is the sequential chart of Dot Clock signal, horizontal-drive signal (Hsync), GS signal, VD1, VG (j), VG (j+1) and VG (j+2) under the situation of 40Hz.
Figure 30 representes prior art, is that expression is between the high period of Dot Clock signal frequency, clock count value, Hsync cycle, grid ramp signal under the situation of situation and 40Hz of 60Hz (between the GS_ high period to refresh rate; During pixel writes) and the low period of grid ramp signal between (GOE_ low level width; During the grid slope) form that compares.
Label declaration
1 display device (liquid crystal indicator)
2 figure LSI (display controller)
3 control circuits (control assembly)
4 scan signal line drive circuits
8 TFT (on-off element)
Decision-making circuit during the 33 first grid slopes
53 second pixels are stable write during decision-making circuit
Decision-making circuit during the 54 second grid slopes
70 first pixels are stable write during decision-making circuit
S (1) ..., S (N) source bus line (video signal cable)
G (1) ..., G (M) grid bus (scan signal line)
The Hsync horizontal-drive signal
Embodiment
Embodiment 1 is (about " A; Pixel is stable write during " fixing embodiment)
Utilize description of drawings an embodiment of the invention below.
The display system of this embodiment is as shown in Figure 1, by liquid crystal indicator (display device; LCD:Liquid crystal display) 1 and the figure LSI (display controller) 2 that is disposed at this display device 1 prime constitute.
(about display device)
Display device 1 possesses: logic controller (control circuit; Control assembly) 3; Scan signal line drive circuit (gate drivers) 4, data signal wire driving circuit (source electrode driver) 5 and display part 6.
On display part 6; Many source bus line (video signal cable) S (1) that are connected with the data signal wire driving circuit of incoming video signal ..., S (N) and be connected in scan signal line drive circuit many grid buss (scan signal line) G (1) ..., G (M) is configured to the ranks shape each other, each intersection point of these buses is provided with the on-off element that the TFT8 that is connected with pixel electrode 7 etc. constitutes.The voltage VghVgl voltage that applies on the grid bus that TFT8 is utilized in this TFT8 is connected carries out switch control.
Control circuit 3 has the effect as the control part of display device 1, from figure LSI2 acceptance point CK (Dot Clock signal), horizontal-drive signal (Hsync) and GOE signal (about the detailed content of GOE signal, said below) etc.Control circuit 3 generates various control signals according to the some CK, horizontal-drive signal and the GOE signal that receive from figure LSI2, and outputs to gate drivers 4 and source electrode driver 5.As from the signal of control circuit 3, grid ramp signal, grid initial pulse (GSP), gate clock pulse (GCK) and latch signal etc. are arranged to gate drivers 4 transmissions.
Gate drivers 4 is as shown in Figure 2, possesses: by M bistable multivibrator (F1 of series connection ..., FM) the 10 shift LD portions 11 that constitute; Input comes from the output of each bistable multivibrator 10 and a plurality of and door 60 of GOE signal; According to from each a plurality of SS 12 of switching of output of door 60; Generation is input to the VD1 generative circuit 72 of input signal of an input terminal of SS 12; And the VD2 generative circuit 21 that generates the input signal of another input terminal that is input to SS 12.The public terminal of on-off element 12 with corresponding to the grid bus G (1) of this SS 12 ..., G (M) connects.
It is the grid off voltage Vgl of off-state that 21 generations of VD2 generative circuit are enough to make the TFT8 that is arranged at display part 6.
It is the gate turn-on voltage Vgh of on-state that 72 generations of VD1 generative circuit are enough to make the TFT8 that is arranged at display part 6.
Describe down in the face of structure and GOE signal as the figure LSI2 of most important parts of the present invention.
Figure LSI2 is as shown in Figure 1, possesses: Dot Clock signal control part 30; Dot Clock signal generating circuit 31; Horizontal-drive signal generation circuit 32; And first pixel is stable write during decision-making circuit 70.
And horizontal-drive signal generation circuit 32 inside possess the clock counter 34 that the Dot Clock signal is counted, on the other hand, first pixel is stable write during decision-making circuit 70 inside possess timing circuit 71.
Dot Clock signal control part 30 according to the expectation refresh rate (frame frequency) commit point clock signal, and will corresponding to this Dot Clock signal command signal be transferred to Dot Clock signal generating circuit 31.
The instruction that Dot Clock signal generating circuit 31 is accepted from Dot Clock signal control part 30 generates the Dot Clock signal.That is to say that the Dot Clock signal in this embodiment changes corresponding to refresh rate.Therefore, for example when wanting to realize low power consumption, can use the low refresh rate of 40Hz, and on the other hand, in other cases, can use the for example common refresh rate of 60Hz.And Dot Clock signal generating circuit 31 also sends to the Dot Clock signal that generates the control circuit 3 and the inner horizontal-drive signal generation circuit 32 of figure LSI2 of display device 1 one sides.
Horizontal-drive signal generation circuit 32 utilizes the Dot Clock signal of 34 pairs of stipulated numbers of clock counter to count from Dot Clock signal generating circuit 31 acceptance point clock signals, and generates horizontal-drive signal.And horizontal-drive signal generation circuit 32 also sends to decision-making circuit 70 during inner stable the writing of first pixel of control circuit 3 and the figure LSI2 of display device 1 one sides with the horizontal-drive signal that generates.
First pixel is stable write during decision-making circuit 70 as stated, inside has timing circuit 71, utilize this timing circuit 71 decision pixels be stable write during (GOE signal _ high level width), and generate the GOE signal.The reference clock that these timing circuit 71 bases are different with above-mentioned Dot Clock signal carries out the time instrumentation.Here, so-called pixel is stable to be meant in a scan period during writing, gate drivers 4 outputs be enough to make grid bus (scan signal line) G (1) ..., the scanning of connecting of the TFT8 on the G (M) voltage (high level) during.
And, also to first pixel is stable write during decision-making circuit 70 input level synchronizing signals, this horizontal-drive signal becomes the reset signal of GOE signal.Thereby the cycle of GOE signal is the identical cycle with the cycle of horizontal-drive signal.
Yet, be to utilize the Dot Clock signal in the past, promptly the Dot Clock signal is counted (GOE signal _ high level width) and grid off period (GOE signal _ low level width) during setting that pixel is stable and writing.Therefore, under the situation that refresh rate changes, the Dot Clock signal changes, thus pixel is stable write during (GOE signal _ high level width) and grid off period (GOE signal _ low level width) also change thereupon.
And first pixel of this embodiment is stable write during in the decision-making circuit 70, with pixel is stable write during (GOE signal _ high level width) fixing, its variation with refresh rate is had nothing to do.To concrete grammar that realize this point be described below.
First pixel is stable write during decision-making circuit 70 with horizontal-drive signal as reset signal (as triggering), during utilizing that timing circuit 71 instrumentation pixels are stable and writing (GOE signal _ high level width).That is to say, in the input level synchronizing signal, timing circuit 71 beginning instrumentations.Then, in a single day instrumentation finishes, and just making the GOE signal is low level.In case the GOE signal is a low level, just making TFT8 is the hard closing state.As a result, during can making that pixel is stable and writing (GOE signal _ high level width) for certain, and irrelevant with the variation of refresh rate.
For example, Fig. 3 is the sequential chart of Dot Clock signal, horizontal-drive signal (Hsync), GOE signal, VG (j), VG (j+1) and VG (j+2) under the situation of expression 60Hz refresh rate.On the other hand, Fig. 4 is the sequential chart of Dot Clock signal, horizontal-drive signal (Hsync), GOE signal, VG (j), VG (j+1) and VG (j+2) under the expression 40Hz situation.Even become from the refresh rate of 60Hz shown in Figure 3 under the situation of refresh rate of 40Hz shown in Figure 4; Also can be arranged at that first pixel is stable and write during the different reference clock signal of Dot Clock signal in the timing circuit 71 of decision-making circuit 70; Rather than the Dot Clock signal in this embodiment, during coming that the instrumentation pixel is stable and writing (GOE signal _ high level width).
More particularly, even refresh rate is being become from 60Hz under the situation of 40Hz, during not changing also that pixel is stable and writing (GOE signal _ high level width).Be to be 16.9 microseconds under the situation of 60Hz during this period at refresh rate.As shown in Figure 4, horizontal-drive signal one input just utilizes timing circuit 71 beginning instrumentations.Then, one through 16.9 microseconds, and the GOE signal just becomes low level from high level.When importing next horizontal-drive signal again, the GOE signal is become high level from low level once more, repeat aforesaid operations thereafter.During can making like this that pixel is stable and writing (GOE signal _ high level width) for certain, and during making that pixel is stable and writing for certain, and irrelevant with refresh rate.
In addition, Fig. 5 is the form that (pixel stablize write during) compares during expression is Dot Clock signal frequency, clock count value, horizontal-drive signal cycle, GOE signal _ high level width and the TGON under the situation of situation and 40Hz of 60Hz to refresh rate.Especially, if during being conceived to TGON (pixel is stable write during), then can know no matter be at 60Hz or 40Hz, under the situation of arbitrary refresh rate, can make TGON during (pixel is stable write during) for certain.
And be not limited to said structure, and also can be according to panel size or resolution, promptly according to the kind of display device, during setting at random that pixel is stable and writing (GOE signal _ high level width).Describe in the face of this structure down.
Here, as an example, be that example describes with different types of display device A display device B each other.
Through set-up register again on the basis of said structure, first pixel is stable write during decision-making circuit 70 can determine that pixel is stable and write during (GOE signal _ high level width).
Here, in order to help to understand, utilize register shown in Figure 6 and TGON during (pixel stablize write during) corresponding form describe.
In this table with corresponding expression during register and the TGON.That is, as shown in Figure 6, for register (0,0), 10 microseconds during the distribution T GON, for 15 microseconds during register (0,1) the distribution T GON, for 20 microseconds during register (1,0) the distribution T GON, for register (1,1), 25 microseconds during the distribution T GON.
Then, from first pixel of display device 1 one side direction figure LSI2 is stable write during the corresponding signal of kind of decision-making circuit 70 inputs and display device.For convenience's sake, this signal is called the register setting signal here.This register signal setting signal is the signal of set-up register, utilizes the setting of this register, during can determining that pixel is stable and writing (GOE signal _ high level width).For example, as shown in Figure 6, under the situation of display device A; Utilize the register setting signal, mask register (0,0); Pixel is stable write during (GOE signal _ high level width) be 10 microseconds, under the situation of display device B, utilize the register setting signal; Mask register (1,0), pixel is stable write during (GOE signal _ high level width) be 15 microseconds.Like this can be according to the kind of display device, during setting that pixel is stable and writing (GOE signal _ high level width).If during can determining like this that pixel is stable and writing (GOE signal _ high level width), then utilize with above said identical method, can with the change of refresh rate irrespectively fixed pixel stablize write during (GOE signal _ high level width).In addition, above-mentioned register setting signal can be synchronous with the command signal of exporting from Dot Clock signal control part 30, also can be asynchronous.
The said reference signal is preferably used the timer clock signal.In addition, the benchmark CLK that reference signal can using system CPU etc. controls, rather than uses the Dot Clock signal that shows usefulness.
In addition, be not limited to said structure, under the situation that frame frequency (refresh rate) changes, also can be and the count value of set point clock signal initiatively according to the variation of this frame frequency, during writing so that fixed pixel is stable or set the value that it is a regulation.That is to say, under the situation that the Dot Clock signal frequency of demonstration usefulness also changes when frame frequency changes, can control through the count value that changes CLK.
(comparative example of embodiment 1)
Comparative example in the face of above-mentioned embodiment describes down.
Fig. 7 is the sequential chart of Fig. 3 comparative example of this embodiment of expression, and Fig. 8 is the sequential chart of Fig. 4 comparative example of this embodiment of expression.As shown in Figure 7, in comparative example, utilize the count value of Dot Clock signal to come during the instrumentation TGON.Here, as shown in Figure 7, be 811 clock signals (CK).And, become from 60Hz under the situation of 40Hz at refresh rate, making equally during the TGON is 811 clock signals (CK).
Therefore, be under the situation of 60Hz at refresh rate, as shown in Figure 7, be 16.9 microseconds during the TGON, and be under the situation of 40Hz at refresh rate, as shown in Figure 8, during the TGON 25.3 microseconds.Promptly, also of all kinds during the TGON because of the difference of refresh rate, there is the uncontrollable also fixing problem during the TGON.
In addition, Fig. 9 is the form of comparative example of Fig. 5 of this embodiment of expression.Shown in this table, in comparative example, to counting according to clock number during the TGON, so there is the problem that changes corresponding to refresh rate.
Embodiment 2 is (about " B; During the grid slope " fixing embodiment)
Utilize accompanying drawing that another embodiment of the present invention is described below.In this embodiment, the difference with above-mentioned embodiment 1 is described, therefore, for the ease of explanation, to have with embodiment 1 in the member of illustrated member identical function, adopt same numbering, and omit its explanation.In the above-described embodiment, control during writing pixel is stable.And in this embodiment, to during the grid slope is set, the mode that can control simultaneously during this grid slope describes.
Here, be meant during the so-called grid slope voltage level tilt to descend (or ladder property ground descends) during.
The source electrode driver 4 of this embodiment is shown in figure 10, possesses: by M bistable multivibrator (F1 of series connection ..., FM) the 10 shift LD portions 11 that constitute; According to a plurality of SSes 12 that switch from the output separately of each bistable multivibrator 10; Generation is input to the VD1 generative circuit 20 of input signal of an input terminal of SS 12; And the VD2 generative circuit 21 that generates the input signal of another input terminal that is input to SS 12.The public terminal of SS 12 with corresponding to the grid bus G (1) of this SS 12 ..., G (M) connects.That is to say, different with embodiment 1, be not provided with and door 60.
In addition, the VD1 generative circuit 20 of this embodiment is shown in figure 11, by resistance R cnt that carries out charging and discharging and capacitor Ccnt, the switch SW 1 and the switch SW 2 that are used for controlling the inverter INV of this charging and discharging and are used for switching charging and discharging constitute.
An input terminal to switch SW1 applies signal voltage Vdd.This signal voltage Vdd has to be enough to make above-mentioned TFT8 to become the DC voltage of Vgh voltage of the level of on-state.Another terminal of this switch SW 1 is connected with the end of resistance R cnt, and also is connected with the end of capacitor Ccnt.The other end of resistance R cnt is through switch SW 2 ground connection.The switch control of this switch SW 2 is carried out according to the grid ramp signal via inverter INV input.
The grid ramp signal is described in the literary composition of back, and is synchronous with horizontal-drive signal, carries out the switch control of switch SW 1, carries out the switch control of switch SW 2 simultaneously through inverter INV.
Specifically, be that switch SW 1 is an on-state under the situation of high level (pixel write during) at the grid ramp signal, for this switch SW 2, INV applies low level via inverter, so switch SW 2 is an off-state.Therefore, Vgh voltage is applied to as the VD1 signal on the input terminal of switch SW, and Vgh voltage also is accumulated among the capacitor Ccnt simultaneously.
On the contrary, be under the situation on low level (during the grid slope) at the grid ramp signal, switch SW 1 is an off-state, at this moment, for switch SW 2, INV applies high level via inverter, so switch SW 2 is an on-state.Therefore, the electric charge that is held among the capacitor Ccnt is through resistance R cnt discharge, and voltage level descends from Vgh voltage gradually.With voltage level descend so gradually during be called the grid slope during.Thereby, as the VD1 signal of the input signal of a terminal that is input to SS 12 (signal that generates by the VD1 generative circuit), for like the civilian described Figure 13 in back, the sawtooth wave shown in 14.
Then, also the same in this embodiment with embodiment 1, structure and grid ramp signal as the figure LSI2 of most important part of the present invention are described.
Figure LSI2 is shown in figure 12, possesses decision-making circuit 33 during Dot Clock signal control part 30, Dot Clock signal generating circuit 31, horizontal-drive signal generation circuit 32 and the first grid slope.
And horizontal-drive signal generation circuit 32 inside possess the clock counter 34 that the Dot Clock signal is counted, and on the other hand, decision-making circuit 33 inside possess timing circuit 35 during the first grid slope.
Dot Clock signal control part 30 and will be transferred to Dot Clock signal generating circuit 31 corresponding to the command signal of this Dot Clock signal according to refresh rate (frame frequency) the commit point clock signal of expectation.
The instruction that Dot Clock signal generating circuit 31 is accepted from Dot Clock signal control part 30 generates the Dot Clock signal.That is to say that the Dot Clock signal in this embodiment changes according to refresh rate.Therefore, for example when wanting to realize low power consumption, can use the low refresh rate of 40Hz, and on the other hand, in other cases, can use the for example common refresh rate of 60Hz.And Dot Clock signal generating circuit 31 also sends to the Dot Clock signal that generates the control circuit 3 and the inner horizontal-drive signal generation circuit 32 of figure LSI2 of display device 1 one sides.
Horizontal-drive signal generation circuit 32 utilizes the Dot Clock signal of 34 pairs of stipulated numbers of clock counter to count from Dot Clock signal generating circuit 31 acceptance point clock signals, and generates horizontal-drive signal.And horizontal-drive signal generation circuit 32 also sends to decision-making circuit 33 during the inner first grid slope of control circuit 3 and the figure LSI2 of display device 1 one sides with the horizontal-drive signal that generates.
Decision-making circuit 33 during the first grid slope, and inside has timing circuit 35 as stated, utilize (GS signal _ low level width) during this timing circuit 35 decision grid slopes, and generate the grid ramp signal.The reference clock that these timing circuit 35 bases are different with above-mentioned Dot Clock signal carries out the time instrumentation.
And, decision-making circuit 33 input level synchronizing signals during the first grid slope also, this horizontal-drive signal becomes the reset signal of grid ramp signal.Thereby the cycle of grid ramp signal is the identical cycle with the cycle of horizontal-drive signal.
Yet, be in the past through utilize the Dot Clock signal, promptly the Dot Clock signal counted, set pixel write during during (GS signal _ high level width) and the grid slope (GS signal _ low level width).Therefore, changing under the situation of refresh rate, the Dot Clock signal changes, thus pixel write during during (GS signal _ high level width) and the grid slope (GS signal _ low level width) also change thereupon.
And during the first grid slope of this embodiment in the decision-making circuit 33, fixedly (GS signal _ low level width) during the grid slope, and irrelevant with the variation of refresh rate.Describe in the face of the concrete grammar of realizing this point down.
Decision-making circuit 33 is accepted horizontal-drive signal from horizontal-drive signal generation circuit 32 during the first grid slope, so can obtain the cycle (being exactly the one-period of horizontal-drive signal from the next input of being input to of horizontal-drive signal promptly) of a horizontal-drive signal.Thereby, through from the cycle (1H) of this horizontal-drive signal, deduct (GS signal _ low level width) during (being predetermined) grid slope of predetermined fixed, during just can obtaining pixel and writing (GS signal _ high level width).During if known pixels writes (GS signal _ high level width); Then with horizontal-drive signal as reset signal (as trigger); (GS signal _ high level width) carries out instrumentation and (that is to say during utilizing 35 pairs of these pixels of timing circuit to write; In the input level synchronizing signal, timer just begins instrumentation).Can generate the grid ramp signal of having fixed (GS signal _ low level width) during the grid slope with this.As a result, can make during the grid slope (GS signal _ low level width) for certain, and irrelevant with the variation of refresh rate.
For example, Figure 13 is the sequential chart of Dot Clock signal, horizontal-drive signal (Hsync), GS signal, VD1, VG (j), VG (j+1) and VG (j+2) under the situation of expression 60Hz refresh rate.On the other hand, Figure 14 is the sequential chart of Dot Clock signal, horizontal-drive signal (Hsync), GS signal, VD1, VG (j), VG (j+1) and VG (j+2) under the expression 40Hz situation.Even become from the refresh rate of 60Hz shown in Figure 13 under the situation of refresh rate of 40Hz shown in Figure 14; In this embodiment; Neither use the Dot Clock signal; And use be arranged at the first grid slope during the different reference clock of Dot Clock signal in the timing circuit 35 of decision-making circuit 33, come (GS signal _ low level width) during the instrumentation grid slope.
More particularly, be that refresh rate is being become from 60Hz under the situation of 40Hz, to carrying out instrumentation during the one-period of the horizontal-drive signal of after changing refresh rate (being 40Hz) here.Shown in figure 14, be 40.3 microseconds during this period.Then, from deducting during this period (GS signal _ low level width during the fixing grid slope that is predetermined; 10 microseconds), the result is 30.3 microseconds.
Shown in figure 14, horizontal-drive signal is input in a single day, and timing circuit 35 just begins instrumentation, makes the grid ramp signal become high level from low level simultaneously.Then, through 30.3 microseconds, make the grid ramp signal become low level from high level.When importing next horizontal-drive signal again, then make the grid ramp signal become high level from low level once more, then repeat aforesaid operations afterwards.Can make with this that (GS signal _ low level width) serves as certain during grid slope, and irrelevant with refresh rate.
In addition, Figure 15 is that expression is the form that Dot Clock signal frequency, clock count value, horizontal-drive signal cycle (Hsync cycle), GS signal _ high level width (pixel write during) and GS signal _ low level width (during the grid slope) under the situation of situation and 40Hz of 60Hz compare to refresh rate.If especially be conceived to grid slope width, can know no matter be under the 60Hz or the situation of arbitrary refresh rate of 40Hz, can make the grid slope during (GS signal _ low level width) certain.
And be not limited to said structure, and also can be according to panel size or resolution, promptly set (GS signal _ low level width) during the grid slope arbitrarily according to the kind of display device.Describe in the face of this structure down.
Here, as an example, be that example describes with the mutually different display device A display device of kind B.
Through set-up register again on the basis of said structure, decision-making circuit 33 can determine (GS signal _ low level width) during the grid slope during the first grid slope.Here, in order to help to understand, utilize register shown in Figure 16 and grid slope during (GS signal _ low level width) corresponding form describe.
This form is with register and the corresponding expression of GS signal _ low level width (during the grid slope).Promptly shown in figure 16, for (GS signal _ low level width) 5 microseconds during register (0,0) the distribution grid slope; For register (0; 1) (GS signal _ low level width) 10 microseconds during the distribution grid slope are for (GS signal _ low level width) 15 microseconds during register (1,0) the distribution grid slope; For (GS signal _ low level width) 20 microseconds during register (1,1) the distribution grid slope.
Then, decision-making circuit 33 during the first grid slope of figure LSI2 is from the display device 1 one sides input signal corresponding with the kind of display device.For convenience's sake, this signal is called the register setting signal here.This register signal setting signal is the signal of set-up register, through the setting of this register, can determine (GS signal _ low level width) during the grid slope.For example, shown in figure 16, under the situation of display device A; Utilize the register setting signal, mask register (0,0); (GS signal _ low level width) is 5 microseconds during the grid slope, under the situation of display device B, utilizes the register setting signal; Mask register (1,0), (GS signal _ low level width) is 15 microseconds during the grid slope.Like this can be according to during the kind setting grid slope of display device (GS signal _ low level width).If can determine like this (GS signal _ low level width) during the grid slope, just can utilize the method identical, with the change of refresh rate irrespectively fixedly (GS signal _ low level width) during the grid slope with said method.
In addition, the effect during the grid slope in the past is flicker and Δ V in the reduction face, so utilizing the grid slope to come under the state of flicker and Δ V in the reduction face, to the bias voltage enforcement optimization (adjustment) of opposite electrode.Therefore, if change during the grid slope, then the reduction amount of flicker and Δ V changes in the face, thereby departs from optimization (adjustment) state, flicker in the generation face.On the contrary, of this embodiment, with fixing during the grid slope, can stationary plane in the reduction amount of flicker and Δ V, even refresh rate changes, also can prevent the generation of glimmering in the face.
Embodiment 3 is (about " C; Pixel is stable write during with the grid slope during fixing " embodiment)
Utilize accompanying drawing that another embodiment of the present invention is described below.In this embodiment, for the difference with above-mentioned embodiment 1,2 is described, for the ease of explanation, to have with embodiment 1,2 in the member of illustrated member identical function, adopt same numbering, and omit its explanation.
In the above-described embodiment, only control during the grid slope with pixel is stable write during in arbitrary side.Yet, if adopt this embodiment, can to during the grid slope and pixel is stable write during both sides control.
In this embodiment, be the structure of VD1 generative circuit with the difference of above-mentioned embodiment.The VD1 generative circuit of being put down in writing in this embodiment 20 '; Shown in figure 23; Be different from the grid ramp signal (GS ' signal) of embodiment 1 from outside input, and between the input end of grid ramp signal (GS ' signal) and switch SW 1, inverter INV be set.Like this, in embodiment 1, during grid ramp signal (GS signal) during for low level is the grid slope, and in this embodiment, during grid ramp signal (GS ' signal) during for high level is the grid slope.
The figure LSI2 of this embodiment; Shown in figure 17, possess: Dot Clock signal control part 50, Dot Clock signal generating circuit 51, horizontal-drive signal generation circuit 52, second pixel are stable write during decision-making circuit (grid determines parts during the slope) 54 and or door 55 during the decision-making circuit (pixel is stable write during determine parts) 53, second grid slope.In addition, the same with above-mentioned embodiment 1, horizontal-drive signal generation circuit 52 has clock counter (with reference to Fig. 1).Also have, decision-making circuit 54 has the timing circuit (not shown) that carries out the time instrumentation according to second reference clock that is different from the Dot Clock signal during the second grid slope.
Second pixel is stable write during decision-making circuit 53 have the timing circuit (not shown) that carries out the time instrumentation according to first reference clock that is different from the Dot Clock signal.And, to second pixel is stable write during decision-making circuit 53 input level synchronizing signals.
Second pixel is stable write during decision-making circuit 53 with the input of this horizontal-drive signal as triggering (utilizing the input of horizontal-drive signal to reset), utilize first reference clock to begin instrumentation, the pixel that is predetermined was write between stationary phase measures.Second pixel is stable write during decision-making circuit 53 in the input level synchronizing signal, become high level from low level, become high level during being predetermined, then, be low level G_on signal before being created on the next horizontal-drive signal of input.That is, the G_on signal be the pixel that is predetermined is stable write during in become the signal of high level.
As stated, decision-making circuit 54 has the timing circuit (not shown) that carries out the time instrumentation according to second reference clock that is different from the Dot Clock signal during the second grid slope.And, to the above-mentioned G_on signal of 54 inputs of decision-making circuit during the second grid slope.Decision-making circuit 54 becomes the low level while at this G_on signal from high level during the second grid slope, begin to carry out instrumentation with second reference clock, and during the grid slope that is predetermined of instrumentation (GS ' signal _ high level width).Decision-making circuit 54 is when the G_on signal descends during the second grid slope; Become high level from low level; Become the high level on (during the grid slope) during being predetermined, then, be created on before the negative edge of next G_on signal and be low level grid ramp signal (GS ' signal).That is to say, grid ramp signal (GS ' signal) be terminal during stable writing with pixel as the grid slope that is predetermined at top during in become the signal of high level.
And or door is 55 shown in figure 18, has the effect as the GOE signal generating circuit, and input G_on signal and grid ramp signal (GS ' signal) are with output signal (the GOE signal of this or door 55; The output inhibit signal) exports to display device 1 one sides.That is to say that the GOE signal is that at least one signal in G_on signal or grid ramp signal (GS ' signal) becomes high level during for high level, become low level signal during for low level G_on signal or grid ramp signal (GS ' signal) both sides.
The gate drivers of this embodiment, shown in figure 19 on the basis of said structure, also have the input terminal of GOE signal.And, in scan signal line drive circuit 4, also have with from the output signal of each bistable multivibrator 10 and the input of GOE signal with door 60, should with output control SS 12 of door 60.
Thereby, when the GOE signal is low level, by the strong hand SS is connected with the VD2 generative circuit, gate drivers is applied to be enough to make TFT8 be the grid off voltage Vgl of off-state.That is to say, at G_on signal and grid ramp signal (GS ' signal) when both sides are low level, the state of TFT8 for forcing to break off.
Utilize Figure 20,21 to explain that the refresh rate when using this embodiment is the situation of 60Hz and the refresh rate sequential chart as the Dot Clock signal of the situation of 40Hz, horizontal-drive signal (Hsync), grid ramp signal (GS ' signal), GOE signal, VD1, VG (j), VG (j+1) and VG (j+2) below.Figure 20 representes that refresh rate is the situation of 60Hz, and Figure 21 representes that refresh rate is the situation of 40Hz.
Shown in figure 20, at moment t1, to second pixel is stable write during decision-making circuit 53 input level synchronizing signals, the G_on signal becomes high level from low level simultaneously.When the G_on signal becomes high level; Second pixel is stable write during decision-making circuit 53 utilize first reference clock to begin instrumentation; After (being 16.9 microseconds) during stable the writing of pixel that is predetermined,, make the G_on signal become low level here from high level at moment t2.Then, at the moment t4 of horizontal-drive signal input, second pixel is stable write during decision-making circuit 53 make the G_on signal become high level from low level, repeat same action afterwards.
Decision-making circuit 54 is accepted the G_on signal during the second grid slope, becomes low level moment t2 at the G_on signal from high level, generates the grid ramp signal that becomes high level from low level.Decision-making circuit 54 is at grid ramp signal (GS ' signal) (t2 constantly) when low level becomes high level during the second grid slope; Utilize second reference clock to begin instrumentation; After (being microsecond here) during the grid slope that is predetermined; At moment t3, and the grid ramp signal (GS ' signal) become low level from high level.Then, become low level moment t5 at the G_on signal from high level, grid ramp signal decision-making circuit 54 makes grid ramp signal (GS ' signal) become high level from low level, repeats same action afterwards.
In addition, in the horizontal period, all be low level moment t3～moment t4 at G_on signal and grid ramp signal (GS ' signal), the GOE signal is a low level, is high level during other.
Thereby; VG (j) becomes pixel and writes (G_ON signal _ high level width) between stationary phase between moment t1～moment t2; During becoming the grid slope between moment t2～moment t3 (GS ' signal _ high level width), between moment t3～moment t4, become the grid off period, afterwards; VG (j+1) and VG (j+2) horizontal period that also staggers one by one repeats identical action.
In addition; If employing said method; Shown in figure 21, even be under the situation of 40Hz, though as during moment t3 '～moment t4 ' of grid off period making refresh rate; With different during moment t3～moment t4, but during can making also that pixel is stable and writing during (t1～moment t2, t 1 '～moment t2 ') constantly constantly and the grid slope (t2～t3, t2 '～t3 ') be necessarily.
Promptly like Figure 20, shown in 21; At refresh rate is that 60Hz and refresh rate are under the situation of 40Hz; Though the cycle of Dot Clock signal frequency, horizontal-drive signal (Hsync), grid off period (GOE signal _ low level width) are inequality; But in addition, can make especially that pixel is stable and write during and during the grid slope for certain.
In addition; Figure 22 is in this embodiment of expression, is that Dot Clock signal frequency, clock count value, Hsync cycle, pixel under the situation of situation and 40Hz of 60Hz stablized the form that (GS ' signal _ high level width) and grid off period (GOE signal _ low level width) compare during (G_ON signal _ high level width), the grid slope during writing to refresh rate.As shown in the drawing, under the situation of 60Hz and the arbitrary refresh rate of 40Hz, can make the grid slope during (GS ' signal _ high level width) and pixel is stable write during (G_ON signal _ high level width) for certain.
And the VD1 generative circuit is shown in figure 23 in this embodiment, is on the basis of the structure shown in the embodiment 2, also between the input end of GS ' signal and switch SW 1, is provided with INV (inverter).Like this, in this embodiment, be different from embodiment 2, during GS ' signal high level width is the grid slope.
In addition, be meant between the off period of so-called on-off element scanning that scan signal line drive circuit output is enough to make the pixel switch on the sweep trace to break off stop voltage (cut-off level) during.
In addition; In this embodiment; During writing by pixel is stable, during the grid slope and on-off element between the off period (grid off period) form a horizontal scan period; But, during also can writing by pixel for example is stable and on-off element between the off period (grid off period) form.In addition, in the present invention, the signal (directly being called the GOE signal) of action that is used for stopping above-mentioned on-off element is by G_ON signal, GS signal, become with the pupil, through be provided with at gate drivers etc. should and door, also can become the GOE signal at gate drivers one adnation.
In addition, in this embodiment, also can be the same with embodiment 1,2, through set-up register, during setting at random that pixel is stable and writing and during the grid slope.
Also have, in this embodiment, be, and generate the GOE signal, but also can generate the GOE signal by LCD1 at LCD (display device) 1 one side settings or door 55 by figure LSI2 at figure LSI2 one side setting or door 55.
In addition, above-mentioned first reference clock can be identical with second reference clock, also can be different.
In addition; The present invention is not limited to above-mentioned various embodiment; In the scope shown in the claim, all changes can be arranged, on the basis of different embodiment, make up disclosed technical method respectively and the embodiment that obtains, be also included within the technical scope of the present invention.
As stated; Display controller of the present invention is controlled the display device with a plurality of pixels, video signal cable, scan signal line and scan signal line drive circuit, wherein; The said pixel of said vision signal alignment provides data-signal; Said scan signal line and said video signal cable are arranged in a crossed manner, said scan signal line drive circuit to said scan signal line output scanning signal to drive said scan signal line
In a horizontal period of above-mentioned display device, have be stable the writing of pixel of high level from the voltage level of said scanning signals line drive circuit output during,
Have and use and the irrelevant reference signal of the frame frequency of above-mentioned display device, determine that above-mentioned voltage level is to determine parts during stable the writing of pixel during stable the writing of pixel of high level.
In addition, as stated, display-apparatus control method of the present invention; Display device to having a plurality of pixels, video signal cable, scan signal line and scan signal line drive circuit is controlled; Wherein, the said pixel of said vision signal alignment provides data-signal, and said scan signal line and said video signal cable are arranged in a crossed manner; Said scan signal line drive circuit to said scan signal line output scanning signal to drive said scan signal line
In a horizontal period of above-mentioned display device, have be stable the writing of pixel of high level from the voltage level of said scanning signals line drive circuit output during,
Use and the irrelevant reference signal of the frame frequency of above-mentioned display device, determine that above-mentioned voltage level is stable the writing of pixel of high level during.
Thereby, can be how regardless of the variation of frame frequency, be set at expectation value during writing with pixel is stable.
In addition, as stated, display controller of the present invention; Display device to having a plurality of pixels, video signal cable, scan signal line and scan signal line drive circuit is controlled; Wherein, the said pixel of said vision signal alignment provides data-signal, and said scan signal line and said video signal cable are arranged in a crossed manner; Said scan signal line drive circuit to said scan signal line output scanning signal to drive said scan signal line
In a horizontal period of above-mentioned display device, have during the grid slope that the voltage level of said scanning signals line drive circuit output reduces,
Have and use and the irrelevant reference signal of the frame frequency of above-mentioned display device, determine to determine parts during the grid slope during the grid slope that above-mentioned voltage level reduces.
In addition, as stated, display-apparatus control method of the present invention; Display device to having a plurality of pixels, video signal cable, scan signal line and scan signal line drive circuit is controlled; Wherein, the said pixel of said vision signal alignment provides data-signal, and said scan signal line and said video signal cable are arranged in a crossed manner; Said scan signal line drive circuit to said scan signal line output scanning signal to drive said scan signal line
In a horizontal period of above-mentioned display device, have during the grid slope that the voltage level of said scanning signals line drive circuit output reduces,
Use and the irrelevant reference signal of the frame frequency of above-mentioned display device, determine during the grid slope of above-mentioned voltage level reduction.
Thereby, can be how regardless of the variation of frame frequency, with being set at expectation value during the grid slope.
In addition; As stated, display controller of the present invention is controlled the display device with a plurality of pixels, video signal cable, scan signal line, on-off element and scan signal line drive circuit; Wherein, The said pixel of said vision signal alignment provides data-signal, and said scan signal line and said video signal cable are arranged in a crossed manner, and said on-off element is arranged on the intersection point of said scan signal line and said video signal cable; Said scan signal line drive circuit to said scan signal line output scanning signal to drive said scan signal line
In a horizontal period of above-mentioned display device; Have during being stable the writing of pixel of high level from the voltage level of said scanning signals line drive circuit output, during the grid slope that the voltage level of said scanning signals line drive circuit output reduces and from the voltage level of said scanning signals line drive circuit output be that low level on-off element is between the off period
Said display controller has:
Use and the first irrelevant reference signal of frame frequency, the decision voltage level is to determine parts during the above-mentioned pixel of high level is stablized stable the writing of pixel during writing; And
Use and the second irrelevant reference signal of frame frequency, so that above-mentioned pixel is stable during writing terminal is determined to determine parts during the grid slope during the above-mentioned grid slope as ground, top.
In addition; As stated, display-apparatus control method of the present invention is controlled the display device with a plurality of pixels, video signal cable, scan signal line, on-off element and scan signal line drive circuit; Wherein, The said pixel of said vision signal alignment provides data-signal, and said scan signal line and said video signal cable are arranged in a crossed manner, and said on-off element is arranged on the intersection point of said scan signal line and said video signal cable; Said scan signal line drive circuit to said scan signal line output scanning signal to drive said scan signal line
In a horizontal period of above-mentioned display device; Have during being stable the writing of pixel of high level from the voltage level of said scanning signals line drive circuit output, during the grid slope that the voltage level of said scanning signals line drive circuit output reduces and from the voltage level of said scanning signals line drive circuit output be that low level on-off element is between the off period
Use and the first irrelevant reference signal of frame frequency, the decision voltage level is during to be that the above-mentioned pixel of high level is stable write,
Use and the second irrelevant reference signal of frame frequency, during above-mentioned pixel is stable during writing terminal is determined above-mentioned grid slope as ground, top, and,
Between the off period, stop the action of above-mentioned on-off element at above-mentioned on-off element.
Thereby, can be how regardless of the variation of frame frequency, with pixel is stable write during and be set at expectation value respectively during the grid slope.
The embodiment or the embodiment that reach described in the detailed description of the invention content; Clear and definite up hill and dale technology contents of the present invention; But should not be interpreted as narrowly and be defined in above-mentioned concrete example, spirit of the present invention with after in the claim scope stated, can implement all changes.
Practicality in the industry
The present invention is specially adapted to the mobile device of portable phone or second generation monolithic (One-Segment) LCD, UMPC etc.

Claims (19)

1. display controller; Display device to having a plurality of pixels, video signal cable, scan signal line and scan signal line drive circuit is controlled, and wherein, the said pixel of said vision signal alignment provides data-signal; Said scan signal line and said video signal cable are arranged in a crossed manner; Said scan signal line drive circuit, is characterized in that to drive said scan signal line to said scan signal line output scanning signal
In a horizontal period of said display device, have be stable the writing of pixel of high level from the voltage level of said scan signal line drive circuit output during,
Having the frame frequency according to said display device, the count value of the Dot Clock signal of said display device is changed, is to determine parts during stable the writing of pixel during stable the writing of pixel of high level to determine said voltage level.
2. display controller; Display device to having a plurality of pixels, video signal cable, scan signal line and scan signal line drive circuit is controlled, and wherein, the said pixel of said vision signal alignment provides data-signal; Said scan signal line and said video signal cable are arranged in a crossed manner; Said scan signal line drive circuit, is characterized in that to drive said scan signal line to said scan signal line output scanning signal
In a horizontal period of said display device, have be stable the writing of pixel of high level from the voltage level of said scan signal line drive circuit output during,
Have and use and the irrelevant reference signal of the frame frequency of said display device, determine that said voltage level is to determine parts during stable the writing of pixel during stable the writing of pixel of high level.
3. according to claim 1 or claim 2 display controller is characterized in that,
Even frame frequency changes, said pixel is stable write during the decision parts also can keep during stable the writing of said pixel of temporary transient decision.
4. according to claim 1 or claim 2 display controller is characterized in that,
Said pixel is stable during the decision parts change that said pixel is stable and write according to the kind of said display device during writing.
5. display controller as claimed in claim 4 is characterized in that,
Also have kind according to said display device, during distributing that the decision said pixel that parts determined is stable during writing by said pixel is stable and writing, and the register during in preestablishing during these any.
6. display controller as claimed in claim 5 is characterized in that,
The kind of said display device is to be arranged at the size condition of the panel in the said display device or the resolution condition of said display device at least.
7. a display device is characterized in that,
Has the control assembly that the display controller put down in writing by claim 1 or 2 is controlled.
8. method for controlling display device; This display device has a plurality of pixels, video signal cable, scan signal line and scan signal line drive circuit, and wherein, the said pixel of said vision signal alignment provides data-signal; Said scan signal line and said video signal cable are arranged in a crossed manner; Said scan signal line drive circuit, is characterized in that to drive said scan signal line to said scan signal line output scanning signal
In a horizontal period of said display device, have be stable the writing of pixel of high level from the voltage level of said scan signal line drive circuit output during,
According to the frame frequency of said display device, the count value of the Dot Clock signal of said display device is changed, thereby during determining that said voltage level is stable the writing of pixel of high level.
9. method for controlling display device; This display device has a plurality of pixels, video signal cable, scan signal line and scan signal line drive circuit, and wherein, the said pixel of said vision signal alignment provides data-signal; Said scan signal line and said video signal cable are arranged in a crossed manner; Said scan signal line drive circuit, is characterized in that to drive said scan signal line to said scan signal line output scanning signal
In a horizontal period of said display device, have be stable the writing of pixel of high level from the voltage level of said scan signal line drive circuit output during,
Utilize and the irrelevant reference signal of the frame frequency of said display device, determine that said voltage level is stable the writing of pixel of high level during.
10. display controller; Display device to having a plurality of pixels, video signal cable, scan signal line and scan signal line drive circuit is controlled, and wherein, the said pixel of said vision signal alignment provides data-signal; Said scan signal line and said video signal cable are arranged in a crossed manner; Said scan signal line drive circuit, is characterized in that to drive said scan signal line to said scan signal line output scanning signal
In a horizontal period of said display device, have during the grid slope that the voltage level of said scan signal line drive circuit output reduces,
Have frame frequency, determine to determine parts during the grid slope during the grid slope that said voltage level reduces according to said display device.
11. display controller as claimed in claim 10 is characterized in that,
Even frame frequency changes, the decision parts also can be kept during the said grid slope of temporary transient decision during the said grid slope.
12. like claim 10 or 11 described display controllers, it is characterized in that,
The decision parts change the count value of the Dot Clock signal of said display device, thereby determine during the said grid slope according to the frame frequency of said display device during the said grid slope.
13. display controller as claimed in claim 12 is characterized in that,
During the decision parts change said grid slope according to the kind of said display device during the said grid slope.
14. display controller as claimed in claim 13 is characterized in that,
Also have kind, distribute during the said grid slope during the decision said grid slope that parts determined according to said display device, and the register during in preestablishing during these any.
15. display controller as claimed in claim 14 is characterized in that,
The kind of said display device is to be arranged at the size condition of the panel in the said display device or the resolution condition of said display device at least.
16. a display device is characterized in that,
Has the control assembly of controlling by each display controller of putting down in writing in the claim 10 to 15.
17. method for controlling display device; This display device has a plurality of pixels, video signal cable, scan signal line and scan signal line drive circuit, and wherein, the said pixel of said vision signal alignment provides data-signal; Said scan signal line and said video signal cable are arranged in a crossed manner; Said scan signal line drive circuit, is characterized in that to drive said scan signal line to said scan signal line output scanning signal
In a horizontal period of said display device, have during the grid slope that the voltage of said scan signal line drive circuit output reduces,
According to the frame frequency of said display device, determine during the grid slope of said voltage level reduction.
18. method for controlling display device as claimed in claim 17 is characterized in that,
According to the frame frequency of said display device, the count value of the Dot Clock signal of said display device is changed, thereby determine during the said grid slope.
19. method for controlling display device; This display device has a plurality of pixels, video signal cable, scan signal line, on-off element and scan signal line drive circuit; Wherein, the said pixel of said vision signal alignment provides data-signal, and said scan signal line and said video signal cable are arranged in a crossed manner; Said on-off element is arranged on the intersection point of said scan signal line and said video signal cable; Said scan signal line drive circuit, is characterized in that to drive said scan signal line to said scan signal line output scanning signal
In a horizontal period of said display device; Have during being stable the writing of pixel of high level from the voltage level of said scan signal line drive circuit output, during the grid slope that the voltage level of said scan signal line drive circuit output reduces and from the voltage level of said scan signal line drive circuit output be that low level on-off element is between the off period
According to the frame frequency of said display device, the count value of the Dot Clock signal of said display device is changed, during determining that said voltage level is stable the writing of pixel of high level,
According to the frame frequency of said display device, the count value of the Dot Clock signal of said display device is changed, during said pixel is stable during writing terminal is determined said grid slope as ground, top,
And at said on-off element between the off period, make said on-off element stop action.
CN201110339476.4A 2006-09-05 2007-06-08 The control method of display controller, display device, display system and display device Expired - Fee Related CN102426826B (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2006-240776 2006-09-05
JP2006240776 2006-09-05
CN200780029423.4A CN101501753B (en) 2006-09-05 2007-06-08 Display controller, display device, display system and method for controlling display device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
CN200780029423.4A Division CN101501753B (en) 2006-09-05 2007-06-08 Display controller, display device, display system and method for controlling display device

Publications (2)

Publication Number Publication Date
CN102426826A true CN102426826A (en) 2012-04-25
CN102426826B CN102426826B (en) 2016-03-02

Family

ID=39156991

Family Applications (2)

Application Number Title Priority Date Filing Date
CN200780029423.4A Expired - Fee Related CN101501753B (en) 2006-09-05 2007-06-08 Display controller, display device, display system and method for controlling display device
CN201110339476.4A Expired - Fee Related CN102426826B (en) 2006-09-05 2007-06-08 The control method of display controller, display device, display system and display device

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CN200780029423.4A Expired - Fee Related CN101501753B (en) 2006-09-05 2007-06-08 Display controller, display device, display system and method for controlling display device

Country Status (3)

Country Link
US (2) US8896590B2 (en)
CN (2) CN101501753B (en)
WO (1) WO2008029546A1 (en)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101719352B (en) * 2008-10-09 2012-07-25 北京京东方光电科技有限公司 Device and method for detection after forming liquid crystal box
KR101082167B1 (en) * 2009-09-07 2011-11-09 삼성모바일디스플레이주식회사 Organic Light Emitting Display and Driving Method Thereof
US9111502B2 (en) * 2012-11-30 2015-08-18 Shenzhen China Star Optoelectronics Technology Co., Ltd Driving circuit and LCD device having data monitoring module
JP2015072310A (en) * 2013-10-01 2015-04-16 株式会社ジャパンディスプレイ Liquid crystal display device
CN104299588B (en) 2014-10-27 2017-01-11 京东方科技集团股份有限公司 Grid drive circuit, grid drive method and display device
CN104867473B (en) * 2015-06-16 2018-03-20 深圳市华星光电技术有限公司 Driving method, drive device and display device
US10366663B2 (en) * 2016-02-18 2019-07-30 Synaptics Incorporated Dithering a clock used to update a display to mitigate display artifacts
JP2018019207A (en) * 2016-07-27 2018-02-01 富士ゼロックス株式会社 Cooperation management device and communication system
US10916212B2 (en) * 2016-09-06 2021-02-09 Sakai Display Products Corporation Display device with two gate drive circuits and gate slope forming sections for reducing display uneveness
CN107402486B (en) * 2017-08-31 2020-06-30 京东方科技集团股份有限公司 Array substrate, driving method thereof and display device
KR102489597B1 (en) * 2017-12-27 2023-01-17 엘지디스플레이 주식회사 Display interface device
CN112289268A (en) * 2020-11-02 2021-01-29 武汉华星光电技术有限公司 Driving method and device of display panel
CN115132129B (en) * 2022-07-07 2023-08-08 惠科股份有限公司 Driving circuit, display module and display device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003345317A (en) * 2003-05-09 2003-12-03 Sharp Corp Display device and display method
CN1624752A (en) * 2003-11-10 2005-06-08 Lg.菲利浦Lcd株式会社 Driving unit for liquid crystal display device

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3245918B2 (en) 1992-01-20 2002-01-15 カシオ計算機株式会社 Image display device
US5559620A (en) 1992-03-05 1996-09-24 Casio Computer Co., Ltd. Anti-ferroelectric liquid crystal display device with intersecting alignment film directions
JPH063647A (en) 1992-06-18 1994-01-14 Sony Corp Drive method for active matrix type liquid crystal display device
US5821910A (en) * 1995-05-26 1998-10-13 National Semiconductor Corporation Clock generation circuit for a display controller having a fine tuneable frame rate
JPH09265077A (en) 1996-03-29 1997-10-07 Matsushita Electric Ind Co Ltd Anti-ferroelectric liquid crystal element drive method
JPH11174415A (en) 1997-12-10 1999-07-02 Canon Inc Electro-optical device
JP3406508B2 (en) * 1998-03-27 2003-05-12 シャープ株式会社 Display device and display method
JP3595745B2 (en) * 1999-01-29 2004-12-02 キヤノン株式会社 Image processing device
JP3620434B2 (en) * 2000-07-26 2005-02-16 株式会社日立製作所 Information processing system
JP2003114648A (en) * 2001-09-28 2003-04-18 Internatl Business Mach Corp <Ibm> Liquid crystal display device, computer device and its control method for driving lcd panel
JP2004287164A (en) * 2003-03-24 2004-10-14 Seiko Epson Corp Data driver and optoelectronic device
JP3726910B2 (en) * 2003-07-18 2005-12-14 セイコーエプソン株式会社 Display driver and electro-optical device
JP2006072078A (en) * 2004-09-03 2006-03-16 Mitsubishi Electric Corp Liquid crystal display device and its driving method
US7598959B2 (en) * 2005-06-29 2009-10-06 Intel Corporation Display controller
JP2007072365A (en) * 2005-09-09 2007-03-22 Renesas Technology Corp Driving device for display device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003345317A (en) * 2003-05-09 2003-12-03 Sharp Corp Display device and display method
CN1624752A (en) * 2003-11-10 2005-06-08 Lg.菲利浦Lcd株式会社 Driving unit for liquid crystal display device

Also Published As

Publication number Publication date
CN102426826B (en) 2016-03-02
US20150035815A1 (en) 2015-02-05
US9336738B2 (en) 2016-05-10
WO2008029546A1 (en) 2008-03-13
US20090295779A1 (en) 2009-12-03
CN101501753A (en) 2009-08-05
US8896590B2 (en) 2014-11-25
CN101501753B (en) 2011-12-28

Similar Documents

Publication Publication Date Title
CN101501753B (en) Display controller, display device, display system and method for controlling display device
US9075472B2 (en) Display device having partial panels and driving method thereof
TWI391848B (en) Display device and electronic apparatus
US8289312B2 (en) Liquid crystal display device
CN101739981B (en) Liquid crystal display
CN100356439C (en) Display driver, electro-optical device, and method of driving electro-optical device
CN101884062A (en) Display device and method for driving display device
US20190197976A1 (en) Active-matrix display device and method for driving the same
CN103137077A (en) Controlling the stabilization period of an electrophoresis display device
US8421780B2 (en) Counter circuit, control signal generating circuit including the counter circuit, and display apparatus
US20210327388A1 (en) Scanning signal line drive circuit, display device provided with same, and driving method of scanning signal line
CN107204168B (en) Driving method for display panel
CN103268748B (en) A kind of voltage control method of electrode and device
CN114995678A (en) Liquid crystal display device and related electronic equipment
KR20080018648A (en) Liquid crystal display and driving method thereof
US9412323B2 (en) Power saving method and related waveform-shaping circuit
KR101989931B1 (en) Liquid crystal display and undershoot generation circuit thereof
CN103745706B (en) The array base palte horizontal drive circuit that three rank drive
EP3040982A1 (en) Gate drive circuit, gate driving method, and display device
KR101785339B1 (en) Common voltage driver and liquid crystal display device including thereof
CN214504392U (en) Touch display device and electronic equipment
KR100430093B1 (en) Method and Apparatus of Driving Liquid Crystal Panel
KR20160083378A (en) Display device and gate driving circuit thereof
KR100365657B1 (en) Driving method of a display device and a driving circuit
KR100701071B1 (en) The method of controlling source drive integrated circuit in liquid crystal disply device

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20160302

Termination date: 20200608