CN102420613A - High-speed high-resolution digital acquisition device and processing method of controllable triggering period signal - Google Patents
High-speed high-resolution digital acquisition device and processing method of controllable triggering period signal Download PDFInfo
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Abstract
The invention discloses a high-speed high-resolution digital acquisition device and a processing method of a controllable triggering period signal. The high-speed high-resolution digital acquisition device is characterized in that 1+N analogue-to-digital converters are arranged in the high-speed high-resolution digital acquisition device, and the input end of each analogue-to-digital converter is provided with a time delayer in a connecting manner, thus 1+N time delayers corresponding to the 1+N analogue-to-digital converters are arranged in the high-speed high-resolution digital acquisition device, wherein the output end of each analogue-to-digital converter is connected with the input end of a large programmable logic device. The invention has the advantages that: an AD (Analog-to-Digital) acquisition control and pre-processing unit consisting of an FPGA (Field Programmable Gate Array) and multiple paths of AD converters are utilized, thus the sampling time resolution of high-speed digital acquisition is largely increased, and the high-speed high-resolution digital acquisition processing method of the controllable triggering period signal, disclosed by the invention, has remarkable substantial characteristics and remarkable improvement compared with the prior art.
Description
Technical field
The present invention relates to the technical field of Fibre Optical Sensor, a kind of specifically high speed, high resolution digital collection device and processing method thereof of controlled triggering periodic signal, particularly its inner electrical connecting structure.
Background technology
Along with the high speed development of electronic device and reaching its maturity of computer bus technology, the sampling rate of data acquisition has obtained develop rapidly, and A/D sample rate has now reached 10GS/s.Owing to the development of high-speed digitization technology, the A/D sample rate improves greatly, this spatial resolution and acquisition precision from having improved system to a great extent in recent years.
In distributed optical fiber sensing system, spatial resolution is a crucial parameter, and distributed optical fiber sensing system carries out the digitized sampling processing to the waveform signal of tested optical fiber, and the size in sampling interval directly influences resolution of ranging.If high-resolution distributed optical fiber sensing system resolution of ranging is 1m, then require the interval of signal sampling is not more than 1 ns.Obviously, realize that 1 ns Direct Sampling at interval is difficult to realize.
What realize the high-resolution sampling at present mainly is that accidental sampling is used in the digital oscilloscope of high sampling resolution.It is applicable to the periodicity emphasis complex signal; Utilize time interval double slanted measurement by magnification technology; Can accomplish very high temporal resolution; The major defect of this method is that the sampling appearance time of view picture waveform is long, and the characteristic requirements of measuring with the distributed optical fiber sensing system quick real-time contradicts, and the circuit more complicated.
Summary of the invention
The object of the present invention is to provide a kind of high speed, high resolution digital collection device of controlled triggering periodic signal; Its figure place that adopts the multi-channel A capture card is more than 12; Thereby improved the sampling time resolution that high-speed figure is gathered greatly, overcome the shortcoming and defect that exists in the prior art.
To achieve these goals; Technical scheme of the present invention is: the high speed, high resolution digital collection device of controlled triggering periodic signal; It is characterized in that: be provided with 1+N platform analog to digital converter in the said high speed, high resolution digital collection device; The input of every analog to digital converter all is connected with a time delays device; Platform number with respect to analog to digital converter in the said high speed, high resolution digital collection device is provided with 1+N platform time delays device, and the output of analog to digital converter is connected with the input of extensive programmable logic device.
Monocycle, different triggering sampling was synthetic to reach the effect that improves sampling rate.In distributed optical fiber sensing system, the signal of spontaneous back scattering light signal produces through exciting of laser pulse, and whole system is by the lock-out pulse co-ordination.In other words; When control system produces a lock-out pulse; Laser emission light pulse, receiver begins to receive the consequent spontaneous back scattering light signal of processing simultaneously, and lock-out pulse produces a plurality of different delayed time through the over-sampling delayer sampling trigger signal carries out different triggering sampling to spontaneous back scattering light signal of the input monocycle of multi-channel A/D analog to digital converter; Reducing signals sampling at interval, thereby improve the spatial resolution of signal digital sampling.
The performance of high-speed a/d sampling card mainly shows three aspects to the influence of system:
sampling rate and bandwidth;
data acquisition modes;
sampling resolution and precision; 4. data signal processing method.Analyze one by one in the face of its each performance index down.
(1) sampling rate and bandwidth
Distributed fiberoptic sensor system requirements system space resolution reaches 1m; Sampling rate and its A/D of A/D sampling card are inversely proportional to change-over time, draw thus under the spatial resolution of 1m requires, and the required minimum sampling rate of A/D sampling card is 100MHz; Therefore; When sampling sticked into the row design to A/D, list considered that from the angle of system space resolution requirement its sampling rate must be not less than 100MHz.If want further to improve the spatial resolution of system, then A/D sampling card will need higher sampling rate again.
As a kind of preferred version of the present invention, the sampling rate and the bandwidth of the special-purpose AD capture card of said high-speed, high precision distributed temperature measuring are >=100 MHz.
(2) sampling resolution and precision
The resolution of A/D sampling card is meant the minimum change of the distinguishable input signal of A/D sampling card, common least significant bit (LSB) decision by A/D sampling card.Improve sampling resolution and precision, must increase the figure place of A/D sampling card, can improve analog-to-digital precision and reliability like this.Yet the figure place of A/D sampling card is many more, and the speed of its conversion is slow more, and this will influence the temporal resolution of system.In addition, when selecting the figure place of A/D sampling card, also the dynamic range of considered and real input signal adapts.The cost of A/D sampling card also is the factor that must consider.
(3) data signal processing method
In distributed optical fiber temperature transducer system, adopt the time domain cumulative mean to improve the signal to noise ratio of system usually and recover the method for waveform.In distributed fiberoptic sensor, adopted the linear accumulation mode of multi-point average.
After the multiple spot cumulative mean; The signal to noise ratio of sampled signal is improved greatly, average preceding acquisition
raising doubly.The method of time-domain digital signal cumulative mean is the basic skills of distributed optical fiber temperature sensor signal processing.
A kind of high speed, high resolution digital collection device processing method of controlled triggering periodic signal, it is characterized in that: the step of processing method is following
(1) initialization address generator;
(2) 1+N road analog to digital converter data are put into corresponding pre-stored module;
(3) memory cell of address generator indication is taken out data and is put into two-way memory module from the pre-stored module;
(4) data in pre-stored module and the corresponding two-way memory module are sent into the respective adders addition;
(5) result of adder deposits two-way separately memory module in;
(6) address counter adds 1;
(7) judge whether to accomplish adding up of an amplitude wave shape each point,, then turn back to step (1) and continue if do not accomplish; If accomplish, then carry out downwards;
(8) judge whether to accomplish the average time of setting,, then turn back to step (1) and continue if do not accomplish; If accomplish, then finish.
The invention discloses a kind of high speed, high resolution digital collection device and processing method thereof of controlled triggering periodic signal, beneficial effect of the present invention is: the present invention utilizes scale programmable logic device (FPGA) to form the high speed, high resolution digital collection processing method of the controlled triggering periodic signal of AD acquisition controlling and pretreatment unit and multi-channel A/D analog to digital converter design.The high speed, high resolution digital collection method of controlled triggering periodic signal with the waveform signal in each cycle by certain hour at interval (after △ t=1ns) the different triggering n of time-delay road AD analog to digital converter is sampled respectively and is added up; The corresponding address that generates by address generator P1 then leaves in the array; The n circuit-switched data that is about to all different triggering collection of delaying time of amplitude wave shape is all read in the array; Data in the array are synthesized a complete high-resolution sampled data; Thereby improved the sampling time resolution that high-speed figure is gathered greatly, had outstanding substantive distinguishing features and marked improvement compared to existing technologies.
Description of drawings
Fig. 1 is a structure function property structured flowchart of the present invention.
Fig. 2 is the different triggering high speed acquisition of the time-delay of a controlled triggering periodic signal sequential chart.
Fig. 3 is the memory location figure of each channel signal of the present invention in array.
Embodiment
With reference to the accompanying drawings, the present invention is further described.
The present invention is a kind of high speed, high resolution digital collection device of controlled triggering periodic signal; As shown in fig. 1; It is different from prior art and is: be provided with 1+N platform analog to digital converter 1 in the said high speed, high resolution digital collection device; The input of every analog to digital converter 1 all is connected with a time delays device 2; Platform number with respect to analog to digital converter 1 in the said high speed, high resolution digital collection device is provided with 1+N platform time delays device 2, and the output of analog to digital converter 1 is connected with the input of extensive programmable logic device 3.
As a kind of preferred version of the present invention, the figure place of the special-purpose AD capture card of said dual channel high speed high accuracy distributed temperature measuring is that sample strip is wider than 100MHz more than 12.
In the specific implementation; Be provided with 1+N pre-stored module 4 in the said extensive programmable logic device 3; Be provided with 1+N adder 5, the two-way memory module 6 of 1+N with respect to pre-stored module 4; The first input end of each pre-stored module 4 is the output of a corresponding analog to digital converter 1 separately; First output of each pre-stored module 4 is connected with the first input end of an adder 5; Input/output terminal is two-way is connected for the input/output terminal of adder 5 and a two-way memory module 6 first; The two-way connection of first input/output terminal of two-way memory module 6 second input/output terminals and communication transport module 7, second input of said pre-stored module 4 is connected with timing control unit 8 first outputs, and first input/output terminal of timing control unit 8 is connected with the input/output terminal of address generator 9 is two-way; Be provided with clock 10 between timing control unit 8 and the address generator 9; Second input/output terminal of timing control unit 8 is connected with the input/output terminal of time delays device 2 is two-way, and first output of address generator 9 is connected with pre-stored module 4 second inputs, adder 5 first input ends, two-way memory module 6 first input ends respectively, second input/output terminal of said communication transport module 7 and 11 two-way connections of PCI/ISA bus.
In the specific implementation; Be provided with 1+N group analog to digital converter 1 and time delays device 2 in the said high speed, high resolution digital collection device; When being provided with many group analog to digital converters 1 with time delays device 2, between them the parallel data transmission structure, every all independent corresponding pre-stored module 4 of analog to digital converter 1.
In the specific implementation; Be provided with 1+N group pre-stored module 4, adder 5, two-way memory module 6 in the said extensive programmable logic device 3; When the pre-stored of group more than being provided with module 4, adder 5, two-way memory module 6; Be the parallel data transmission structure between them, every two-way memory module 6 all with 7 two-way connections of communication transport module.
The rear orientation light form entering main amplifying circuit with analog electrical signal after opto-electronic conversion that carries temperature signal in the distributed fiberoptic sensor amplifies; The signal level of coming out gets into 1+n road ultra high speed A module subsequently and scale programmable logic device (FPGA) is formed the AD acquisition controlling and processing unit carries out data processing, just finally obtains the temperature field data of corresponding points.Therefore; After sending light pulse; Lock-out pulse produces a plurality of different delayed time through the over-sampling delayer sampling trigger signal carries out different triggering sampling to spontaneous back scattering light signal of the input monocycle of multi-channel A/D analog to digital converter;, just can obtain along fiber axis to the rear orientation light signal distributions, realize that distributing optical fiber sensing measures.
Introduce with regard to the specific embodiments of the high-speed figure collector of controlled triggering periodic signal below.
The high-speed figure collector of controlled triggering periodic signal mainly comprises n road ultra high speed A module, time delays device and scale programmable logic device (FPGA) composition AD acquisition controlling and processing unit.Its function mainly be with in APD opto-electronic conversion distributed fiberoptic sensor, carry temperature signal after carry out high-speed digitization to the Raman scattering photosignal; And carry out buffer memory after the data preliminary treatment such as multiple averaging adds up; Handle to computer by the PCI/ISA interface communication again, thereby obtain behind the space of fiber distribution information to Raman diffused light.
The workflow of the high-speed figure collector of controlled triggering periodic signal is when control system produces a lock-out pulse; Laser emission light pulse; Receiver begins to receive the consequent spontaneous back scattering light signal of processing simultaneously; Scattering photodetection signal is input into the A/D change-over circuit that the parallel 100MHz ultra high speed A chip in n road is formed; The lock-out pulse of light pulse produces a plurality of different delayed time through the over-sampling delayer sampling trigger signal carries out different triggering sampling to spontaneous back scattering light signal of the input monocycle of n road A/D analog to digital converter; N road AD sampled data result is fed in the scale programmable logic device (FPGA) core design FIFO memory module as buffer memory, to handle storage and the matching problem of transmission between A/D sampling card and the computer preferably.
In the side circuit design, the unitary sampling frequency is 100MHz, and the corresponding time interval can be decided to be 10ns, and corresponding fiber distance is about 1m.For realizing 1 Ocm resolution, adopt time-delay dislocation synthetic schemes, the index request of time-delay resolution is superior to 1 ns, makes the sampling interval reach 1ns.
As shown in Figure 2; For an amplitude wave deltoid; Press 10ns (about 1m optical fiber at interval) sampling one frame data at interval; Control next frame waveform signal time-delay 1ns (approximately O.1m optical fiber at interval) second frame data of sampling that the second road AD analog to digital converter is gathered then, so sampling, the waveform that the synthetic panel height resolution of n frame data that each controlled triggering periodic signal is gathered by n road AD analog to digital converter is sampled.
In design, this product adopts the precision time delay chip as the precision time delay circuit, and when trigger impulse arrived, the timing control unit of scale programmable logic device (FPGA) was regulated the delay control signal of setting trigger impulse according to host computer instruction output.
The time-delay sequential that produces is as shown in Figure 3.The high-speed figure collector of controlled triggering periodic signal (deposits the waveform signal of one-period among corresponding pre-stored module R1～RN in like data after △ t=1ns) the different triggering n of time-delay road AD analog to digital converter is sampled by certain hour at interval; Respective adders is read the pre-stored module and is added up with the last cumulative data of corresponding two-way memory module storage afterwards; The corresponding address that generates by address generator P1 then leaves in the array; The n circuit-switched data that is about to all different triggering collection of delaying time of amplitude wave shape is all read in the array, and the data in the array are synthesized a complete high-resolution sampled data.
This method is analyzed and computing with regard to the data in available this array.Fig. 3 shows the position that the sampled data of each paths is deposited in array.
Wherein, the data of " △ " expression first via channel sample, the sampling of " ◇ " expression second paths
Data, the data of the 3rd periodic sampling of " zero " expression, the synthetic number of times of " n " expression, " K "
The data volume of representing the sampling of every paths, " L " expression the data total amount that will sample.The relation of K and L is: K=L/n.
As shown in Figure 3, first data of " O " expression first via channel sample are placed in the array on O the position; First data of " 1 " expression second paths sampling are placed in the array on the 1st position: first data of " 2 " expression Third Road channel sample are placed in the array on the 2nd position; First data of " n 1 " expression n paths sampling are placed in the array on one 1 positions of n: second data of " n " expression first via channel sample are placed in the array on n the position; And the like can the data of L altogether of required sampling be placed in the array in order, synthesize a complete high-resolution sampled data.
Different triggering sampling of monocycle synthetic technology has solved the contradiction between high-resolution and the big data quantity.Delay time through regulating the time delays device just can carry out the high-resolution sampling and testing to the fiber-optic signal of any range finding range, optional position.
Because the test waveform of the high-speed figure collector of controlled triggering periodic signal refreshes in real time; So will carry out high speed storing, stack, average for the data of sampling gained; For unlikely microprocessor is produced overcharge; This method specialized designs hardware circuit FPGA design come auxiliary storage, the stack of accomplishing data, and average work is accomplished by the microprocessor upper computer software.Circuit in the past is owing to adopt a large amount of discrete devices, and complex circuit, noise, power consumption are all very big, have adopted extensive programmable gate array device FPGA at present, have simplified design, greatly reduce noise and power consumption, have improved the performance of average treatment.According to the above, the storage of this method design, the theory diagram of stack are as shown in Figure 1:
The work of above each several part is under the control of FPGA, to carry out, and entire work process can be used following concise and to the point step narration:
(1) initialization address generator;
(2) 1+N road analog to digital converter data are put into corresponding 1+N pre-stored module;
(3) memory cell of address generator indication is taken out data and is put into the two-way memory module of corresponding 1+N from the pre-stored module of 1+N road;
(4) data in the two-way memory module in 1+N road of 1+N road pre-stored module and correspondence are sent into the respective adders addition;
(5) result of adder deposits two-way separately memory module in;
(6) address counter adds 1;
(7) judge whether to accomplish adding up of an amplitude wave shape each point,, then turn back to step (1) and continue if do not accomplish; If accomplish, then carry out downwards;
(8) judge whether to accomplish the average time of setting,, then turn back to step (1) and continue if do not accomplish; If accomplish, then finish.
After hardware had been accomplished the stack of set point number, the stack result among two-way memory module DR1～DRn was delivered to microprocessor and is carried out the division arithmetic with respect to average time, and this process is accomplished by software fully.The overlaying scheme that hardware and software combines can be simplified circuit can realize the high-speed data processing again.
In the high-speed figure collector of high-resolution controlled triggering periodic signal, require real-time processing signals, processing speed is fast, and operating frequency is high; When adopting standard TTL or cmos circuit to form, complicated circuit, the printed board area is bigger; It is longer to connect up, and causes phase mutual interference and time delay, adds the influence of whole system wiring; Make it that certain intrinsic noise arranged, can't eliminate, influenced the overall performance of system with the method for average.Use scale programmable logic device (FPGA) to carry out programmed, a slice can replace multi-disc and even tens preferred circuits, and complete machine integrated circuit number is reduced; Thereby the printed board size is less, and cabling shortens, and machine routing shortens; Reduce the intrinsic noise of summation averaging system so greatly; Help improving the performance of system, make also that the instrument power consumption reduces, weight reduces, volume-diminished, improves reliability.
Scale programmable logic device (FPGA) adopts the Virtex-5 family device core design of XiLinx company to comprise functional module elements such as timing control unit, address generator, adder, two-way memory module, communications module.
The timing control unit of core design in the scale programmable logic device (FPGA); Function is to realize the accurate SECO of n ultra high speed A chip; And regulate the delay control signal of setting trigger impulse according to host computer instruction output, be used to accomplish the co-ordination of whole system.
The 1+n road pre-stored module of core design in the scale programmable logic device (FPGA), function are to deposit the data of the last time sampling of 1+n road ultra high speed A module.
The address generator of core design in the scale programmable logic device (FPGA), function are that the data memory module for the last time sampling of depositing 1+n road ultra high speed A module and the last accumulation result provides unique geocoding.
The 1+n road adder of core design is by the lock-out pulse co-ordination of outside input in the scale programmable logic device (FPGA), and the synchronizing signal mode is that rising edge triggers, can be by upper computer selecting internal trigger or synchronously outer.Function mainly be accomplish with two-way scattered light signal data last time add up and with the function that current data adds up once more, the result after adding up sends into corresponding two-way memory module and stores, the data acquisition degree of depth and accumulative frequency can be designed by upper computer software.
The communications modular unit of FPGA core design realizes that sending into microprocessor display to the result data after adding up through the PCI/ISA bus comes out.
The above person is merely most preferred embodiment of the present invention, is not to be used to limit scope of the present invention, and all equivalences of doing according to claim of the present invention change or modify, and are all the present invention and contain.
Here description of the invention and application is illustrative, is not to want with scope restriction of the present invention in the above-described embodiments.Here the distortion of the embodiment that is disclosed and change are possible, and the replacement of embodiment is known with the various parts of equivalence for those those of ordinary skill in the art.Those skilled in the art are noted that under the situation that does not break away from spirit of the present invention or substantive characteristics, and the present invention can be with other forms, structure, layout, ratio, and realize with other elements, material and parts.Under the situation that does not break away from the scope of the invention and spirit, can carry out other distortion and change here to the embodiment that is disclosed.
Claims (6)
1. the high speed, high resolution digital collection device of controlled triggering periodic signal; It is characterized in that: be provided with 1+N platform analog to digital converter (1) in the said high speed, high resolution digital collection device; The input of every analog to digital converter (1) all is connected with a time delays device (2); Platform number with respect to analog to digital converter (1) in the said high speed, high resolution digital collection device is provided with 1+N platform time delays device (2), and the output of analog to digital converter (1) is connected with the input of extensive programmable logic device (3).
2. the high speed, high resolution digital collection device of controlled triggering periodic signal according to claim 1; It is characterized in that: be provided with 1+N pre-stored module (4) in the said extensive programmable logic device (3); Be provided with 1+N adder (5), the two-way memory module of 1+N (6) with respect to pre-stored module (4); The first input end of each pre-stored module (4) is the output of a corresponding analog to digital converter (1) separately; First output of each pre-stored module (4) is connected with the first input end of an adder (5); Input/output terminal is two-way is connected for the input/output terminal of adder (5) and a two-way memory module (6) first; The two-way connection of first input/output terminal of two-way memory module (6) second input/output terminals and communication transport module (7); Second input of said pre-stored module (4) is connected with timing control unit (8) first outputs; The two-way connection of input/output terminal of first input/output terminal of timing control unit (8) and address generator (9); Be provided with clock (10) between timing control unit (8) and the address generator (9), the two-way connection of input/output terminal of second input/output terminal of timing control unit (8) and time delays device (2), first output of address generator (9) is connected with pre-stored module (4) second inputs, adder (5) first input end, two-way memory module (6) first input end respectively.
3. the high speed, high resolution digital collection device of controlled triggering periodic signal according to claim 1; It is characterized in that: be provided with 1+N group analog to digital converter (1) and time delays device (2) in the said high speed, high resolution digital collection device; When being provided with many group analog to digital converters (1) and time delays device (2); Between them the parallel data transmission structure, all independent corresponding pre-stored module (4) of every analog to digital converter (1).
4. the high speed, high resolution digital collection device of controlled triggering periodic signal according to claim 1; It is characterized in that: be provided with 1+N group pre-stored module (4), adder (5), two-way memory module (6) in the said extensive programmable logic device (3); When being provided with many group pre-stored modules (4), adder (5), two-way memory module (6); Be the parallel data transmission structure between them, every two-way memory module (6) all with two-way connection of communication transport module (7).
5. the high speed, high resolution digital collection device of controlled triggering periodic signal according to claim 2 is characterized in that: second input/output terminal of said communication transport module (7) and two-way connection of PCI/ISA bus (11).
6. the high speed, high resolution digital collection device processing method of controlled triggering periodic signal, it is characterized in that: the step of processing method is following
(1) initialization address generator;
(2) 1+N road analog to digital converter data are put into corresponding pre-stored module;
(3) memory cell of address generator indication is taken out data and is put into two-way memory module from the pre-stored module;
(4) data in pre-stored module and the corresponding two-way memory module are sent into the respective adders addition;
(5) result of adder deposits two-way separately memory module in;
(6) address counter adds 1;
(7) judge whether to accomplish adding up of an amplitude wave shape each point,, then turn back to step (1) and continue if do not accomplish; If accomplish, then carry out downwards;
(8) judge whether to accomplish the average time of setting,, then turn back to step (1) and continue if do not accomplish; If accomplish, then finish.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102931994A (en) * | 2012-09-26 | 2013-02-13 | 成都嘉纳海威科技有限责任公司 | High-speed signal sampling and synchronizing framework and method applied to signal processing chip |
| CN103791937A (en) * | 2014-01-15 | 2014-05-14 | 上海波汇通信科技有限公司 | Device and method for acquiring data in distributed optical fiber sensing system |
| CN106385256A (en) * | 2016-09-22 | 2017-02-08 | 电子科技大学 | Multi-channel parallel acquisition system with storage function and synchronous recognition function |
| CN107947793A (en) * | 2017-11-13 | 2018-04-20 | 苏州云芯微电子科技有限公司 | A kind of circuit and method for the calibration of multi-chip analog-digital converter sampling phase uniformity |
| CN110823560A (en) * | 2018-08-07 | 2020-02-21 | 上海华依科技集团股份有限公司 | Data acquisition method for automatic transmission offline test system |
| CN111277248A (en) * | 2020-04-03 | 2020-06-12 | 中国科学院近代物理研究所 | Multi-working-mode synchronous pulse generating device and working method thereof |
| CN111928972A (en) * | 2020-08-06 | 2020-11-13 | 中国人民解放军海军工程大学 | Method and system for improving spatial resolution of distributed optical fiber temperature measurement system |
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2010
- 2010-09-27 CN CN201010292844XA patent/CN102420613A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102931994A (en) * | 2012-09-26 | 2013-02-13 | 成都嘉纳海威科技有限责任公司 | High-speed signal sampling and synchronizing framework and method applied to signal processing chip |
| CN102931994B (en) * | 2012-09-26 | 2015-11-25 | 成都嘉纳海威科技有限责任公司 | Be applied to high speed signal sampling and synchronous framework and the method for signal processing chip |
| CN103791937A (en) * | 2014-01-15 | 2014-05-14 | 上海波汇通信科技有限公司 | Device and method for acquiring data in distributed optical fiber sensing system |
| CN103791937B (en) * | 2014-01-15 | 2016-05-11 | 上海波汇科技股份有限公司 | The apparatus and method of data acquisition in a kind of distributed optical fiber sensing system |
| CN106385256A (en) * | 2016-09-22 | 2017-02-08 | 电子科技大学 | Multi-channel parallel acquisition system with storage function and synchronous recognition function |
| CN106385256B (en) * | 2016-09-22 | 2019-01-25 | 电子科技大学 | With the multi-channel parallel acquisition system for storing synchronous identification function |
| CN107947793A (en) * | 2017-11-13 | 2018-04-20 | 苏州云芯微电子科技有限公司 | A kind of circuit and method for the calibration of multi-chip analog-digital converter sampling phase uniformity |
| CN107947793B (en) * | 2017-11-13 | 2021-02-26 | 苏州云芯微电子科技有限公司 | Circuit and method for multi-chip analog-to-digital converter sampling phase consistency calibration |
| CN110823560A (en) * | 2018-08-07 | 2020-02-21 | 上海华依科技集团股份有限公司 | Data acquisition method for automatic transmission offline test system |
| CN111277248A (en) * | 2020-04-03 | 2020-06-12 | 中国科学院近代物理研究所 | Multi-working-mode synchronous pulse generating device and working method thereof |
| CN111277248B (en) * | 2020-04-03 | 2023-09-19 | 中国科学院近代物理研究所 | Synchronous pulse generating device with multiple working modes and working method thereof |
| CN111928972A (en) * | 2020-08-06 | 2020-11-13 | 中国人民解放军海军工程大学 | Method and system for improving spatial resolution of distributed optical fiber temperature measurement system |
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Application publication date: 20120418 |