CN102420175B - Method for adding contact hole etching process window by setting top etching barrier layer - Google Patents
Method for adding contact hole etching process window by setting top etching barrier layer Download PDFInfo
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- CN102420175B CN102420175B CN2011101602870A CN201110160287A CN102420175B CN 102420175 B CN102420175 B CN 102420175B CN 2011101602870 A CN2011101602870 A CN 2011101602870A CN 201110160287 A CN201110160287 A CN 201110160287A CN 102420175 B CN102420175 B CN 102420175B
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Abstract
The invention discloses a method for adding a contact hole etching process window by setting a top etching barrier layer. According to the method, an etching stop layer which is generally positioned at the bottom of a dielectric layer is moved to the top and can be selectively made of silicon nitride. The method adopts the following basic flows of: firstly, normally etching to reach the height of a silicon gate; secondly, additionally arranging a mask plate of which the area contains holes on a substrate; selectively etching the contact hole by using a top film as a hard barrier layer, wherein the general etching depth is about 800A, the etching stop layer can be stripped in the subsequent CMP (Chemical Mechanical Polishing) engineering or can be certainly retained and the etching stop layer has no influence on the subsequent engineering. Although one extra photoetching work procedure is additionally arranged, a process window of the flow can be greatly increased and the area of a chip is reduced.
Description
Technical field
The present invention relates to a kind of semiconducter process, relate in particular to a kind of top etching barrier layer that arranges to increase the method for contact hole etching process window.
Background technology
Along with the develop rapidly of semiconductor technology, process node is scaled, and wherein the spacing of Si-gate and Si-gate is that whole technique requires one of the harshest engineering to photoetching in integrated.For the control device short-channel effect, the width of side wall (spacer) is attenuate significantly.The contact hole etching technique of main flow is generally all used the bottom etching stop layer at present, realizes the etching of the poor oxide-film of differing heights, and thickness does not wait at 200 ~ 600A.This causes the space of leaving follow-up contact hole for significantly to dwindle, and can only in designing requirement, stipulate upwards to connect contact hole in the place of Si-gate minimum spacing, and give relatively well-to-do pitch space of contact hole engineering.Certainly, this class way sacrifice be to have increased chip area, improve chip cost.
The storage circuit design is particularly deeply concerned to chip area, the stint no sacrifice device speed of some technique (such as SONOS technique), by in the Si-gate deposit silicon nitride, in conjunction with phosphorosilicate glass (PSG), it is metal front insulation layer, do not use the bottom etching stop layer, utilize merely dry etching to different oxide-films, the etching selection ratio of nitride film, reach and dwindle contact hole.Wherein, the contact hole etching technique of main flow is generally all used the bottom etching stop layer at present, realizes the etching of the poor oxide-film of differing heights.Generally its technological process is listed as follows:
Step a: the long-pending bottom of pad etching stop layer: silicon nitride (200-600A left and right)
Step b: contact hole insulating barrier film forming, then to interlayer film CMP
Step c: contact hole engineering photoetching
Steps d: contact hole engineering dry etching, first etching interlayer film also stops at the bottom etching stop layer, then adds quarter
Step e: the bottom etching stop layer, finally remove photoresist
Step f: follow-up normal metal chemical industry journey
It is the hole dry etching to be required too high that but there is the problem of a maximum in this type of technique, and process window is quite little, is unfavorable for scale of mass production.
Summary of the invention
The invention discloses a kind of top etching barrier layer that arranges to increase the method for contact hole etching process window, in order to solve prior art, carry out in the process of etching, if the spacing to Si-gate and Si-gate is controlled, to the hole dry etching, require too high, and process window is quite little, be unfavorable for the problem of scale of mass production.
Above-mentioned purpose of the present invention is achieved through the following technical solutions:
A kind of method of top etching barrier layer with increase contact hole etching process window that arrange, wherein,
Step a: include on the substrate of semiconductor device unit and form an interlayer dielectric layer one, the first grid simultaneously the semiconductor device unit comprised and second grid cover;
Step b: deposit one etching barrier layer on described dielectric layer;
Step c: spin coating photoresist on etching barrier layer, carry out the opening figure that photoetching for the first time forms gate via, active area through hole, grid-active area through hole;
Steps d: utilize opening figure to carry out the first dry etching, open etching barrier layer, and the etching dielectric layer, to form gate via, active area through hole and grid-active area through hole, make the bottom of described gate via terminate in and contact described first grid; The bottom of described active area through hole is terminated in dielectric layer, and the active area of contact semiconductor device cell not; Make the part zone of described grid-active area via bottoms terminate in and contact described second grid, make another part zone of grid-active area via bottoms terminate in dielectric layer simultaneously, and the active area of contact semiconductor device cell not;
Step e: remove photoresist;
Step f: spin coating photoresist on etching barrier layer for the second time, and carry out photoetching for the second time, and the photoresist of spin coating for the second time covers described gate via, and the formed opening figure of photoetching is for the second time exposed described active area through hole and grid-active area through hole;
Step g: utilize the formed opening figure of photoetching for the second time to carry out the second dry etching, etch away the dielectric layer of described active area via bottoms until the source region through hole terminates in and the contact portion active area, and etch away the dielectric layer that described grid-active area via bottoms terminates in the below, part zone in dielectric layer, until grid-active area through hole terminates in and the contact portion active area;
Step h: the photoresist of spin coating is for the second time removed.
The top etching barrier layer that arranges as above is to increase the method for contact hole etching process window, wherein, also comprise after described steps d: carry out over etching, the degree of depth that makes described active area through hole and grid-active area through hole is all over the degree of depth of described gate via.
The top etching barrier layer that arranges as above to be to increase the method for contact hole etching process window, wherein, by the THICKNESS CONTROL of described etching barrier layer at 100A between 400A.
The top etching barrier layer that arranges as above is to increase the method for contact hole etching process window, and wherein, in step b, deposit silicon nitride is to form described etching barrier layer.
The top etching barrier layer that arranges as above is to increase the method for contact hole etching process window, and wherein, the precision of described photoetching for the first time is greater than the precision of described photoetching for the second time.
The top etching barrier layer that arranges as above, to increase the method for contact hole etching process window, wherein, also comprises after described step a: the technique of dielectric layer being carried out to the cmp planarization.
The top etching barrier layer that arranges as above is to increase the method for contact hole etching process window, wherein, the degree of depth of the formed active area through hole of described over etching and grid-active area through hole be the formed active area through hole of the first dry etching and grid-active area through hole the degree of depth 20%.
The top etching barrier layer that arranges as above is to increase the method for contact hole etching process window, wherein, final grid-active area through hole is placed in described second grid and part active area top simultaneously, and by the electric conducting material be filled in grid-active area through hole, second grid is electrically connected with the part active area that grid-active area through hole contacts, and the cross section of grid-active area through hole is rectangle.
The top etching barrier layer that arranges as above, to increase the method for contact hole etching process window, wherein, also comprises after step h: carry out conventional follow-up metallization engineering.
The top etching barrier layer that arranges as above, to increase the method for contact hole etching process window, wherein, also comprises after step h: in carrying out subsequent chemistry mechanical lapping engineering, described etching barrier layer is peeled off.
In sum, owing to having adopted technique scheme, the present invention arranges the top etching barrier layer and makes the method for window by the common etching stop layer in the dielectric layer bottom is moved to top to increase contact hole etching, carry out afterwards the technological operation of two photoetching and etching, form respectively the contact hole of a plurality of different depths, in technical scheme disclosed in this invention, increased together extra photo-mask process, greatly increase the process window of flow process, dwindle chip area.
The accompanying drawing explanation
Fig. 1 is that the present invention arranges the top etching barrier layer and makes the schematic diagram after blanket dielectric layer on the active area of method of window to increase contact hole etching;
Fig. 2 is that the present invention arranges the top etching barrier layer and makes the schematic diagram after deposit on the dielectric layer of method of window forms etching barrier layer to increase contact hole etching;
Fig. 3 is that the present invention arranges the schematic diagram top etching barrier layer is made the photoetching for the first time of method of window to increase contact hole etching after;
Fig. 4 is that the present invention arranges the schematic diagram top etching barrier layer is made the dry etching for the first time of method of window to increase contact hole etching after;
Fig. 5 is that the present invention arranges the schematic diagram top etching barrier layer is made the removal photoresist of method of window to increase contact hole etching after;
Fig. 6 is that the present invention arranges the schematic diagram top etching barrier layer is made the photoetching for the second time of method of window to increase contact hole etching after;
Fig. 7 is that the present invention arranges the schematic diagram top etching barrier layer is made the dry etching for the second time of method of window to increase contact hole etching after;
Fig. 8 is that the present invention arranges the schematic diagram top etching barrier layer is made the photoresist of removal spin coating for the second time of method of window to increase contact hole etching after;
Fig. 9 be the present invention arrange the top etching barrier layer with increase contact hole etching make window method carry out the structural representation after over etching.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is further described:
A kind of method of top etching barrier layer with increase contact hole etching process window that arrange, wherein,
Fig. 1 is that the present invention arranges the top etching barrier layer and makes the schematic diagram after blanket dielectric layer on the active area of method of window to increase contact hole etching, refer to Fig. 1, step a: one, include on the substrate 101 of semiconductor device unit and form a dielectric layer 102, first grid 201 and second grid 202 are covered, in the semiconductor device unit quantity of the grid of similar first grid 201 and second grid 202 actual have a plurality of, device does not draw fully for simplicity, the sidewall of first grid 201 and second grid 202 all is surrounded with side wall separator (unmarked), therefore, dielectric layer 102 covers on the side wall separator simultaneously.Be different from prior art, at first the present invention carries out the formation of dielectric layer 102, carries out afterwards the formation of etching barrier layer 103 again.
Fig. 2 is that the present invention arranges the top etching barrier layer and makes the schematic diagram after deposit on the dielectric layer of method of window forms etching barrier layer to increase contact hole etching, refer to Fig. 2, step b: deposit one etching barrier layer 103 on described dielectric layer 102, make and can using etching barrier layer 103 carry out optionally contact hole etching as hard barrier layer in subsequent technique by deposit etching barrier layer 103 on dielectric layer 102, the thickness basis of etching barrier layer 103 contact hole for the second time needs the degree of depth of etching to determine, by the second dry etching, need the degree of depth of etching to determine, the second dry etching needs the degree of depth of etching darker, etching barrier layer 103 is thicker, otherwise, etching barrier layer 103 is thinner,
In the present invention, the thickness of described etching barrier layer 103 generally all is controlled to 100A between 400A.
In step b of the present invention, deposit silicon nitride is to form described etching barrier layer 103, and preferably, etching barrier layer 103 adopts fine and close silicon nitride to form, and further, etching barrier layer 103 also can adopt other material.
Also comprise after described step a in the present invention: the technique that dielectric layer 102 is carried out to the cmp planarization makes the upper surface of the dielectric layer 102 that forms smooth.
Described grid in the present invention-active area through hole 303 is for be placed in the rectangular opening of described second grid 202 and described active area top simultaneously, be also first in the photoresistance 106 that plays the mask effect, to be formed with the opening figure (can be controlled by the photo mask board pattern) of some rectangles in the second dry etching process, make it to be transferred in the grid of dielectric layer 102-active area through hole 303, thereby the cross section of formed grid-active area through hole 303 or vertical view are the holes (for example being generally rectangular hole) of a rectangle.
Fig. 3 is that the present invention arranges the schematic diagram top etching barrier layer is made the photoetching for the first time of method of window to increase contact hole etching after, refer to Fig. 3, step c: spin coating photoresist 104 on etching barrier layer 103, carry out photoetching for the first time and form gate via 301, active area through hole 302, the figure of grid-active area through hole 303, wherein, gate via 301 figures are placed in the top of the polysilicon of first grid 201, active area through hole 302 figures are placed in the top of active area, grid-the figure of active area through hole 303 is placed in the top of second grid 202 and active area simultaneously,
Fig. 4 is that the present invention arranges the schematic diagram top etching barrier layer is made the dry etching for the first time of method of window to increase contact hole etching after, refer to Fig. 4, steps d: carry out the first dry etching, open etching barrier layer 103, and etching dielectric layer 102, to form gate via 301, active area through hole 302 and grid-active area through hole 303, make described gate via 301 terminate in described first grid 201, by the first dry etching, make gate via 301 etch into the degree of depth of polysilicon; Described active area through hole 302 terminates in the top of described active area, and does not contact described active area; Described grid-active area through hole 303 parts terminate in described second grid 202, and another part terminates in the top of described active area, and do not contact described active area;
Fig. 5 is that the present invention arranges the schematic diagram top etching barrier layer is made the removal photoresist of method of window to increase contact hole etching after, refer to Fig. 5, step e: remove photoresist 104, owing to needing to recoat photoresist 106 in subsequent technique, therefore need in this processing step, the photoresist 104 of spin coating for the first time thoroughly be removed;
Fig. 6 is that the present invention arranges the schematic diagram top etching barrier layer is made the photoetching for the second time of method of window to increase contact hole etching after, refer to Fig. 6, step f: the spin coating photoresist 106 for the second time, photoresist 106 is spin-coated on etching barrier layer 103 equally, carry out afterwards photoetching for the second time, the figure that photoetching for the second time forms covers described gate via 301, described active area through hole 302 and grid-active area through hole 303 exposes, and for follow-up, further is etched with source region through hole 302 and grid-active area through hole 303 is ready;
Described in the present invention, the precision of photoetching for the second time is less than the precision of described photoetching for the first time, because the figure of photoetching is for the second time only required cover gate through hole 301, expose active area through hole 302 and grid-active area through hole 303, without forming precision graphic, therefore lower for the required precision of photoetching for the second time.
Fig. 7 is that the present invention arranges the schematic diagram top etching barrier layer is made the dry etching for the second time of method of window to increase contact hole etching after, refer to Fig. 7, step g: carry out the second dry etching, because photoresist 106 seals gate via 301, therefore the second dry etching only carries out etching to active area through hole 302 and grid-active area through hole 303, by carrying out the second dry etching, increase the degree of depth of active area through hole 302 and grid-active area through hole 303, make described active area through hole 302 terminate in active area, and make described grid-active area through hole 303 parts terminate in described second grid 202, another part terminates in described active area, wherein, total etching depth of active area through hole 302 and grid-active area through hole 303 is all in the 800A left and right,
Fig. 8 is that the present invention arranges the schematic diagram top etching barrier layer is made the photoresist of removal spin coating for the second time of method of window to increase contact hole etching after, refers to Fig. 8, step h: will 106 removals of the photoresist of spin coating for the second time.
After step h in the present invention, also comprise: carry out conventional follow-up metallization engineering, the present invention and prior art be I believe, have only increased by one extra photoetching process, and can follow-up technique not impacted.
After step h in the present invention, also comprise: in carrying out subsequent chemistry mechanical lapping engineering, described etching barrier layer 103 is peeled off, further, under the prerequisite that does not affect subsequent technique, also this etching barrier layer 103 can be retained.Shown in Fig. 8, because final obtained grid-active area through hole 303 parts drop on second grid 202 and part active area (202 active area on contiguous second grid) top, so can reduce the quantity as the metal interlamination medium layer that forms interconnection line in follow-up processing step, and the electric conducting material replaced in grid-active area through hole 303 is electrically connected second grid 202 with the part active area that grid-active area through hole 303 contacts as far as possible.In addition, for example, with any material (common stress film or bottom etching stop layer), do not cover the grid 101,102 of substrate 101 and semiconductor unit before forming dielectric layer 102, this has reduced operation on the one hand, on the other hand, in the etching process of follow-up through hole 302,303 contact active areas, reduced the etching requirement, otherwise just need to utilize the etching selection ratio of dry etching to different oxide-films, nitride film, reach the purpose of dwindling contact hole, visible the present invention has effectively avoided the excessive demand to the through hole dry etching.
Fig. 9 be the present invention arrange the top etching barrier layer with increase contact hole etching make window method carry out the structural representation after over etching, refer to Fig. 9, after described steps d, also comprise: carry out over etching, make the degree of depth of described active area through hole 301 and grid-active area through hole 303 all over described gate via.
The degree of depth of the described over etching institute etching in the present invention is 20% of the first dry etching degree of depth, in the process of etching dielectric layer, the degree of depth A2 of the formed active area through hole of over etching dielectric layer and grid-active area through hole be the formed active area through hole of the first dry etching (etching dielectric layer) and grid-active area through hole degree of depth A1 20%.
Further, also include a shallow via regions 105 in the present invention, be arranged on a side of described active area, described grid-active area through hole 303 same some terminate in described shallow via regions 105.
In sum, owing to having adopted technique scheme, the present invention arranges the top etching barrier layer and is moved to top with the method that increases contact hole etching and make window by the etching stop layer in the dielectric layer bottom usually, and its material can be chosen as silicon nitride.Typical process flow, at first normally etching into the Si-gate height, then increases a mask, and the hole on the district inclusion silicon substrate utilizes top-film as hard barrier layer, carrys out optionally etching contact hole, and general etching depth is in the 800A left and right.Etching stop layer can be peeled off in subsequent chemistry mechanical lapping (CMP) engineering, can certainly select to retain, and it exists does not affect successive projects.Although increased together extra photo-mask process, can greatly increase the process window of flow process, dwindle chip area.
Above specific embodiments of the invention be have been described in detail, but it is just as example, the present invention is not restricted to specific embodiment described above.To those skilled in the art, any equivalent modifications that the present invention is carried out and alternative also all among category of the present invention.Therefore, equalization conversion and the modification done without departing from the spirit and scope of the invention, all should contain within the scope of the invention.
Claims (10)
1. one kind arranges the top etching barrier layer to increase the method for contact hole etching process window, it is characterized in that,
Step a: include on the substrate of semiconductor device unit and form an interlayer dielectric layer one, the first grid simultaneously the semiconductor device unit comprised and second grid cover;
Step b: deposit one etching barrier layer on described interlayer dielectric layer;
Step c: spin coating photoresist on etching barrier layer, carry out the opening figure that photoetching for the first time forms gate via, active area through hole, grid-active area through hole;
Steps d: utilize opening figure to carry out the first dry etching, open etching barrier layer, and the etching interlayer dielectric layer, to form gate via, active area through hole and grid-active area through hole, make the bottom of described gate via terminate in and contact described first grid; The bottom of described active area through hole is terminated in interlayer dielectric layer, and the active area of contact semiconductor device cell not; Make the part zone of described grid-active area via bottoms terminate in and contact described second grid, make another part zone of grid-active area via bottoms terminate in interlayer dielectric layer simultaneously, and the active area of contact semiconductor device cell not;
Step e: remove photoresist;
Step f: spin coating photoresist on etching barrier layer for the second time, and carry out photoetching for the second time, and the photoresist of spin coating for the second time covers described gate via, and the formed opening figure of photoetching is for the second time exposed described active area through hole and grid-active area through hole;
Step g: utilize the formed opening figure of photoetching for the second time to carry out the second dry etching, etch away the dielectric layer of described active area via bottoms until the active area through hole terminates in and the contact portion active area, and etch away the dielectric layer that described grid-active area via bottoms terminates in the below, part zone in dielectric layer, until grid-active area through hole terminates in and the contact portion active area;
Step h: the photoresist of spin coating is for the second time removed.
2. the top etching barrier layer that arranges according to claim 1 is to increase the method for contact hole etching process window, it is characterized in that, also comprise after described steps d: carry out over etching, the degree of depth that makes described active area through hole and grid-active area through hole is all over the degree of depth of described gate via.
3. the top etching barrier layer that arranges according to claim 1, to increase the method for contact hole etching process window, is characterized in that, by the THICKNESS CONTROL of described etching barrier layer at 100A between 400A.
4. the top etching barrier layer that arranges according to claim 1, to increase the method for contact hole etching process window, is characterized in that, in step b, deposit silicon nitride is to form described etching barrier layer.
5. the top etching barrier layer that arranges according to claim 1, to increase the method for contact hole etching process window, is characterized in that, the precision of described photoetching for the first time is greater than the precision of described photoetching for the second time.
6. the top etching barrier layer that arranges according to claim 1, to increase the method for contact hole etching process window, is characterized in that, after described step a, also comprises: the technique of dielectric layer being carried out to the cmp planarization.
7. the top etching barrier layer that arranges according to claim 2 is to increase the method for contact hole etching process window, it is characterized in that, the degree of depth of the formed active area through hole of described over etching and grid-active area through hole be the formed active area through hole of the first dry etching and grid-active area through hole the degree of depth 20%.
8. the top etching barrier layer that arranges according to claim 1 is to increase the method for contact hole etching process window, it is characterized in that, final grid-active area through hole is placed in described second grid and part active area top simultaneously, and by the electric conducting material be filled in grid-active area through hole, second grid is electrically connected with the part active area that grid-active area through hole contacts, and the cross section of grid-active area through hole is rectangle.
9. the top etching barrier layer that arranges according to claim 1, to increase the method for contact hole etching process window, is characterized in that, after step h, also comprises: carry out conventional follow-up metallization engineering.
10. the top etching barrier layer that arranges according to claim 1, to increase the method for contact hole etching process window, is characterized in that, after step h, also comprises: in carrying out subsequent chemistry mechanical lapping engineering, described etching barrier layer is peeled off.
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| CN105789115A (en) | 2016-04-26 | 2016-07-20 | 京东方科技集团股份有限公司 | Via hole manufacturing method, array substrate and manufacturing method thereof and display device |
| CN110879344A (en) * | 2019-11-13 | 2020-03-13 | 上海华力集成电路制造有限公司 | Shared contact hole and etching defect detection method thereof |
| CN113808998A (en) * | 2020-06-16 | 2021-12-17 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
| CN115881687A (en) * | 2021-08-27 | 2023-03-31 | 长鑫存储技术有限公司 | Semiconductor structure, semiconductor structure manufacturing method and memory |
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| JP3941133B2 (en) * | 1996-07-18 | 2007-07-04 | 富士通株式会社 | Semiconductor device and manufacturing method thereof |
| KR100596834B1 (en) * | 2003-12-24 | 2006-07-04 | 주식회사 하이닉스반도체 | Method for Forming Polysilicon Plug of Semiconductor Device |
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| CN1166055A (en) * | 1996-05-23 | 1997-11-26 | 世界先进积体电路股份有限公司 | Method for producing connecting wire of conductor |
| CN1469434A (en) * | 2002-07-17 | 2004-01-21 | 茂德科技股份有限公司 | Contact hole forming process |
| CN101752314A (en) * | 2008-12-04 | 2010-06-23 | 上海华虹Nec电子有限公司 | Surface channel PMOS device with self-aligned contact hole and manufacturing method |
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