CN103474389B - The manufacture method of metal interconnect structure - Google Patents
The manufacture method of metal interconnect structure Download PDFInfo
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- CN103474389B CN103474389B CN201210184977.4A CN201210184977A CN103474389B CN 103474389 B CN103474389 B CN 103474389B CN 201210184977 A CN201210184977 A CN 201210184977A CN 103474389 B CN103474389 B CN 103474389B
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Abstract
A manufacture method for metal interconnect structure, comprising: first provide the Semiconductor substrate with target electric coupling area; Then in this Semiconductor substrate, form photoresist, photoresist exposed, develop after at least retain photoresist on target electric coupling area; Then deposit low temperature oxide skin(coating) on the photoresist of Semiconductor substrate and reservation; Then in low temperature oxide layer, height of formation is greater than the first dielectric layer of the photoresist of reservation and the height sum of low temperature oxide layer again; The residual altitude of low temperature oxide layer to the first dielectric layer removed subsequently on the first dielectric layer of Partial Height and the photoresist of reservation flushes with the photoresist of reservation; Remove the photoresist of described reservation afterwards, to form groove in described first dielectric layer; Finally in this groove, insert conductive material and remove the Excess conductive material outside described groove.Adopt manufacture method of the present invention to form the method for metal interconnect structure, can have greatly improved to the uniformity of chip live width.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of manufacture method of metal interconnect structure.
Background technology
Metal interconnect structure is the indispensable structure of semiconductor device.In semiconductor fabrication, the quality of the metal interconnect structure of formation has a significant impact the performance of semiconductor device and semiconductor manufacturing cost.
The manufacture method of existing metal interconnect structure, such as power mos transistor device, generally comprise: first dielectric layer on active area structure, form contact hole pattern within it afterwards, then in contact hole, insert metal form conductive plunger, on this conductive plunger and dielectric layer, upper strata dielectric layer is formed after planarization, adopt photoetching process on the dielectric layer of upper strata, define the photoresist of strip region afterwards, subsequently with this photoresist for mask carries out etching the groove formed for the formation of metal interconnect structure.
But, carry out define pattern with photoresistance exposure, in process dielectric layer etched with plasma, often find pattern that density is different critical size after etching can difference very large, this directly can have influence on the connection of interconnect architecture and front layer electric conductor.Also the different problem of critical size can be there is in the pattern that the region at center and edge is identical.And these problems carry out define pattern in existing having with photoresistance exposure, be very formidable in technological process dielectric layer etched with plasma.
In view of this, the present invention proposes a kind of manufacture method of new metal interconnect structure, to solve the problem.
Summary of the invention
The problem that the present invention solves is the manufacture method proposing a kind of new metal interconnect structure, to solve the problem changed with pattern density and residing wafer position of the rear critical size of metal interconnect structure etching that existing manufacture method is formed.
For solving the problem, the invention provides a kind of manufacture method of metal interconnect structure, the method comprises:
Semiconductor substrate is provided, described Semiconductor substrate has target electric coupling area;
Form photoresist on the semiconductor substrate, described photoresist exposed, develop after at least retain photoresist on target electric coupling area;
Deposit low temperature oxide skin(coating) in described Semiconductor substrate and photoresist;
Described low temperature oxide layer is formed the first dielectric layer, and the height of described first dielectric layer is greater than the photoresist of described reservation and the height sum of low temperature oxide layer;
The low temperature oxide layer removed on described first dielectric layer of Partial Height and the photoresist of described reservation flushes to residual altitude with the photoresist of reservation;
Remove the photoresist of described reservation, to form groove in described first dielectric layer;
In described groove, insert conductive material and the Excess conductive material removed outside described groove to form metal interconnect structure.
Alternatively, target electric coupling area is and the source electrode of transistor, grid or the conductive plunger be directly electrically connected that drains.
Alternatively, target electric coupling area is the conductive plunger of front layer.
Alternatively, before forming photoresist on the semiconductor substrate, also bottom anti-reflection layer is formed on the semiconductor substrate.
Alternatively, the Semiconductor substrate provided also is formed with etch stop layer; Before formation bottom anti-reflection layer is formed on the semiconductor substrate, also the etch stop layer on described target electric coupling area is removed.
Alternatively, the material of described etch stop layer is at least one in silicon dioxide, silicon nitride, silicon oxynitride, carborundum, carbonitride of silicium.
Alternatively, described low temperature oxide layer adopts atomic layer deposition method to be formed.
Alternatively, described first dielectric layer removing Partial Height adopts dry etching.
Alternatively, the dielectric constant k scope of the material of described first dielectric layer is 2.0<k<4.0.
Alternatively, the method removing the photoresist of described reservation is that wet method is removed, the liquid adopted is PGME(propyleneglycolmonomethylester) or PGMEA(propyleneglycolmonomethylesteracetate), or the mixed liquor of these two kinds of organic liquor.
Alternatively, the dielectric constant k scope of the material of described first dielectric layer is 2.7<k<4.0, and the method removing the photoresist of described reservation is dry etching, adopts gas to be oxygen base plasma.
Alternatively, the conductive material inserted in described groove is at least one in copper, aluminium, tungsten, silver, gold.
Compared with prior art, the present invention has the following advantages:
Be different from and of the prior artly form metal interconnect structure by dry etching in the dielectric layer, the present invention adopts the photoresist of patterning as core (core), dielectric layer is formed around the photoresist of described patterning, after removing described photoresist afterwards, this photoresist is according to the shape of pattern, can groove be left, afterwards in this groove filled conductive material correspondingly to form metal interconnect structure.Because said method is more simpler than traditional Damascus technics, avoiding with photoresistance is the etching process of mask to dielectric layer, thus avoid difference after the pattern critical size of definition after development and etching between critical size along with pattern density and on wafer the different and different problem of present position, achieve the uniformity improving chip live width.
Accompanying drawing explanation
Fig. 1 is the manufacturing process flow chart of the metal interconnect structure in the embodiment of the present invention;
Fig. 2 to Figure 10 is the intermediate structure schematic diagram of the metal interconnect structure according to the manufacture method formation in Fig. 1;
Figure 11 is the final structure schematic diagram of the metal interconnect structure according to the manufacture method formation in Fig. 1.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.Because the present invention focuses on interpretation principle, therefore, chart not in scale.
The manufacture method of the metal interconnect structure that the present invention proposes, belong to the back-end process of semiconductor applications, thus, the present embodiment, the conductive plunger in the front layer of metal interconnect structure to be formed the upper strata metal interconnect structure be electrically connected with it, introduces manufacture method of the present invention in detail.
First the flow chart of composition graphs 1, perform step S11, provide Semiconductor substrate, described Semiconductor substrate has target electric coupling area, wherein, this target electric coupling area is the conductive plunger of front layer in metal interconnect structure.In other embodiment, this target electric coupling area also can be and the source electrode of transistor, grid or the conductive plunger be directly electrically connected that drains.
Shown in Figure 2, in the present embodiment, substrate can be silicon, germanium or SiGe etc., it is formed with multiple active, passive device.Active device is such as planar transistor MOS, and its structure comprises on source electrode, drain electrode, channel region between source electrode and drain electrode and is formed with gate insulator, grid successively.In other embodiment, this MOS transistor also can be groove type MOS transistor (TrenchMOS).The source electrode of MOS transistor, drain electrode, grid can also be formed with metal silicide to reduce contact resistance.
In most cases, active, passive device need to be formed with other device or control circuit through multilevel metal interconnection structure and be electrically connected, to realize respective function.Such as, MOS transistor is connected with bit line, wordline etc. by 8 layers of metal interconnect structure, between 8 layers of metal interconnect structure, particularly, between MOS transistor and first layer metal pattern (Metal1), each layer metal pattern (Metal1, Metal2 ...) between by conductive plunger realize interconnection.Continue with reference to shown in Fig. 3, conductive plunger 31 is the target electric coupling area of the present embodiment, and this conductive plunger 31 is formed in interlayer dielectric layer 30, is connected with front layer metal pattern (not shown), thus, also claims the conductive plunger 31 of front layer; The substrate comprising the conductive plunger 31 of front layer is the Semiconductor substrate of the present embodiment.In other embodiment, the conductive plunger that, passive device active with various is directly connected, the conductive plunger be such as directly connected with the source electrode of MOS transistor, drain electrode, grid is also target electric coupling area of the present invention, and comprising the conductive plunger that, passive device active with various be directly connected is Semiconductor substrate of the present invention.
Then perform step S12, as shown in Figure 3, the described Semiconductor substrate comprising conductive plunger 31 and this conductive plunger 31 is carried out to the interlayer dielectric layer 30 of electric insulation forms etch stop layer 32(EtchStopLayer, ESL).The region that this etch stop layer 32 is not opened, plays the effect of insulating to the region under it.
In specific implementation process, the material of described etch stop layer 32 is at least one in silicon dioxide, silicon nitride, silicon oxynitride, carborundum, carbonitride of silicium.
This step is optional step.
Then perform step S13, remove the etch stop layer on described target electric coupling area.
In the present embodiment, target electric coupling area is conductive plunger 31, and the method removing the etch stop layer 32 on it is photoetching, etching.Non-targeted electric coupling area, the residual photoresist namely on interlayer dielectric layer 30 adopts wet method or ashing method to remove.After this step is finished, the structural section figure of formation as shown in Figure 4.
This step is optional step.
Then perform step S14, form bottom anti-reflection layer on the semiconductor substrate.
The bottom anti-reflection layer 33 of this step is formed on etch stop layer 32 and on the conductive plunger 31 exposed.After this step is finished, the structural section figure of formation as shown in Figure 5.
This step is optional step.
Perform step S15, bottom anti-reflection layer 33 form photoresist, described photoresist is exposed, develop after at least retain photoresist on target electric coupling area.
As above give an account of and continue, bottom anti-reflection layer 33 forms photoresist, after utilizing mask plate to expose, after development, by using plasma etching to be removed by unnecessary bottom reflector, form the photoresist 34 of patterning, the photoresist 34 corresponding upper strata metal pattern of this patterning, for forming electrical connection between upper and lower metal pattern, thus at least need to retain the photoresist 34 on conductive plunger 31.Photoresist in this step can select positive photoresist, also can select negative photoresist, and needed for concrete exposure imaging process, technique is existing technique, does not repeat them here.
In other embodiments, if without etch stop layer 32, bottom anti-reflection layer 33, then the direct interlayer dielectric layer 30 carrying out electric insulation at conductive plunger 31 and this conductive plunger 31 forms photoresist.
Due in the present invention, the photoresist 34 of this reservation, also the photoresist of patterning is claimed, object is the position occupying metal interconnection pattern in the subsequent dielectric layer, therefore, in this step, the pattern of the photoresist 34 of this reservation is upper strata metal pattern, the bottom at least part of region of photoresist 34 of this reservation is dropped on target electricity electric coupling area completely, is on conductive plunger 31 in the present embodiment.With reference to shown in Fig. 6, remain the photoresist 34 in two regions, one of them corresponding conductive plunger 31, another removes rear object for forming metal pattern, this another photoresist 34 is not connected with front layer conductive plunger, or be connected with the target electric coupling area of another corresponding section, be such as connected with other conductive plunger of front layer.In addition, do not need the bottom anti-reflection layer 33 retaining photoresist region to be substantially consumed in this step, if there is residual bottom anti-reflection layer, then remove, method is such as dry etching.
Then step S16 is performed, with reference to shown in Fig. 7, deposit low temperature oxide skin(coating) 35 on the photoresist 34 of etch stop layer 32 and described reservation.
In this step, this low temperature oxide layer 35(lowtemperatureoxide, LTO) cover photoetching agent pattern 34, can avoid follow-up when needing hot conditions to form the first dielectric layer, to the infringement of photoetching agent pattern 34, cause it to be out of shape.The material of this low temperature oxide, such as, for passing through the low temperature oxide that atomic layer deposition method (ALD) generates within 100 degrees Celsius.
Perform step S17 afterwards, with reference to shown in Fig. 8, low temperature oxide layer 35 forms the first dielectric layer 36, the height of described first dielectric layer 36 is greater than the photoresist 34 of described reservation and the height sum of both the low temperature oxide layer 35 on it.
The material of the first dielectric layer 36 can be the silicon dioxide of dielectric constant 2.7<k<4.0, for reducing parasitic capacitance, also can be the super low-K dielectric material of dielectric constant between 2.0-2.7.
Then, perform step S18, with reference to shown in Fig. 9, the low temperature oxide layer 35 removed on described first dielectric layer 36 of Partial Height and the photoresist 34 of described reservation flushes to the described residual altitude of the first dielectric layer 36 with the photoresist 34 of reservation.
This step adopts dry etching, and the low temperature oxide layer 35 on the photoresist 34 of reservation is also etched removal, and etching gas is fluoro-gas, such as CF
4, C
4f
8deng.This step also can adopt cmp (CMP).
After step S15 is finished, the photoresist 34 of reservation protrudes from Semiconductor substrate, and the object of step S17 and step S18 is the region that employing first dielectric layer 36 fills outside the photoresist 34 that retains.
In other embodiment, if without etch stop layer 32, then carry out the interlayer dielectric layer 30 of electric insulation and the photoresist 34 of reservation form the first dielectric layer 36 at conductive plunger 31, this conductive plunger 31, remove Partial Height afterwards to concordant with the height of the photoresist 34 of described reservation.
Afterwards, perform step S19, remove the photoresist 34 of described reservation, to form groove to expose target electric coupling area in described first dielectric layer 36.
With reference to shown in Figure 10, when removing the photoresist 34 of described reservation, the bottom anti-reflection layer 33 under it is also removed substantially simultaneously.In addition, in this removal process, material or the dielectric constant of the first dielectric layer need be considered, such as in step S17, the dielectric constant k scope of the material of described first dielectric layer 36 is 2.0<k<4.0, then remove described reservation photoresist 34 and under the method for bottom anti-reflection layer 33 be that wet method is removed, the liquid adopted is PGME(propyleneglycolmonomethylester) or PGMEA(propyleneglycolmonomethylesteracetate), or the arbitrary proportion mixed liquor of these two kinds of organic liquor.It should be noted that, when the dielectric constant k scope of the material of the first dielectric layer 36 is 2.7<k<4.0, remove described reservation photoresist 34 and under the method for bottom anti-reflection layer 33 can also for dry etching, gas is adopted to be oxygen base plasma, such as oxygen, carbon dioxide or carbon monoxide.
Due to the metal interconnection pattern that photoresist 34 correspondence of this patterning need be formed, thus, after this step is finished, the region that the photoresist 34 be before patterned occupies is exposed formation groove, this groove at least exposes target electric coupling area, and in the present embodiment, a groove exposes conductive plunger 31, another groove is metal pattern or is connected with the target electric coupling area of another section, such as, be connected with the conductive plunger of another section.
Finally perform step S20, with reference to shown in Figure 11, in described groove, insert conductive material 37 and the Excess conductive material 37 removed outside described groove to form metal interconnect structure.
In the process of implementation, the conductive material 37 inserted in groove such as, for realizing the material of conducting function, at least one in copper, aluminium, tungsten, silver, gold, but can be not limited to above-mentioned material to this step.The conductive material 37 removed outside groove can adopt CMP or method for etching plasma.
Through above-mentioned steps, define a kind of new metal interconnect structure.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.
Claims (12)
1. a manufacture method for metal interconnect structure, is characterized in that, comprising:
Semiconductor substrate is provided, described Semiconductor substrate has target electric coupling area;
Form photoresist on the semiconductor substrate, described photoresist exposed, develop after at least retain photoresist on target electric coupling area to form the photoresist of patterning;
Deposit low temperature oxide skin(coating) on the patterned photo glue of described Semiconductor substrate and reservation;
Described low temperature oxide layer is formed the first dielectric layer, and the height of described first dielectric layer is greater than the patterned photo glue of described reservation and the height sum of low temperature oxide layer;
Low temperature oxide layer to the described residual altitude of the first dielectric layer removed on described first dielectric layer of Partial Height and the patterned photo glue of described reservation flushes with the photoresist of reservation;
Remove the patterned photo glue of described reservation, to form groove in described first dielectric layer;
In described groove, insert conductive material and the Excess conductive material removed outside described groove to form metal interconnect structure.
2. manufacture method according to claim 1, is characterized in that, described target electric coupling area is the conductive plunger be directly connected with the source electrode of transistor, grid or the electricity that drains.
3. manufacture method according to claim 1, is characterized in that, described target electric coupling area is the conductive plunger of front layer.
4. manufacture method according to claim 1, is characterized in that, before forming photoresist on the semiconductor substrate, also forms bottom anti-reflection layer on the semiconductor substrate.
5. manufacture method according to claim 4, is characterized in that, the Semiconductor substrate provided also is formed with etch stop layer; Before forming bottom anti-reflection layer on the semiconductor substrate, also the etch stop layer on described target electric coupling area is removed.
6. manufacture method according to claim 5, is characterized in that, the material of described etch stop layer is at least one in silicon dioxide, silicon nitride, silicon oxynitride, carborundum, carbonitride of silicium.
7. manufacture method according to claim 1, is characterized in that, described low temperature oxide layer adopts atomic layer deposition method to be formed.
8. manufacture method according to claim 1, is characterized in that, described first dielectric layer removing Partial Height adopts dry etching.
9. manufacture method according to claim 1, is characterized in that, the dielectric constant k scope of the material of described first dielectric layer is 2.0<k<4.0.
10. manufacture method according to claim 9, is characterized in that, the method removing the photoresist of described reservation is that wet method is removed, and the liquid of employing is PGME or PGMEA, or the mixed liquor of these two kinds of organic liquor.
11. manufacture methods according to claim 1, it is characterized in that, the dielectric constant k scope of the material of described first dielectric layer is 2.7<k<4.0, and the method removing the photoresist of described reservation is dry etching, adopts gas to be oxygen base plasma.
12. manufacture methods according to claim 1, is characterized in that, the conductive material inserted in described groove be in copper, aluminium, tungsten, silver, gold in one or combination.
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| CN101416278A (en) * | 2006-04-07 | 2009-04-22 | 美光科技公司 | Simplified technological process for doubling range interval |
| CN102169825A (en) * | 2010-02-12 | 2011-08-31 | 三星电子株式会社 | Method of forming fine patterns of semiconductor device |
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| CN101416278A (en) * | 2006-04-07 | 2009-04-22 | 美光科技公司 | Simplified technological process for doubling range interval |
| CN102169825A (en) * | 2010-02-12 | 2011-08-31 | 三星电子株式会社 | Method of forming fine patterns of semiconductor device |
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