CN103474389A - Metal interconnection structure manufacturing method - Google Patents
Metal interconnection structure manufacturing method Download PDFInfo
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- CN103474389A CN103474389A CN2012101849774A CN201210184977A CN103474389A CN 103474389 A CN103474389 A CN 103474389A CN 2012101849774 A CN2012101849774 A CN 2012101849774A CN 201210184977 A CN201210184977 A CN 201210184977A CN 103474389 A CN103474389 A CN 103474389A
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Abstract
A metal interconnection structure manufacturing method comprises the following steps: firstly, a semiconductor substrate with a target electric connection area is provided; secondly, a photoresist is formed on the semiconductor substrate, exposure and development are carried out on the photoresist, and the photoresist on the target electric connection area is at least retained; thirdly, a low-temperature oxide layer is deposited on both the semiconductor substrate and the retained photoresist; fourthly, a first dielectric layer having a height greater than the sum of the height of the retained photoresist and the height of the low-temperature oxide layer is formed on the low-temperature oxide layer; fifthly, part of the height of the first dielectric layer and residual height from the low-temperature oxide layer on the retained photoresist to the first dielectric layer are removed so as to be flush with the retained photoresist; sixthly, the retained photoresist is removed so as to form grooves in the first dielectric layer; and finally, a conductive material is filled in the grooves and the superfluous conductive material outside the grooves is removed. By the adoption of the metal interconnection structure manufacturing method, uniformity of line width of a chip will be improved greatly.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of manufacture method of metal interconnect structure.
Background technology
Metal interconnect structure is the indispensable structure of semiconductor device.In semiconductor fabrication, the quality of the metal interconnect structure of formation has a significant impact performance and the semiconductor manufacturing cost of semiconductor device.
The manufacture method of existing metal interconnect structure, power mos transistor device for example, generally comprise: dielectric layer on active area structure at first, form afterwards contact hole pattern within it, then in contact hole, insert metal and form conductive plunger, form the upper strata dielectric layer after planarization on this conductive plunger and dielectric layer, adopt afterwards photoetching process to define the photoresist of strip region on the dielectric layer of upper strata, take subsequently this photoresist carries out the groove that etching is formed for forming metal interconnect structure as mask.
Yet, carry out define pattern with photoresistance exposure, with plasma, dielectric layer is carried out in the process of etching, often find that pattern that density the is different critical size after etching is can difference very large, this can directly have influence on being connected of interconnect architecture and anterior layer electric conductor.Also can there be the different problem of critical size in the identical pattern in the zone at center and edge.And these problems are carried out define pattern in existing having with photoresistance exposure, it is very formidable with plasma, dielectric layer being carried out in the technological process of etching.
In view of this, the present invention proposes a kind of manufacture method of new metal interconnect structure, to address the above problem.
Summary of the invention
The problem that the present invention solves is the manufacture method that proposes a kind of new metal interconnect structure, to solve the problem changed with pattern density and wafer position of living in of critical size after the metal interconnect structure etching that existing manufacture method forms.
For addressing the above problem, the invention provides a kind of manufacture method of metal interconnect structure, the method comprises:
Semiconductor substrate is provided, there is target on described Semiconductor substrate and be electrically connected to zone;
Form photoresist on described Semiconductor substrate, at least retain target after described photoresist is exposed, develops and be electrically connected to the photoresist on zone;
Deposit low temperature oxide layer on described Semiconductor substrate and photoresist;
Form the first dielectric layer on described low temperature oxide layer, the height of described the first dielectric layer is greater than the photoresist of described reservation and the height sum of low temperature oxide layer;
Low temperature oxide layer to residual altitude on described first dielectric layer of removal Partial Height and the photoresist of described reservation flushes with the photoresist of reservation;
Remove the photoresist of described reservation, in described the first dielectric layer, to form groove;
Insert conductive material and remove unnecessary conductive material outside described groove to form metal interconnect structure in described groove.
Alternatively, target electrical connection zone is the conductive plunger directly be electrically connected to transistorized source electrode, grid or drain electrode.
Alternatively, target electrical connection zone is the conductive plunger of anterior layer.
Alternatively, form photoresist on described Semiconductor substrate before, also on described Semiconductor substrate, form bottom anti-reflection layer.
Etch stop layer also is provided on the Semiconductor substrate provided alternatively; Before on described Semiconductor substrate, the formation bottom anti-reflection layer forms, the etch stop layer also described target is electrically connected on zone is removed.
Alternatively, the material of described etch stop layer is at least one in silicon dioxide, silicon nitride, silicon oxynitride, carborundum, carbonitride of silicium.
Alternatively, described low temperature oxide layer is to adopt atomic layer deposition method to form.
Alternatively, remove the described first dielectric layer employing dry etching of Partial Height.
Alternatively, the dielectric constant k scope of the material of described the first dielectric layer is 2.0<k<4.0.
Alternatively, the method of removing the photoresist of described reservation is that wet method is removed, the liquid adopted is PGME(propylene glycol monomethyl ester) or PGMEA(propylene glycol monomethyl ester acetate), or the mixed liquor of these two kinds of organic liquor.
Alternatively, the dielectric constant k scope of the material of described the first dielectric layer is 2.7<k<4.0, and the method for removing the photoresist of described reservation is dry etching, and adopting gas is oxygen base plasma.
Alternatively, the conductive material of inserting in described groove is at least one in copper, aluminium, tungsten, silver, gold.
Compared with prior art, the present invention has the following advantages:
Be different from and of the prior artly in dielectric layer, by dry etching, form metal interconnect structure, the present invention adopts the photoresist of patterning as core (core), form dielectric layer around the photoresist of described patterning, after removing afterwards described photoresist, this photoresist is according to the shape of pattern, can stay groove, afterwards in this groove the filled conductive material correspondingly to form metal interconnect structure.Because said method is more simpler than traditional Damascus technics, avoided take photoresistance as the etching process of mask to dielectric layer, thereby the difference between the pattern critical size of definition after having avoided developing and critical size after etching has realized improving the uniformity of chip live width along with pattern density reaches the different and different problem of present position on wafer.
The accompanying drawing explanation
Fig. 1 is the manufacturing process flow chart of the metal interconnect structure in the embodiment of the present invention;
Fig. 2 to Figure 10 is the intermediate structure schematic diagram according to the metal interconnect structure of the formation of the manufacture method in Fig. 1;
Figure 11 is the final structure schematic diagram according to the metal interconnect structure of the formation of the manufacture method in Fig. 1.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.Because the present invention focuses on interpretation principle, therefore, drawing not in scale.
The manufacture method of the metal interconnect structure that the present invention proposes, the back-end process that belongs to semiconductor applications, thereby forming the upper strata metal interconnect structure be electrically connected to it on the conductive plunger that the present embodiment be take in the anterior layer of metal interconnect structure is example, introduces in detail manufacture method of the present invention.
At first in conjunction with the flow chart of Fig. 1, execution step S11, provide Semiconductor substrate, has target on described Semiconductor substrate and be electrically connected to zone, and wherein, it is the conductive plunger of anterior layer in metal interconnect structure that this target is electrically connected to zone.In other embodiment, it can be also the conductive plunger directly be electrically connected to transistorized source electrode, grid or drain electrode that this target is electrically connected to zone.
Shown in Figure 2, in the present embodiment, substrate can, for silicon, germanium or SiGe etc., be formed with multiple active, passive device on it.Active device is for example planar transistor MOS, and its structure comprises on the channel region between source electrode, drain electrode, source electrode and drain electrode and is formed with successively gate insulator, grid.In other embodiment, this MOS transistor can be also groove type MOS transistor (Trench MOS).Can also be formed with metal silicide on the source electrode of MOS transistor, drain electrode, grid to reduce contact resistance.
In most of situation, active, passive device need form and be electrically connected to other device or control circuit through multilevel metal interconnection structure, to realize function separately.For example, MOS transistor is connected with bit line, word line etc. by 8 layers of metal interconnect structure, between 8 layers of metal interconnect structure, particularly, between MOS transistor and first layer metal pattern (Metal 1), (Metal 1 for each layer of metal pattern, Metal 2 ...) between by conductive plunger realize the interconnection.Continuation is with reference to shown in Fig. 3, and the target that conductive plunger 31 is the present embodiment is electrically connected to zone, and this conductive plunger 31 is formed in interlayer dielectric layer 30, with anterior layer metal pattern (not shown), be connected, thereby, also claim the conductive plunger 31 of anterior layer; The Semiconductor substrate that the substrate of the conductive plunger 31 that comprises anterior layer is the present embodiment.In other embodiment, with various active, conductive plungers that passive device directly is connected, the conductive plunger for example directly be connected with source electrode, drain electrode, the grid of MOS transistor also is electrically connected to zone for target of the present invention, and comprising with various conductive plungers active, that passive device directly is connected is Semiconductor substrate of the present invention.
Then perform step S12, as shown in Figure 3, described, comprise conductive plunger 31 and this conductive plunger 31 carried out on the Semiconductor substrate of interlayer dielectric layer 30 of electric insulation, form etch stop layer 32(Etch Stop Layer, ESL).The zone that this etch stop layer 32 is not opened, play the effect of being insulated in the zone under it.
In specific implementation process, the material of described etch stop layer 32 is at least one in silicon dioxide, silicon nitride, silicon oxynitride, carborundum, carbonitride of silicium.
This step is inessential step.
Then perform step S13, remove described target and be electrically connected to the etch stop layer on zone.
In the present embodiment, it is conductive plunger 31 that target is electrically connected to zone, and the method for removing the etch stop layer 32 on it is photoetching, etching.Non-target is electrically connected to zone, and the residual photoresist on interlayer dielectric layer 30 adopts wet method or ashing method to remove.After this step is finished, the structural section figure of formation as shown in Figure 4.
This step is inessential step.
Then perform step S14, on described Semiconductor substrate, form bottom anti-reflection layer.
The bottom anti-reflection layer 33 of this step is formed on etch stop layer 32 and reaches on the conductive plunger 31 exposed.After this step is finished, the structural section figure of formation as shown in Figure 5.
This step is inessential step.
Execution step S15 forms photoresist on bottom anti-reflection layer 33, at least retains target after described photoresist is exposed, develops and is electrically connected to the photoresist on zone.
As above give an account of and continue, form photoresist on bottom anti-reflection layer 33, after utilizing the mask plate exposure, after development, by using plasma etching that unnecessary bottom reflector is removed, form the photoresist 34 of patterning, the corresponding upper strata of photoresist 34 metal pattern of this patterning, for between upper and lower metal pattern, forming and be electrically connected to, thereby at least need to retain the photoresist 34 on conductive plunger 31.Photoresist in this step can be selected positive photoresist, also can select negative photoresist, and the concrete required technique of exposure imaging process, for existing technique, does not repeat them here.
In other embodiments, if without etch stop layer 32, bottom anti-reflection layer 33 directly forms photoresist on conductive plunger 31 and this conductive plunger 31 carry out the interlayer dielectric layer 30 of electric insulation.
In the present invention, the photoresist 34 of this reservation, the photoresist that also claims patterning, purpose is the position that occupies metal interconnection pattern in subsequent dielectric layer, therefore, in this step, the pattern of the photoresist 34 of this reservation is the upper strata metal pattern, the bottom in photoresist 34 at least part of zones of this reservation is dropped on the target electricity fully and is electrically connected to zone above, in the present embodiment, is on conductive plunger 31.Shown in Fig. 6, the photoresist 34 that has retained two zones, one of them corresponding conductive plunger 31, another removes rear purpose for forming metal pattern, this another photoresist 34 is not connected with the anterior layer conductive plunger, or be electrically connected to zone with the target of corresponding another section and be connected, for example with other conductive plunger of anterior layer, be connected.In addition, do not need the bottom anti-reflection layer 33 that retains the photoresist zone substantially to be consumed in this step, if residual bottom anti-reflection layer is arranged, removed, method is for example dry etching.
Then perform step S16, shown in Fig. 7, deposition low temperature oxide layer 35 on the photoresist 34 of etch stop layer 32 and described reservation.
In this step, this low temperature oxide layer 35(low temperature oxide, LTO) cover photoetching agent pattern 34, can avoid follow-up while needing hot conditions to form the first dielectric layer, to the infringement of photoetching agent pattern 34, cause its distortion.The material of this low temperature oxide is for example with the interior low temperature oxide generated by atomic layer deposition method (ALD) at 100 degrees centigrade.
Perform step afterwards S17, shown in Fig. 8, form the first dielectric layer 36 on low temperature oxide layer 35, the photoresist 34 that the height of described the first dielectric layer 36 is greater than described reservation with its on both height sums of low temperature oxide layer 35.
The material of the first dielectric layer 36 can be the silicon dioxide of dielectric constant 2.7<k<4.0, be to reduce parasitic capacitance, also can be for dielectric constant the ultralow K dielectric material between 2.0-2.7.
Then, execution step S18, shown in Fig. 9, the low temperature oxide layer 35 on described first dielectric layer 36 of removal Partial Height and the photoresist 34 of described reservation to the residual altitude of described the first dielectric layer 36 flushes with the photoresist 34 of reservation.
This step adopts the removal that also is etched of dry etching, the low temperature oxide layer 35 on the photoresist 34 of reservation, and etching gas is fluoro-gas, for example CF
4, C
4f
8deng.This step also can adopt cmp (CMP).
After step S15 is finished, the photoresist 34 of reservation protrudes from Semiconductor substrate, and the purpose of step S17 and step S18 is the zone that adopts the first dielectric layer 36 to fill outside the photoresist 34 retained.
In other embodiment, if without etch stop layer 32, conductive plunger 31, this conductive plunger 31 carry out the interlayer dielectric layer 30 of electric insulation and the photoresist 34 that retains on form the first dielectric layer 36, remove afterwards Partial Height concordant to the height of the photoresist 34 with described reservation.
Afterwards, execution step S19, remove the photoresist 34 of described reservation, at the interior formation groove of described the first dielectric layer 36, to expose target, to be electrically connected to zone.
Shown in Figure 10, while removing the photoresist 34 of described reservation, the bottom anti-reflection layer 33 under it is also removed simultaneously.In addition, in this removal process, need to consider material or the dielectric constant of the first dielectric layer, for example, in step S17, the dielectric constant k scope of the material of described the first dielectric layer 36 is 2.0<k<4.0, remove described reservation photoresist 34 and under the method for bottom anti-reflection layer 33 be that wet method is removed, the liquid adopted is PGME(propylene glycol monomethyl ester) or PGMEA(propylene glycol monomethyl ester acetate), or the arbitrary proportion mixed liquor of these two kinds of organic liquor.It should be noted that, the dielectric constant k scope of the material of the first dielectric layer 36 is 2.7<k<4.0 o'clock, remove described reservation photoresist 34 and under the method for bottom anti-reflection layer 33 can also be dry etching, adopting gas is oxygen base plasma, for example oxygen, carbon dioxide or carbon monoxide.
The corresponding metal interconnection pattern formed that needs of photoresist 34 due to this patterning, thereby, after this step is finished, the zone that the photoresist 34 before be patterned occupies is exposed the formation groove, this groove at least exposes target and is electrically connected to zone, and in the present embodiment, a groove exposes conductive plunger 31, another groove is metal pattern or is electrically connected to regional being connected with the target of another section, for example is connected with the conductive plunger of another section.
Finally perform step S20, shown in Figure 11, insert conductive material 37 and remove unnecessary conductive material 37 outside described groove to form metal interconnect structure in described groove.
In the process of implementation, the conductive material 37 of inserting in groove can be for realizing the material of conducting function for this step, at least one in copper, aluminium, tungsten, silver, gold for example, but be not limited to above-mentioned material.Remove the outer conductive material 37 of groove and can adopt CMP or method for etching plasma.
Through above-mentioned steps, formed a kind of new metal interconnect structure.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible change and modification to technical solution of the present invention; therefore; every content that does not break away from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.
Claims (12)
1. the manufacture method of a metal interconnect structure, is characterized in that, comprising:
Semiconductor substrate is provided, there is target on described Semiconductor substrate and be electrically connected to zone;
Form photoresist on described Semiconductor substrate, at least retain target after described photoresist is exposed, develops and be electrically connected to the photoresist on zone;
Deposit low temperature oxide layer on the photoresist of described Semiconductor substrate and reservation;
Form the first dielectric layer on described low temperature oxide layer, the height of described the first dielectric layer is greater than the photoresist of described reservation and the height sum of low temperature oxide layer;
Low temperature oxide layer on described first dielectric layer of removal Partial Height and the photoresist of described reservation to the residual altitude of described the first dielectric layer flushes with the photoresist of reservation;
Remove the photoresist of described reservation, in described the first dielectric layer, to form groove;
Insert conductive material and remove unnecessary conductive material outside described groove to form metal interconnect structure in described groove.
2. manufacture method according to claim 1, is characterized in that, described target is electrically connected to zone and is and transistorized source electrode, grid or the electric direct-connected conductive plunger that drains.
3. manufacture method according to claim 1, is characterized in that, it is the conductive plunger of anterior layer that described target is electrically connected to zone.
4. manufacture method according to claim 1, is characterized in that, form photoresist on described Semiconductor substrate before, also on described Semiconductor substrate, forms bottom anti-reflection layer.
5. manufacture method according to claim 4, is characterized in that, etch stop layer also is provided on the Semiconductor substrate provided; Form bottom anti-reflection layer on described Semiconductor substrate before, the etch stop layer also described target is electrically connected on zone is removed.
6. manufacture method according to claim 5, is characterized in that, the material of described etch stop layer is at least one in silicon dioxide, silicon nitride, silicon oxynitride, carborundum, carbonitride of silicium.
7. manufacture method according to claim 1, is characterized in that, described low temperature oxide layer is to adopt atomic layer deposition method to form.
8. manufacture method according to claim 1, is characterized in that, described the first dielectric layer of removing Partial Height adopts dry etching.
9. manufacture method according to claim 1, is characterized in that, the dielectric constant k scope of the material of described the first dielectric layer is 2.0<k<4.0.
10. manufacture method according to claim 9, is characterized in that, the method for removing the photoresist of described reservation is that wet method is removed, and the liquid of employing is PGME or PGMEA, or the mixed liquor of these two kinds of organic liquor.
11. manufacture method according to claim 1, is characterized in that, the dielectric constant k scope of the material of described the first dielectric layer is 2.7<k<4.0, and the method for removing the photoresist of described reservation is dry etching, and adopting gas is oxygen base plasma.
12. manufacture method according to claim 1, is characterized in that, the conductive material of inserting in described groove be in copper, aluminium, tungsten, silver, gold in a kind of or the combination.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108417528A (en) * | 2018-02-05 | 2018-08-17 | 武汉新芯集成电路制造有限公司 | A method of improving residue on aluminium pad |
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| CN101416278A (en) * | 2006-04-07 | 2009-04-22 | 美光科技公司 | Simplified technological process for doubling range interval |
| US20090263970A1 (en) * | 2004-06-22 | 2009-10-22 | Keun-Hee Bai | Method of forming fine pattern of semiconductor device using sige layer as sacrificial layer, and method of forming self-aligned contacts using the same |
| CN102169825A (en) * | 2010-02-12 | 2011-08-31 | 三星电子株式会社 | Method of forming fine patterns of semiconductor device |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090263970A1 (en) * | 2004-06-22 | 2009-10-22 | Keun-Hee Bai | Method of forming fine pattern of semiconductor device using sige layer as sacrificial layer, and method of forming self-aligned contacts using the same |
| CN101416278A (en) * | 2006-04-07 | 2009-04-22 | 美光科技公司 | Simplified technological process for doubling range interval |
| CN102169825A (en) * | 2010-02-12 | 2011-08-31 | 三星电子株式会社 | Method of forming fine patterns of semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108417528A (en) * | 2018-02-05 | 2018-08-17 | 武汉新芯集成电路制造有限公司 | A method of improving residue on aluminium pad |
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