CN102420134B

CN102420134B - Manufacturing method of super-junction combined punch-through type groove IGBT (Insulated Gate Bipolar Transistor) device

Info

Publication number: CN102420134B
Application number: CN 201110383157
Authority: CN
Inventors: 王海军
Original assignee: Shanghai Hua Hong NEC Electronics Co Ltd
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2011-11-25
Filing date: 2011-11-25
Publication date: 2013-09-11
Anticipated expiration: 2031-11-25
Also published as: CN102420134A

Abstract

The invention discloses a manufacturing method of a super-junction combined punch-through type groove IGBT (Insulated Gate Bipolar Transistor) device; the manufacturing method comprises the following steps of: growing a first layer of N type epitaxy with the concentration from thickness to thinness on a P type heavy doping substrate; then growing a second layer of N type epitaxy; exposing graphs on the front surface of a silicon wafer, and etching a P column; etching to form grooves; growing an epitaxy with high doping boron on holes or the grooves; grinding the epitaxies till reaching the surface of a monocrystal silicon; carrying out exposure definition on a groove gate; growing a doping N type polycrystalline silicon; etching the polycrystalline silicon; carrying out injection and drive-in of sources and P-wells on the front surface; carrying out silicon wafer reduction on the back surface; and evaporating gold of a collector. According to the manufacturing method, the effects of withstanding voltage and further reducing the specific on-resistance through the exhaustion of the P column and the N type substrate are achieved so that current density is denser, the resistance and the Joule heating in the on-state are reduced, and the turn-off response speed is faster.

Description

Combining super knot punch trench IGBT device making method

Technical field

The invention belongs to method, semi-conductor device manufacturing method.

Background technology

IGBT (Insulated Gate Bipolar Transistor) insulated gate bipolar transistor, by the compound full-control type voltage driven type power semiconductor that BJT (double pole triode) and MOS (insulating gate type field effect tube) form, have the advantage of low conduction voltage drop two aspects of the high input impedance of MOSFET and GTR concurrently.The GTR saturation pressure reduces, and current carrying density is big, but drive current is bigger; The MOSFET driving power is very little, and switching speed is fast, but conduction voltage drop is big, and current carrying density is little.Insulated gate bipolar transistor IGBT combines the advantage of above two kinds of devices, and the little and saturation pressure of driving power reduces.Be fit to very much to be applied to direct voltage and be fields such as 600V and above converter system such as alternating current machine, frequency converter, Switching Power Supply, lighting circuit, traction transmission.

Withstand voltage enough in order to guarantee, will increase the thickness of substrate between N-type MOS structure and the bottom collector electrode as far as possible, just the base thickness of PNP triode is thicker.Though withstand voltage much of that, base resistance is higher, Joule heat can be bigger during on-state, and on state voltage is bigger during work.

Summary of the invention

Technical problem to be solved by this invention provides a kind of combining super knot punch trench IGBT device making method, and it can be so that current density be bigger, and the resistance when reducing on-state and Joule heat make that turn-off response speed is faster.

In order to solve above technical problem, the invention provides a kind of combining super knot punch trench IGBT device making method, may further comprise the steps: on the heavily doped substrate of P type growth concentration by dense to light ground floor N-type extension; And then the N-type extension for the second time of growing up; Silicon chip face exposure figure carries out the etching of P post; Carry out etching and form groove; To the grow up extension of highly doped boron of hole or groove; Carry out the grinding of extension, be ground to the surface of monocrystalline silicon; Carry out the exposure definition of trench gate; Growth doped N-type polysilicon; The polycrystalline grid are carried out etching; The front is carried out the injection of source and P trap and is pushed away trap; Wafer thinning is carried out at the back side; Carry out the steaming gold of collector electrode.

Beneficial effect of the present invention is: reach the withstand voltage and further effect that reduces conduction resistance by exhausting of P post and N-type substrate, make current density bigger, the resistance when having reduced on-state and Joule heat make that turn-off response speed is faster.

Ground floor N-type extension phosphonium ion bulk concentration reduces to 1E13 gradually from 1E17.

N-type extension for the second time, the phosphonium ion bulk concentration is from 1E15 to 1E13.

The figure of silicon chip face exposure micron more than 0.5 carries out the etching of P post.

Etching forms groove dark more than 5 microns.

To the grow up extension of highly doped boron of hole or groove, bulk concentration is more than 1E15.

Growth doped N-type polysilicon, thickness is greater than 500 dusts.

Wafer thinning is carried out at the back side, is thinned to more than 50 microns.

Carry out the steaming gold of collector electrode, the thickness of metal is more than 1 micron.

Description of drawings

Below in conjunction with the drawings and specific embodiments the present invention is described in further detail.

Fig. 1 is the schematic diagram of growth N-type extension from the heavily doped P type substrate;

Fig. 2 is continue the to grow up schematic diagram of lighter extension of basis in the extension first time;

Fig. 3 is the schematic diagram that reaches the groove more than 5 microns from positive etching deeply;

Fig. 4 is the highly doped extension of growing up in the groove of front, grinds then, forms the schematic diagram of P post;

Fig. 5 is the etching of carrying out trench gate, the schematic diagram of the formation of growth polysilicon gate and positive source and P trap;

Fig. 6 carries out the schematic diagram that thinning back side grinds;

Fig. 7 carries out the back side to steam gold, makees the schematic diagram that collector electrode is drawn.

Embodiment

The device architecture that a kind of combining super is tied 8 inches of groove-shaped break-through IGBT has been introduced in invention, do the theoretical super junction N-type groove type MOS structure of supporting of you MOS of outbound in the front of device, reach the effect of withstand voltage and further reduction conduction resistance by exhausting of P post and N-type substrate, make current density bigger, resistance when having reduced on-state and Joule heat make that turn-off response speed is faster.

Before doing positive technology and beginning, growth one deck N-type extension on heavily doped P type substrate, bulk concentration is more than 1E13, bulk concentration is shoaled by dense, and thickness is more than 1 micron, then in the extension of growth bulk concentration between 1E13-1E14, continue the above silicon dioxide of growth 3000 dusts as the barrier layer of etching, the figure of silicon chip face exposure micron more than 0.5 carries out the silicon dioxide etching then, removes photoresist after the etching.Carry out the etching of P type groove with silicon dioxide as the barrier layer then, the degree of depth at quarter washes silicon dioxide more than 5 microns, and the P type extension of growth boron-doping is carried out the grinding of P type extension.To the exposure definition of trench gate, carry out etching, the degree of depth is greater than more than 1 micron, and the N-type of growing up then polycrystalline carries out etching definition polycrystalline grid.Carry out the injection of positive source and trap, push away trap.Carry out the interconnected of metal then.After finishing positive technology, attenuate is carried out according to withstand voltage requirement in the back side, directly carry out the back side and steam gold back formation collector electrode.

By introducing Ku Er MOS concept, replace general metal-oxide-semiconductor again in conjunction with the PNP darlington structure with groove-shaped super junction, form band deep trench field cut-off type IGBT device architecture, this device architecture combines the advantage of super junction NMOS pipe and two kinds of structures of IGBT.Device is positive because super junction NMOS has replaced General N MOS, doing this class device selection substrate so just can be denseer than the substrate concentration of existing IGBT device, cost is lower, like this littler than the PNP base width of general IGBT, on state resistance is littler, and the Joule heat of generation is littler, bear under the equal withstand voltage prerequisite, during OFF state, the fall delay time is shorter, and the short circuit current that can bear is bigger.

The implementation method of the deep slot type IGBT device of combining super knot of the present invention.

1. the groove-shaped IGBT device architecture of combining super knot, the thickness of this silicon chip can be as thin as 50 microns.

2. as shown in Figure 1, the N-type extension is as cutoff layer for the first time in highly doped P type substrate growth, and bulk concentration is shoaled by dense, and every square centimeter of charge carrier number is reduced to 1E13 from 1E17, and thickness is more than 1 micron.

3. as shown in Figure 2, on the basis of the N-type extension first time, the extension for the second time of continue growing up, bulk concentration every square centimeter from 1E13 to 1E14 between.

4. the figure of silicon chip face exposure micron more than 0.5 carries out the etching of P post.

5. as shown in Figure 3, carry out etching and form groove dark more than 5 microns.

6. as shown in Figure 4, to the grow up extension of highly doped B of hole or groove, bulk concentration is more than 1E15.

7. carry out the grinding of extension, be ground to the surface of monocrystalline silicon.

8. carry out the exposure definition of trench gate.

9. growth doped N-type polycrystalline, thickness is greater than 500 dusts.

10. as shown in Figure 5, the polycrystalline grid are carried out etching.

11. the front is carried out the injection of source and P trap and is pushed away trap.

12. as shown in Figure 6, wafer thinning is carried out at the back side, is thinned to more than 50 microns.

13. as shown in Figure 7, carry out the steaming gold of collector electrode, the thickness of metal is more than 1 micron.

The present invention is not limited to execution mode discussed above.More than the description of embodiment is intended in order to describe and illustrate the technical scheme that the present invention relates to.Based on the apparent conversion of the present invention enlightenment or substitute and also should be considered to fall into protection scope of the present invention.Above embodiment is used for disclosing best implementation method of the present invention, so that those of ordinary skill in the art can use numerous embodiments of the present invention and multiple alternative reaches purpose of the present invention.

Claims

1. a combining super knot punch trench IGBT device making method is characterized in that, may further comprise the steps:

On the heavily doped substrate of P type growth concentration by dense to the light N-type extension first time;

And then the N-type extension for the second time of growing up;

Carry out etching and form groove;

Silicon chip face exposure figure forms the P post in groove;

To the grow up extension of highly doped boron of groove;

Carry out the grinding of extension, be ground to the surface of monocrystalline silicon;

Carry out the exposure definition of trench gate;

Growth doped N-type polysilicon;

Etch polysilicon gate;

The front is carried out the injection of source and P trap and is pushed away trap;

Wafer thinning is carried out at the back side;

Carry out the steaming gold of collector electrode.

2. combining super knot punch trench IGBT device making method as claimed in claim 1 is characterized in that N-type extension phosphonium ion bulk concentration reduces to 1E13 gradually from 1E17 for the first time.

3. combining super as claimed in claim 1 knot punch trench IGBT device making method is characterized in that, N-type extension for the second time, and the phosphonium ion bulk concentration is from 1E15 to 1E13.

4. combining super as claimed in claim 1 knot punch trench IGBT device making method is characterized in that, the figure of silicon chip face exposure 0.5 or more micron carries out the etching of P post.

5. combining super knot punch trench IGBT device making method as claimed in claim 1 is characterized in that etching forms groove dark more than 5 microns.

6. combining super as claimed in claim 1 knot punch trench IGBT device making method is characterized in that, to the grow up extension of highly doped boron of hole or groove, bulk concentration is more than 1E15.

7. combining super knot punch trench IGBT device making method as claimed in claim 1 is characterized in that, growth doped N-type polysilicon, and thickness is greater than 500A.

8. combining super knot punch trench IGBT device making method as claimed in claim 1 is characterized in that wafer thinning is carried out at the back side, is thinned to more than 50 microns.

9. combining super knot punch trench IGBT device making method as claimed in claim 1 is characterized in that carry out the steaming gold of collector electrode, the thickness of metal is more than 1 micron.