CN102412304A - An Inverse Scale or Small Scale NMOS Tube Layout Structure Against Total Dose Radiation Effect - Google Patents

An Inverse Scale or Small Scale NMOS Tube Layout Structure Against Total Dose Radiation Effect Download PDF

Info

Publication number
CN102412304A
CN102412304A CN2011103447066A CN201110344706A CN102412304A CN 102412304 A CN102412304 A CN 102412304A CN 2011103447066 A CN2011103447066 A CN 2011103447066A CN 201110344706 A CN201110344706 A CN 201110344706A CN 102412304 A CN102412304 A CN 102412304A
Authority
CN
China
Prior art keywords
gate
source
drain terminal
active region
guard ring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2011103447066A
Other languages
Chinese (zh)
Other versions
CN102412304B (en
Inventor
罗静
徐睿
邹文英
薛忠杰
周昕杰
胡永强
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CETC 58 Research Institute
Original Assignee
CETC 58 Research Institute
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CETC 58 Research Institute filed Critical CETC 58 Research Institute
Priority to CN2011103447066A priority Critical patent/CN102412304B/en
Publication of CN102412304A publication Critical patent/CN102412304A/en
Application granted granted Critical
Publication of CN102412304B publication Critical patent/CN102412304B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention relates to an inverse proportion or small proportion NMOS tube layout structure for resisting total dose radiation effect, which comprises a semiconductor substrate and an active region; depositing a polycrystalline grid in an active region of the semiconductor substrate, respectively arranging a source end injection protection ring and a drain end injection protection ring in two ends of the polycrystalline grid correspondingly deposited in the active region, and respectively forming a source end and a drain end in the source end injection protection ring and the drain end injection protection ring through ion injection; the source end and the drain end are both surrounded by the polycrystalline grid, and the source end and the drain end are isolated through the polycrystalline grid. The invention completely eliminates the problems of electric leakage and isolation failure caused by field oxygen induced inversion under radiation conditions; meanwhile, the edge parasitic transistor which is very sensitive to the total dose effect does not exist on the boundary of the polycrystalline grid crossing the field oxide region, so that the purpose of reinforcing the total dose is achieved; the NMOS tube can be reinforced in inverse proportion or small proportion, which is difficult to realize by the traditional annular gate, the structure is simple, the NMOS tube is compatible with commercial process, the occupied area is small, and the layout wiring is more convenient and flexible.

Description

A kind of inverse ratio of anti-integral dose radiation effect or small scale NMOS pipe domain structure
Technical field
The present invention relates to a kind of metal-oxide-semiconductor domain structure, especially a kind of inverse ratio of anti-integral dose radiation effect or small scale NMOS manage domain structure, belong to the technical field of metal-oxide-semiconductor domain.
Background technology
When device continues to receive ionising radiation (like X ray, gamma-rays etc.), can produce the integral dose radiation effect.For the NMOS pipe, the silica dioxide medium layer of one deck 50~200 nanometers is all arranged between grid and substrate, under radiation condition, ionization produces the electron-hole pair of some in silica dioxide medium.When on grid, adding forward bias, the electronics major part that mobility is bigger is spilled over to grid, and some electronics and hole be to compound, most of hole under the effect of positive electric field to SiO 2/ Si interface transportation, and some is by SiO at the interface 2The defective of one side is captured, and forms interfacial state.Such positive charge accumulation can cause the drift of device threshold voltage, finally influences the performance of device.
Secondly; The transistor that adopts self-registered technology to make; Polysilicon gate is deposited on the thin oxide layer, and source/leakage is injected by the active area that is not covered by polysilicon and formed, and the circuit closeness that this technology produces is high; But make polysilicon gate oxygen on the scene and thin gate oxide transition region produce a parasitic transistor, this parasitic transistor is very responsive to total dose effect.Because an oxygen and thin gate oxide are under radiation condition, meeting ionization electron-hole is right; Because the effect of capturing of trap is piled up positive charge in the SiO2 of Si/SiO2 system one side, forms interfacial state; Badly influence transistorized I-V characteristic; Along with the increase of radiation dose, edge parasitic transistor leakage current also rises rapidly, when leakage current is increased to the ON state current near intrinsic transistor; Transistor can forever be opened, and causes component failure.
At last, total dose effect also can make an oxygen isolated failure.Field oxygen is used for adjacent transistor and isolates, but because total dose effect can ionization produce electron-hole pair in the oxygen on the scene; Because the effect of capturing of trap is piled up positive charge in the SiO2 of Si/SiO2 system one side, thereby the electric leakage structure that forms transoid under the oxygen causes an oxygen to lose isolation features, finally cause circuit function to lose efficacy.
Along with constantly reducing of process, the thickness of gate oxide constantly reduces, and when gate oxide thickness was lower than 60 dusts, total dose effect can be ignored the influence of NMOS pipe threshold voltage.But parasitic transistor electric leakage in edge does not but improve with an oxygen district electric leakage.
In commercial application because parasitic transistor can not conducting, so commercial process without CONSIDERING EDGE parasitic transistor characteristic, this makes that the edge parasitic transistor of commercial device way is very responsive to the integral dose radiation effect.Because the commodity production line is not taked any radiation hardened measure on technology,, need make amendment to the transistor domain therefore in order to reach radiation-resistant purpose.
The NMOS of international popular pipe total dose radiation hardening way is to adopt annular grid structure to realize at present.Annular grid structure has been eliminated the show up transition region of oxygen of gate oxide fully between source/drain region; Eliminated the edge parasitic transistor; Adopt the adjacent NMOS pipe of this structure can a shared source region simultaneously, eliminated an oxygen and isolated an electric leakage problem that causes, and compatible with commercial process.But because the structural limitations of ring-shaped gate, the breadth length ratio that only is fit to the NMOS pipe is at least in the unit more than 4: 1.And the very little NMOS pipe of breadth length ratio utilizes the ring-shaped gate domain structure to realize, is enclosed in the middle of the ring-shaped gate owing to the NMOS drain terminal in addition, and is very limited on the domain wires design.So the application of the reinforced layout structure of ring-shaped gate in radiation-hardened ic is restricted.
Summary of the invention
The objective of the invention is to overcome the deficiency that exists in the prior art, a kind of inverse ratio or small scale NMOS pipe domain structure of anti-integral dose radiation effect is provided, its compact conformation, area occupied is little, and with existing process compatible, wiring is flexibly, and is safe and reliable.
According to technical scheme provided by the invention, a kind of inverse ratio NMOS of anti-integral dose radiation effect manages domain structure, comprises semiconductor substrate and is positioned at the active area on the said semiconductor substrate; Be deposited with the polycrystalline grid in the active area of said semiconductor substrate; The source end is set respectively in the two ends of corresponding deposit formation polycrystalline grid in the said active area injects guard ring and drain terminal injection guard ring, inject in the guard ring through ion injection formation respectively source end and drain terminal at said source end injection guard ring and drain terminal; Said source end and drain terminal are all surrounded by the polycrystalline grid, and leave through the polycrystalline barrier between source end and drain terminal.
Said polycrystalline grid are bar shaped, and an end of polycrystalline grid is provided with the grid exit, and said grid exit is extended with outside the source region, and the grid exit is provided with the grid contact hole corresponding to the other end that links to each other with the polycrystalline grid.
End in contact hole, source is set in the end of said source.The drain terminal contact hole is set in the said drain terminal.The injection guard ring is set in the said active area, and said injection guard ring is coated with the end edge of polycrystalline grid in source region and the said active area, and injects the outer ring that the guard ring extended loop lays out active area; The substrate electric potential contact hole is set in the active area.
A kind of small scale NMOS pipe domain structure of anti-integral dose radiation effect comprises semiconductor substrate and is positioned at the active area on the said semiconductor substrate; Be deposited with the polycrystalline grid in the active area of said semiconductor substrate; The source end is set respectively in the polycrystalline grid that the corresponding deposit of said active area forms injects guard ring and drain terminal injection guard ring; Inject in the guard ring through ion injection formation respectively source end and drain terminal at the source of active area end injection guard ring and drain terminal; Said source end and drain terminal are all surrounded by the polycrystalline grid in the active area, and leave through the polycrystalline barrier between source end and drain terminal.
Said polycrystalline grid are square, and said source end and drain terminal are symmetrically distributed in the both sides of polycrystalline grid; The grid exit is set on the polycrystalline grid, and said grid exit extends outside the active area from the polycrystalline grid, and the end that grid exit correspondence is extended outside the active area is provided with the grid contact hole.
End in contact hole, source is set in the end of said source.The drain terminal contact hole is set in the said drain terminal.The injection guard ring is set in the said active area, and said injection guard ring is coated with the end edge of polycrystalline grid in source region and the said active area, and injects the outer ring that the guard ring extended loop lays out active area; The substrate electric potential contact hole is set in the active area.
Advantage of the present invention: changed the isolation method of this type of NMOS pipe source end and drain terminal, making does not have an oxygen district existence between source end and the drain terminal, has eliminated electric leakage and isolated failure problem that radiation condition end oxygen is inducted and caused after the transoid fully; The border in the oxygen district of polycrystalline grid leap simultaneously no longer exists the highstrung edge of total dose effect parasitic transistor, has reached the purpose of total dose radiation hardening; Inverse ratio and small scale NMOS pipe belong to the weak pipe of MOS device, and be very responsive to the device breadth length ratio, and the breadth length ratio design has imbalance slightly, and device function just maybe be undesired; The present invention is the P-area through what form between N+ injection protection zone and the P+ injection guard ring; Not influenced by total dose effect; Therefore the conduction region that falls when doing than the plumber can not change under radiation condition, does not reinforce the breadth length ratio of NMOS plumber when doing thereby can not influence this type of; Can realize inverse ratio or small scale reinforcing NMOS pipe that the traditional endless grid are difficult to realize; Simple in structure; With commercial process compatible, area occupied is little, is easy to realize flexibly the reinforcing NMOS pipe of all kinds of inverse ratios and small scale; Can guarantee to reinforce the NMOS breadth length ratio and under radiation condition, can not change, and the domain wiring is also more convenient and flexible.
Description of drawings
The edge parasitic transistor that Fig. 1 causes for conventional NMOS pipe total dose effect vertical sketch map that leaks electricity.
Fig. 2 adopts the traditional endless gate layout structure to realize the NMOS duct ligation fruit sketch map of reinforcing.
Fig. 3 realizes the inverse ratio NMOS tubular construction sketch map reinforced for the present invention.
Fig. 4 realizes the small scale NMOS tubular construction sketch map reinforced for the present invention.
Fig. 5~Fig. 8 forms the step sketch map for inverse ratio NMOS tubular construction of the present invention, wherein:
Fig. 5 is the structural representation that is formed with behind the source region.
Fig. 6 is the structural representation behind the formation polycrystalline grid.
Fig. 7 is the structural representation behind formation source end and the drain terminal.
Fig. 8 is the structural representation after guard ring is injected in formation.
Description of reference numerals: 1-active area, 2-polycrystalline grid, 3-source end, 4-grid contact hole, 5-inject the source end of guard ring, 6-boundary line, 7-annular polysilicon gate, 8-contact hole, 9-NMOS pipe, drain terminal, 15-drain terminal, end in contact hole, 16-source, 17-substrate electric potential contact hole, 18-drain terminal contact hole and the 19-grid exit of 10-NMOS pipe.
Embodiment
Below in conjunction with concrete accompanying drawing and embodiment the present invention is described further.
As shown in Figure 1: as to be the conventional NMOS pipe that adopts self-registered technology to make; Polysilicon gate is deposited on the thin oxide layer; Source/leakage is to be injected by the active area that is not covered by polysilicon to form; The circuit closeness that this technology produces is high, but makes polysilicon gate produce a parasitic transistor in a gate oxide and an oxygen transition region, and this parasitic transistor is very responsive to total dose effect.Because an oxygen and gate oxide under radiation condition, can ionization produce electron-hole pair; Because the effect of capturing of trap is piled up positive charge in silicon dioxide one side of silicon/silicon dioxide system, forms interfacial state, badly influences transistorized electric current and voltage characteristic.Along with the increase of radiation dose, edge parasitic transistor leakage current also rises rapidly, and when leakage current was increased to the ON state current near intrinsic transistor, transistor can forever be opened, and causes component failure; On the other hand, the field oxygen that the polycrystalline grid the are crossed over transoid of can under radiation condition, inducting directly causes the source region of NMOS pipe under the non operating state and drain region to form the path that leaks electricity.
As shown in Figure 2: as to be the NMOS pipe that adopts the traditional endless gate layout structure to reinforce.Wherein boundary line 6 area surrounded are the active area of NMOS pipe, and zone 9 is the source end of NMOS pipe, and active area 10 is the drain terminal of NMOS pipe, between zone 9 and active area 10, does not have an existence in oxygen district.So there is not the edge parasitic transistor, eliminate leak channel with this, reach the purpose of total dose radiation hardening.Zone 7 is the annular polysilicon gate of NMOS pipe.One side at annular polysilicon gate links to each other with metal through regional 8 contact holes, and in order to connect proper voltage, the voltage of control NMOS pipe grid is to reach the state of control NMOS pipe.In active area 10 drain terminals of NMOS pipe, also link to each other with metal wire, as this NMOS pipe output potential exit through regional 8 contact holes.
As shown in Figure 3: as to be the inverse ratio NMOS duct ligation composition that utilizes the present invention to reinforce.Some active areas 1 are set on the semiconductor substrate, and said active area 1 is the zone that forms the NMOS pipe; The material of semiconductor substrate comprises silicon.Deposit forms polycrystalline grid 2 in the active area 1 of semiconductor substrate, and said polycrystalline grid 2 are bar shaped, and polycrystalline grid 2 are the polysilicon gate of inverse ratio NMOS pipe.When forming polycrystalline grid 2; Respectively leave certain not deposit of zone polysilicon at the two ends of polycrystalline grid 2; Promptly the two ends of corresponding polycrystalline grid 2 are provided with source end injection guard ring and drain terminal injection guard ring respectively in active area 1; Said source end injects guard ring and drain terminal injects guard ring all by 2 encirclements of polycrystalline grid, and isolates through polycrystalline grid 2 between source end injection guard ring and drain terminal injection guard ring.End at polycrystalline grid 2; One end of said polycrystalline grid 2 is provided with grid exit 19; Said grid exit 19 extends outside the active area 1; Corresponding to the end of extending outside the active area 1 grid contact hole 4 is set at grid exit 19, is deposited with metal in the grid fairlead 4, through controlling the current potential of polycrystalline grid 2 behind the depositing metal in grid fairlead 4.Subsequently;, the source at polycrystalline grid 2 two ends end passes through to inject N type foreign ion in injecting guard ring and drain terminal injection guard ring; To form the source end 3 and the drain terminal 4 of NMOS pipe at the two ends of polycrystalline grid 2, said source end 3 and drain terminal 4 are all surrounded by polycrystalline grid 2, and source end 3 and drain terminal 4 are isolated through polycrystalline grid 2 simultaneously.After forming source end 3 and drain terminal 4, the outer ring of end 3 and drain terminal 4 forms N+ injection protection zone in the source, and said N+ injects the protection zone and covers contiguous polycrystalline grid 2.At last, on semiconductor substrate, inject the p type impurity ion, form and inject guard ring 5, as the substrate contact and the P+ guard ring of inverse ratio NMOS pipe; Said injection guard ring 5 is coated with source region 1, and is covered in the end edge of polycrystalline grid 2, and extends the outer ring of active area 1.
Corresponding to forming the zone of injecting guard ring 5 substrate electric potential contact hole 17 is set at active area 1, behind depositing metal in substrate electric potential contact hole 17, can introduces the substrate electric potential of inverse ratio metal-oxide-semiconductor.End in contact hole, source 16 is set in the source end 3, drain terminal contact hole 18 is set in the drain terminal 4,, thereby can form source end exit, the drain terminal exit of metal-oxide-semiconductor through depositing metal in end in contact hole, source 16 and end in contact hole 18, source.When the p type impurity ion is injected in end injection region and drain terminal injection region in the source, when forming injection guard ring 5, need inject N type foreign ion, can form the domain structure of PMOS pipe like this.The size 11 that identifies among the figure is injected the size that the guard ring territory covers polycrystalline grid 2 for P+; N+ when size 12 is formation source end 3 and drain terminal 4 injects the size that the guard ring territory covers polycrystalline grid 2; Size 13 is injected the size of guard ring territory and P+ injection guard ring territory two border spacings for N+; Size 14 is that end in contact hole, source 16 is big or small with the spacing of polycrystalline grid 2, and these 4 sizes are relevant with the applied manufacturing process of inverse ratio NMOS ruggedized construction.This structure is through the domain structure of ingenious design inverse ratio NMOS pipe; Changed the isolation method of inverse ratio NMOS pipe source end 3 with drain terminal 4; To make do not have an oxygen district to exist between source end 3 and the drain terminal 4, eliminated electric leakage and isolated failure problem that radiation condition end oxygen is inducted and caused after the transoid fully; The border in the oxygen district of polycrystalline grid 2 leaps simultaneously no longer exists the highstrung edge of total dose effect parasitic transistor, has reached the purpose of total dose radiation hardening.
As shown in Figure 4, be the small scale NMOS duct ligation composition that utilizes the present invention to reinforce.Similar with the inverse ratio reinforced layout structure, semiconductor substrate is provided with source region 1, and active area 1 is the zone that forms small scale NMOS pipe.Polycrystalline grid 2 are the polysilicon gate of small scale NMOS pipe, and said polycrystalline grid 2 are square.When forming polycrystalline grid 2, in polycrystalline grid 2, respectively leave certain not deposit of zone polysilicon, the end injection region, source and the drain terminal injection region of symmetrical distribution promptly is set in polycrystalline grid 2, end injection region, said source and drain terminal injection region are positioned at the both sides of polycrystalline grid 2; This zone forms the source/drain region of small scale NMOS pipe.Inject through in end injection region, the source of polycrystalline grid 2 and drain terminal injection region, carrying out N type foreign ion; To form the source end 3 and the drain terminal 4 of NMOS pipe; And in said source the outer ring of end 3 and drain terminal 4 forms N+ and injects the protection zone; Source end 3 and drain terminal 4 are all surrounded by the polycrystalline grid 2 of correspondence, and source end 3 and drain terminal 4 are isolated through polycrystalline grid 2.At polycrystalline grid 2 grid exit 19 is set; Said grid exit 19 extends outside the active area 1; And grid contact hole 4 is set in the end that said grid exit 19 extends outside the active area 1, through depositing metal in grid contact hole 4, can control the current potential of polycrystalline grid 2.
At last, on semiconductor substrate, inject the p type impurity ion, form and inject guard ring 5, as the substrate contact and the P+ guard ring of inverse ratio NMOS pipe; Said injection guard ring 5 is coated with source region 1, and is covered in the end edge of polycrystalline grid 2, and extends the outer ring of active area 1.
Corresponding to forming the zone of injecting guard ring 5 substrate electric potential contact hole 17 is set at active area 1, behind depositing metal in substrate electric potential contact hole 17, can introduces the substrate electric potential of inverse ratio metal-oxide-semiconductor.End in contact hole, source 16 is set in the source end 3, drain terminal contact hole 18 is set in the drain terminal 4,, thereby can form source end exit, the drain terminal exit of metal-oxide-semiconductor through depositing metal in end in contact hole, source 16 and end in contact hole 18, source.When the p type impurity ion is injected in end injection region and drain terminal injection region in the source, when forming injection guard ring 5, need inject N type foreign ion, can form the domain structure of PMOS pipe like this.The size 11 that identifies among the figure is injected the size that the guard ring territory covers polycrystalline grid 2 for P+; N+ when size 12 is formation source end 3 and drain terminal 4 injects the size that the guard ring territory covers polycrystalline grid 2; Size 13 is injected the size of guard ring territory and P+ injection guard ring territory two border spacings for N+; Size 14 is that end in contact hole, source 16 is big or small with the spacing of polycrystalline grid 2, and these 4 sizes are relevant with the applied manufacturing process of inverse ratio NMOS ruggedized construction.This structure is through the domain structure of ingenious design inverse ratio NMOS pipe; Changed the isolation method of inverse ratio NMOS pipe source end 3 with drain terminal 4; To make do not have an oxygen district to exist between source end 3 and the drain terminal 4, eliminated electric leakage and isolated failure problem that radiation condition end oxygen is inducted and caused after the transoid fully; The border in the oxygen district of polycrystalline grid 2 leaps simultaneously no longer exists the highstrung edge of total dose effect parasitic transistor, has reached the purpose of total dose radiation hardening.
Like Fig. 5~shown in Figure 8, be to adopt patent of the present invention to realize reinforcing the formation step of inverse ratio NMOS pipe.At first, setting is formed with source region 1 on semiconductor substrate, and said active area 1 is the active area 1 that forms inverse ratio NMOS pipe, and is as shown in Figure 5.As shown in Figure 6: deposit polysilicon on active area 1 forms polycrystalline grid 2; When forming polycrystalline grid 2, respectively leave certain not deposit of zone polysilicon at polysilicon gate 2 two ends, i.e. source end injection region and drain terminal injection region, this zone forms source/drain region that inverse ratio NMOS manages; End at polycrystalline grid 2 is provided with grid exit 19 on the polycrystalline grid 2, said grid exit 19 extends outside the active area 1.Then, on the end injection region, source at polycrystalline grid 2 two ends and drain terminal injection region, inject source end 3 and the drain terminal 4 that forms the NMOS pipe through N type foreign ion; At last, on active area 1, inject the p type impurity ion, as the substrate contact and the injection guard ring 5 of inverse ratio NMOS pipe; Said injection guard ring 5 covers the end edge and the corresponding grid exit 19 of polycrystalline grid 2.Grid contact hole 4 is set extending out on the grid exit 19 of active area 1; Link to each other with metal through grid contact hole 4; As inverse ratio NMOS pipe grid control of Electric potentials electrode, the end in contact hole, source 16 of inverse ratio NMOS pipe source/drain terminal and drain terminal contact hole 18 be through linking to each other with metal, is used in the source termination and goes into suitable potential or draw the output potential that inverse ratio NMOS manages at drain terminal; Inject in the guard ring 5 and link to each other the substrate electric potential of introducing inverse ratio metal-oxide-semiconductor through substrate electric potential contact hole 17 with metal; Through behind the above-mentioned processing step, can form the NMOS pipe domain structure of inverse ratio.In like manner, said small scale NMOS pipe domain structure can obtain equally.
Like Fig. 3~shown in Figure 8: a kind of inverse ratio of anti-integral dose radiation effect or small scale NMOS pipe domain structure; Domain structure through design inverse ratio or small scale NMOS pipe; Changed the isolation method of this type of NMOS pipe source end 3 with drain terminal 4; To make do not have an oxygen district to exist between source end 3 and the drain terminal 4, eliminated electric leakage and isolated failure problem that radiation condition end oxygen is inducted and caused after the transoid fully; The border in the oxygen district of polycrystalline grid 2 leaps simultaneously no longer exists the highstrung edge of total dose effect parasitic transistor, has reached the purpose of total dose radiation hardening.Inverse ratio and small scale NMOS pipe belong to the weak pipe of MOS device, and be very responsive to the device breadth length ratio, and the breadth length ratio design has imbalance slightly, and device function just maybe be undesired.What N+ of the present invention formed between injecting and injecting with P+ is the P-area, not influenced by total dose effect, and the conduction region that therefore falls when doing than the plumber can not change under radiation condition, thus the breadth length ratio can not influence this type of reinforcing NMOS plumber and do the time.
The present invention's advantage compared with prior art: this structure can realize inverse ratio or the small scale reinforcing NMOS pipe that the traditional endless grid are difficult to realize; Simple in structure; With commercial process compatible, area occupied is little, is easy to realize flexibly the reinforcing NMOS pipe of all kinds of inverse ratios and small scale; Can guarantee to reinforce the NMOS breadth length ratio and under radiation condition, can not change, and the domain wiring is also more convenient and flexible.Unaccomplished matter of the present invention belongs to techniques well known.

Claims (10)

1. 一种抗总剂量辐射效应的倒比例NMOS管版图结构,包括半导体基板及位于所述半导体基板上的有源区(1);其特征是:所述半导体基板的有源区(1)内淀积有多晶栅(2),所述有源区(1)内对应淀积形成多晶栅(2)的两端内分别设置源端注入保护环及漏端注入保护环,在所述源端注入保护环与漏端注入保护环内通过离子注入分别形成源端(3)及漏端(15);所述源端(3)及漏端(15)均被多晶栅(2)包围,且源端(3)与漏端(15)间通过多晶栅(2)隔离。 1. An inverse ratio NMOS tube layout structure resistant to total dose radiation effect, comprising a semiconductor substrate and an active region (1) located on the semiconductor substrate; characterized in that: the active region (1) of the semiconductor substrate A polycrystalline gate (2) is deposited inside, and a source implantation guard ring and a drain implantation guard ring are respectively provided at both ends of the polycrystalline gate (2) correspondingly deposited in the active region (1). The source terminal (3) and the drain terminal (15) are respectively formed by ion implantation into the guard ring and the drain terminal (15); the source terminal (3) and the drain terminal (15) are covered by the polycrystalline gate (2 ), and the source terminal (3) and the drain terminal (15) are isolated by a polycrystalline gate (2). 2.根据权利要求1所述的抗总剂量辐射效应的倒比例NMOS管版图结构,其特征是:所述多晶栅(2)呈条形,多晶栅(2)的一端设置栅极引出端(19),所述栅极引出端(19)延伸有源区(1)外,且栅极引出端(19)对应于与多晶栅(2)相连的另一端设置栅极接触孔(4)。 2. The inverse proportional NMOS transistor layout structure against total dose radiation effect according to claim 1, characterized in that: the polycrystalline gate (2) is strip-shaped, and one end of the polycrystalline gate (2) is provided with a gate lead-out end (19), the gate lead-out end (19) extends outside the active area (1), and the gate lead-out end (19) is provided with a gate contact hole corresponding to the other end connected to the polycrystalline gate (2) ( 4). 3.根据权利要求1所述的抗总剂量辐射效应的倒比例NMOS管版图结构,其特征是:所述源端(3)内设置源端接触孔(16)。 3. The inverse proportional NMOS tube layout structure resistant to total dose radiation effect according to claim 1, characterized in that: the source terminal (3) is provided with a source terminal contact hole (16). 4.根据权利要求1所述的抗总剂量辐射效应的倒比例NMOS管版图结构,其特征是:所述漏端(15)内设置漏端接触孔(18)。 4. The inverse proportional NMOS tube layout structure resistant to total dose radiation effect according to claim 1, characterized in that: the drain terminal (15) is provided with a drain terminal contact hole (18). 5.根据权利要求1所述的抗总剂量辐射效应的倒比例NMOS管版图结构,其特征是:所述有源区(1)内设置注入保护环(5),所述注入保护环(5)覆盖有源区(1)及所述有源区(1)内多晶栅(2)的端部边缘,且注入保护环(5)延伸环绕出有源区(1)的外圈;有源区(1)内设置衬底电位接触孔(17)。 5. The inverse proportional NMOS tube layout structure against total dose radiation effect according to claim 1, characterized in that: an injection guard ring (5) is set in the active region (1), and the injection guard ring (5 ) covers the active region (1) and the end edge of the polycrystalline gate (2) in the active region (1), and the injection guard ring (5) extends around the outer circle of the active region (1); A substrate potential contact hole (17) is arranged in the source region (1). 6.一种抗总剂量辐射效应的小比例NMOS管版图结构,包括半导体基板及位于所述半导体基板上的有源区(1);其特征是:所述半导体基板的有源区(1)内淀积有多晶栅(2),所述有源区(1)对应淀积形成的多晶栅(2)内分别设置源端注入保护环及漏端注入保护环,在有源区(1)的源端注入保护环与漏端注入保护环内通过离子注入分别形成源端(3)及漏端(15),所述源端(3)及漏端(15)均被有源区(1)内的多晶栅(2)包围,且源端(3)与漏端(15)间通过多晶栅(2)隔离。 6. A small-scale NMOS tube layout structure resistant to the effect of total dose radiation, including a semiconductor substrate and an active region (1) located on the semiconductor substrate; it is characterized in that: the active region (1) of the semiconductor substrate A polysilicon gate (2) is deposited inside, and the active region (1) is respectively provided with a source implantation guard ring and a drain implantation guard ring in the polysilicon gate (2) formed by deposition, and in the active area ( 1) The source terminal (3) and the drain terminal (15) are respectively formed by ion implantation into the guard ring and the drain terminal (15), and both the source terminal (3) and the drain terminal (15) are covered by the active region (1) is surrounded by a polycrystalline gate (2), and the source terminal (3) and the drain terminal (15) are isolated by the polycrystalline gate (2). 7.根据权利要求6所述的抗总剂量辐射效应的小比例NMOS管版图结构,其特征是:所述多晶栅(2)呈方形,所述源端(3)及漏端(15)对称分布于多晶栅(2)的两侧;多晶栅(2)上设置栅极引出端(19),所述栅极引出端(19)从多晶栅(2)上延伸出有源区(1)外,且栅极引出端(19)对应延伸出有源区(1)外的端部设置栅极接触孔(4)。 7. The small-scale NMOS transistor layout structure against total dose radiation effect according to claim 6, characterized in that: the polycrystalline gate (2) is square, and the source terminal (3) and drain terminal (15) symmetrically distributed on both sides of the polycrystalline gate (2); the gate terminal (19) is provided on the polycrystalline gate (2), and the gate terminal (19) extends from the polycrystalline gate (2) to an active A gate contact hole (4) is provided outside the area (1), and the gate terminal (19) correspondingly extends out of the active area (1). 8.根据权利要求6所述的抗总剂量辐射效应的小比例NMOS管版图结构,其特征是:所述源端(3)内设置源端接触孔(16)。 8 . The small-scale NMOS tube layout structure resistant to total dose radiation effect according to claim 6 , characterized in that: a source contact hole ( 16 ) is arranged in the source terminal ( 3 ). 9.根据权利要求6所述的抗总剂量辐射效应的小比例NMOS管版图结构,其特征是:所述漏端(15)内设置漏端接触孔(18)。 9. The small-scale NMOS tube layout structure resistant to total dose radiation effect according to claim 6, characterized in that: the drain terminal (15) is provided with a drain terminal contact hole (18). 10.根据权利要求6所述的抗总剂量辐射效应的倒比例NMOS管版图结构,其特征是:所述有源区(1)内设置注入保护环(5),所述注入保护环(5)覆盖有源区(1)及所述有源区(1)内多晶栅(2)的端部边缘,且注入保护环(5)延伸环绕出有源区(1)的外圈;有源区(1)内设置衬底电位接触孔(17)。 10. The inverse proportional NMOS tube layout structure against total dose radiation effect according to claim 6, characterized in that: an injection guard ring (5) is set in the active region (1), and the injection guard ring (5 ) covers the active region (1) and the end edge of the polycrystalline gate (2) in the active region (1), and the injection guard ring (5) extends around the outer circle of the active region (1); A substrate potential contact hole (17) is arranged in the source region (1).
CN2011103447066A 2011-11-03 2011-11-03 Inverse proportion or small proportion NMOS tube layout structure for resisting total dose radiation effect Active CN102412304B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2011103447066A CN102412304B (en) 2011-11-03 2011-11-03 Inverse proportion or small proportion NMOS tube layout structure for resisting total dose radiation effect

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2011103447066A CN102412304B (en) 2011-11-03 2011-11-03 Inverse proportion or small proportion NMOS tube layout structure for resisting total dose radiation effect

Publications (2)

Publication Number Publication Date
CN102412304A true CN102412304A (en) 2012-04-11
CN102412304B CN102412304B (en) 2013-11-13

Family

ID=45914279

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2011103447066A Active CN102412304B (en) 2011-11-03 2011-11-03 Inverse proportion or small proportion NMOS tube layout structure for resisting total dose radiation effect

Country Status (1)

Country Link
CN (1) CN102412304B (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103268874A (en) * 2013-04-23 2013-08-28 中国电子科技集团公司第十一研究所 Radiation-proof infrared focal plane detector reading circuit
CN104934475A (en) * 2015-03-12 2015-09-23 西安电子科技大学 Gate-all-around anti-irradiation MOS field effect transistor based on 65 nm technology
CN106372269A (en) * 2015-07-20 2017-02-01 复旦大学 Anti-radiation layout design method for storage unit circuit
CN109585531A (en) * 2018-11-29 2019-04-05 中国电子科技集团公司第四十七研究所 The metal-oxide-semiconductor field effect transistor of resistant to total dose effect

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101419986A (en) * 2008-12-05 2009-04-29 北京时代民芯科技有限公司 Double edge total dose resistant radiation reinforcement pattern construction preventing edge electricity leakage
CN101431104A (en) * 2008-12-05 2009-05-13 北京时代民芯科技有限公司 Double-edge anti-integral dose radiation reinforced layout structure
CN101752420A (en) * 2009-12-15 2010-06-23 北京时代民芯科技有限公司 Total dose radiation hardening I-shaped gate layout structure
CN102074580A (en) * 2010-11-17 2011-05-25 北京时代民芯科技有限公司 Transistor structure with reinforced total dose radiation resistance
CN202405266U (en) * 2011-11-03 2012-08-29 中国电子科技集团公司第五十八研究所 An Inverse Scale or Small Scale NMOS Tube Layout Structure Against Total Dose Radiation Effect

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101419986A (en) * 2008-12-05 2009-04-29 北京时代民芯科技有限公司 Double edge total dose resistant radiation reinforcement pattern construction preventing edge electricity leakage
CN101431104A (en) * 2008-12-05 2009-05-13 北京时代民芯科技有限公司 Double-edge anti-integral dose radiation reinforced layout structure
CN101752420A (en) * 2009-12-15 2010-06-23 北京时代民芯科技有限公司 Total dose radiation hardening I-shaped gate layout structure
CN102074580A (en) * 2010-11-17 2011-05-25 北京时代民芯科技有限公司 Transistor structure with reinforced total dose radiation resistance
CN202405266U (en) * 2011-11-03 2012-08-29 中国电子科技集团公司第五十八研究所 An Inverse Scale or Small Scale NMOS Tube Layout Structure Against Total Dose Radiation Effect

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103268874A (en) * 2013-04-23 2013-08-28 中国电子科技集团公司第十一研究所 Radiation-proof infrared focal plane detector reading circuit
CN104934475A (en) * 2015-03-12 2015-09-23 西安电子科技大学 Gate-all-around anti-irradiation MOS field effect transistor based on 65 nm technology
CN106372269A (en) * 2015-07-20 2017-02-01 复旦大学 Anti-radiation layout design method for storage unit circuit
CN106372269B (en) * 2015-07-20 2020-10-20 复旦大学 A radiation-resistant layout design method for memory cell circuits
CN109585531A (en) * 2018-11-29 2019-04-05 中国电子科技集团公司第四十七研究所 The metal-oxide-semiconductor field effect transistor of resistant to total dose effect
CN109585531B (en) * 2018-11-29 2022-03-15 中国电子科技集团公司第四十七研究所 MOS field effect transistor for resisting total dose effect

Also Published As

Publication number Publication date
CN102412304B (en) 2013-11-13

Similar Documents

Publication Publication Date Title
CN102270663B (en) Planar power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device with super junction structure and manufacturing method of planar power MOSFET device
CN101419986B (en) Double edge total dose resistant radiation reinforcement pattern construction preventing edge electricity leakage
CN101752420B (en) Total dose radiation hardening I-shaped gate layout structure
CN102969312A (en) High-voltage ESD (electro-static discharge) protective device triggered by bidirectional substrate
CN101924131B (en) Transverse-diffusion MOS (Metal Oxide Semiconductor) device and manufacturing method thereof
CN103840007B (en) VDMOS of shield grid structure
CN109888017A (en) A radiation-resistant LDMOS device
CN102412304A (en) An Inverse Scale or Small Scale NMOS Tube Layout Structure Against Total Dose Radiation Effect
CN102832249A (en) Metal oxide semiconductor (MOS) type power semiconductor device
CN101431104B (en) Double-edge anti-integral dose radiation reinforced layout structure
CN109148583A (en) SNLDMOS device and its manufacturing method
CN109585531A (en) The metal-oxide-semiconductor field effect transistor of resistant to total dose effect
CN202405266U (en) An Inverse Scale or Small Scale NMOS Tube Layout Structure Against Total Dose Radiation Effect
CN104201204A (en) Transverse symmetrical DMOS (double diffusion metal-oxide-semiconductor) pipe and manufacture method thereof
CN102412303A (en) A Layout Reinforcement Structure of Large Striped Gate MOS Tubes Against Total Dose Radiation Effect
CN202332861U (en) A Layout Reinforcement Structure of Large Striped Gate MOS Tubes Against Total Dose Radiation Effect
CN102315217B (en) Multi-finger strip-type gate-ground N-channel metal oxide semiconductor (GGNMOS) and electrostatic protection circuit
CN115863390A (en) Low Radiation Leakage High Voltage LDMOS Device Structure
CN102354678B (en) Silicon-on-insulator (SOI) structures with step-type buried oxide layers
CN105977196A (en) Anti-single-event transient reinforcement SOI member and manufacture method for the same
CN207425863U (en) Semiconductor field effect transistor with three-stage oxygen buried layer
CN205984999U (en) Take power transistor of electrostatic discharge protective diode structure
Dash et al. Segmented Drain Engineered Tunnel Field Effect Transistor for Suppression of Ambipolarity
CN104425489A (en) High-voltage device and low-voltage device integrating structure and integrating method
US6153909A (en) Semiconductor device and method for fabricating the same

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant