CN101431104A - Double-edge anti-integral dose radiation reinforced layout structure - Google Patents
Double-edge anti-integral dose radiation reinforced layout structure Download PDFInfo
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- CN101431104A CN101431104A CNA2008102389536A CN200810238953A CN101431104A CN 101431104 A CN101431104 A CN 101431104A CN A2008102389536 A CNA2008102389536 A CN A2008102389536A CN 200810238953 A CN200810238953 A CN 200810238953A CN 101431104 A CN101431104 A CN 101431104A
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Abstract
The invention relates to a double-edge total dose radiation resistance reinforcement domain structure, and the domain structure comprises an underlay, an active zone, an injection zone and a bar, wherein the active zone and the injection zone are formed on the underlay; overlapping zone of the active zone and the injection zone forms a source zone and a leakage zone; the bar adopts a double-edge structure two sides of which is beyond the active region; the source zone and the leakage zone are separated; the injection zone is arranged on the inner part of the active zone; thin oxide between the active zone and the leakage zone is ensured to exist between the active zone and the leakage zone; and a passageway between the active zone and the leakage zone completely formed by thick oxide is eliminated. The double-edge total dose radiation resistance reinforcement domain structure solves the problem of parasitic leakage caused by the total dose effect of ionizing radiation, and solves the problems of great area, bad symmetry, difficult realization of small breadth length ratio, difficult modelling, and the like brought by traditional closed bar reinforcement structure at the same time.
Description
Technical field
The present invention relates to a kind of domain structure, especially a kind of anti-integral dose radiation reinforced layout structure.
Background technology
Figure 1 shows that the plane graph of a standard normal transistor 11.Transistor 11 comprises an injection region 111, an active area 13, a polysilicon gate 16, the lap of injection region 111 and active area 13 (here being the active area part) is divided into three parts by grid 16, the part that is covered by grid is a channel region 112, and all the other parts on the grid both sides are respectively transistorized source region 14 and drain region 15.Active area 13 has defined the thin-oxide district, and the part outside the active area is all thick oxide region.Transistor when work,, when substrate 12 transoids,, otherwise there is not conductive channel with the conductive channel that forms between source region 14 and the drain region 15 by the substrate (or trap) 12 of the voltage control channel region 112 of grid 16 transoid whether.
The technology of standard all can have design rule.So-called design rule guarantees not occur in the production process layout size rule of making mistake and improving yield exactly.Here introduce 2 design rules commonly used in the standard technology design rule.Among Fig. 1, the minimum of the 111 pairs of active areas 13 in injection region covers 17, and the layout design rules value of establishing this distance is L1
0One end of polysilicon gate 16 leans out the minimum range 18 of active area 13, and the layout design rules value of establishing this distance is L2
0
Channel length and channel width are the most important parameters of transistor.Among Fig. 1, transistorized channel length 19 be defined as source region 14 to the drain region 15 minimum range, channel width 110 is defined as the length of source region 14 or drain region 15 and grid 16 intersecting lenses.
Fig. 2 A is the transistorized longitudinal sectional drawing of standard normal, in this profile, has a source region 24A, and a drain region 26A, and a polysilicon gate 25A are grid oxygen 29A between the substrate 22A of the active area under the grid and the polysilicon gate 25A, and grid oxygen 29A is thin oxygen.Part beyond active area is outer is thick oxygen 28A.
(Total lonizing Dose, TID) effect is meant that electronic devices and components or system are under the radiation environment for a long time to the ionising radiation accumulated dose, forms the phenomenon of oxide trap electric charge and interfacial state electric charge in insulating barrier (mainly being oxide layer) accumulation.Performance of semiconductor device that this cumulative effect can cause is degenerated, and comprises that the drift of device threshold voltage, mobility descend, the increase of leakage current etc.Along with the progress of technology, gate oxide is more and more thinner, the threshold voltage shift of device, and the leakage current of the decline of mobility and intrinsic device is gradually little of negligible degree, and the problem that highlights is the electric leakage of sneak path.
Parasitic leakage mainly refers to the electric leakage relevant with the N transistor npn npn.Its mechanism is: because the total radiation dose effect, in oxide layer, accumulated the positive charge of some, the quantity of stored charge and oxidated layer thickness positive correlation, and the field oxygen thickness that is used as the electricity isolation is tens times of gate oxide thickness, therefore the electric charge in the oxygen can be more much more than the electric charge in the grid oxygen, these positive charges in the oxygen of field form electric field between oxide layer and P type substrate (or P trap), cause the P type substrate (or P trap) under the oxygen layer to be tending towards transoid; When the dosage of radiation is enough big, the electric field that a large amount of positive charges of accumulating in the oxygen of field cause will be enough to make the above-mentioned zone transoid, when the zone of transoid when N+ injection region more than 2 or 2 links to each other, will be at the interval electric leakage path that forms of these N+, originally will not design and this path is not the designer, be a kind of parasitic leakage path.There are two kinds of main electric leakage paths in the conventional transistor design.
One is the edge current leakage that the polysilicon gate of same device causes at active area and place intersection overlap joint.In Fig. 2 A, during substrate (or trap) 22A transoid under near the field oxygen 28A radiation effect causes active area, to between the source region of device 24A and drain region 25A, form parasitic channel 212A, be equivalent to form respectively the parasitic transistor 211A of a parallel connection in the both sides of intrinsic transistor.This will have a strong impact on Devices Characteristics.Another is the electric leakage that exists between the N type district of different components, shown in Fig. 2 B.When radiation effect causes being used for substrate (or trap) 22B transoid under the field oxygen 28B that electricity isolates, form conducting channel 212B, when the current potential at this parasitic channel 212B two ends not simultaneously, will in raceway groove, form leakage current, this can cause the decreased performance of circuit or even thoroughly lose efficacy.This leakage mechanisms may occur between source (or leak) the district 24B of two N transistor npn npns, perhaps occurs between source (or leakage) the district 24B of the N+ type contact zone 214B of trap 213B and adjacent N transistor npn npn, as Fig. 2 B.
Along with the development of domestic and international technology, occurred adopting closed grid structure shown in Figure 3 to solve the edge current leakage problem.The drain region 35 of this structure 31 is in closed grid 36, and source region 34 is outside closed grid 36, and is or opposite.Has only the grid oxygen under the grid 36 between source region 34 and the drain region 35, be thin oxide layer, field oxygen path between source region 34 that can abatement device and the drain region 35, solve the edge current leakage problem, but this structure devices area is bigger, source-drain area is asymmetric, and out-of-shape, bring a lot of inconveniences for design and modeling, in addition, closed grid structure 31 can not solve the electric leakage problem that exists between the different components N type district shown in Fig. 2 B.
Summary of the invention
Technology of the present invention is dealt with problems and is: overcome the deficiencies in the prior art, a kind of anti-integral dose radiation reinforced layout structure is provided, solved the parasitic leakage problem that causes by the ionising radiation total dose effect, having solved traditional closed grid ruggedized construction simultaneously brings area big, symmetry is bad, is difficult to realize little breadth length ratio and is difficult to problems such as modeling.
Technical solution of the present invention is: a kind of double-edge anti-integral dose radiation reinforced layout structure, it is characterized in that, described domain structure comprises substrate, active area, injection region, grid, on substrate, be formed with source region and injection region, the overlapping region of active area and injection region forms source region and drain region, grid adopt both sides to exceed the dual edge structure of active area, and source region and drain region separated, the injection region is in the inside of active area, guarantee to have thin-oxide between source region and the drain region, eliminated the path that constitutes by thick-oxide fully between source region and the drain region.
Described active area satisfies L1 〉=L1 to the minimum overlay length value L1 of injection region
0, wherein, L1
0Be the minimum overlay length value of injection region in the standard technology design rule to active area.
The minimum length value L2 that described grid exceed active area satisfies L2 〉=L2
0, wherein, L2
0The minimum length value that exceeds active area for grid in the standard technology design rule.
The channel length L of the MOS transistor that described domain structure constitutes is by the distance decision between source region and the drain region, and its channel width W is by the length decision of the intersecting lens of source region and grid.
The present invention's advantage compared with prior art is: the present invention adopts the domain structure of dual edge grid, rational deployment by injection region and active area, make and have thin-oxide between source region and the drain region all the time, eliminate the path that constitutes by thick-oxide fully between source region and the drain region, when solving the radiation initiation parasitic leakage problem relevant with the N transistor npn npn, the area that can also solve traditional ruggedized construction existence is big, symmetry is bad, be difficult to realize little breadth length ratio and be difficult to problems such as modeling, obtained significant effect.As Fig. 6, be depicted as the metal-oxide-semiconductor of employing structure of the present invention and the transfer characteristic curve of non-reinforcing MOS, and drain-source current l
DSWith gate source voltage V
GSThe curve that changes.Fig. 6 has provided the curvilinear motion before and after the total dose irradiation of 1Mrad (Si), and as seen adopting the static leakage of the metal-oxide-semiconductor of structure formation of the present invention is V
GSL during=V
DSValue has reduced about 3 orders of magnitude, causes the parasitic leakage problem thereby solved by the ionising radiation total dose effect.And, compare with closed grid ruggedized construction, reduced device area, have the symmetry that leak in the source, can realize any breadth length ratio, be convenient to design and modeling, and this structure has solved the electric leakage problem that exists between the insurmountable different components N of the closed grid structure type district.
Description of drawings
Fig. 1 is standard normal transistor planar figure;
Fig. 2 A is a standard normal transistor longitudinal sectional drawing;
Fig. 2 B is the electric leakage schematic diagram between the total dose effect different N+district of causing;
Fig. 3 is ring-shaped gate transistor arrangement schematic diagram commonly used;
Fig. 4 is a domain structure schematic diagram one of the present invention;
Fig. 5 A be structure shown in Figure 4 along A-A, profile;
Fig. 5 B is the profile of structure shown in Figure 4 along B-B ';
Fig. 6 is for adopting formed metal-oxide-semiconductor of structure of the present invention and the non-reinforcing metal-oxide-semiconductor transfer characteristic curve before and after the total dose irradiation of 1Mrad (Si);
Fig. 7 is a domain structure schematic diagram two of the present invention.
Embodiment
As shown in Figure 4, domain structure 41 comprises substrate 42, active area 43, injection region 411, grid 46, on substrate 42, be formed with source region 43 and injection region 411, the overlapping region of active area 43 and injection region 411 forms source region 44 and drain region 45, grid 46 adopt both sides to exceed the dual edge structure of active area 43, and source region 44 and drain region 45 separated, injection region 411 is in the inside of active area 43, guarantee to have thin-oxide between source region 44 and the drain region 45, eliminated the path that constitutes by thick-oxide fully between source region 44 and the drain region 45.
In domain structure 41, in order to realize the thin-oxide district, the minimum overlay length value 47 of 43 pairs of injection regions 411 of active area satisfies L1 〉=L1
0, wherein, L1
0Be the minimum overlay length value of injection region in the standard technology design rule to active area, as in typical 0.18 μ m technology, L1
0Value be about 0.25 μ m.The minimum length value 48 that grid 46 exceed active area 43 satisfies L2 〉=L2
0, wherein, L2
0For grid in the standard technology design rule exceed the minimum length value of active area, as in typical 0.18 μ m technology, L2
0Value be about 0.2 μ m.The channel length L of the MOS transistor that domain structure 41 constitutes is by 49 decisions of the distance between source region 44 and the drain region 45, and its channel width W is by length 410 decisions of source region 44 with the intersecting lens of grid 46.In addition, according to the characteristic of MOS transistor, above-mentioned source region 44 and drain region 45 can exchange.
Along the A-A of Fig. 4, and the profile that B-B ' is done is shown in Fig. 5 A and Fig. 5 B.Wherein active area 43 has defined thin-oxide district 53A, the 53B of device, and the zone outside the active area 43 is thick oxide region 511A, 511B.Between between source region 44 and the drain region 45 and source region 44 or drain region 45 and other N type district, there is thin-oxide all the time like this, the field oxygen parasitic leakage path that is produced by total dose effect will be eliminated owing to the existence of this thin-oxide, and then parasitic static leakage current also will reduce greatly, as shown in Figure 6, the transistor that adopts structure of the present invention is behind the total dose irradiation of 1Mrad (Si), still characteristic is good, compares its static leakage current 3 orders of magnitude that descended with non-ruggedized construction.
Fig. 7 has provided another execution mode.Domain structure 41 comprises substrate 42, active area 43, injection region 411, grid 46, on substrate 42, be formed with source region 43 and injection region 411, the overlapping region of active area 43 and injection region 411 forms source region 44 and drain region 45, grid 46 adopt both sides to exceed the dual edge structure of active area 43, and source region 44 and drain region 45 separated, in this embodiment, grid 46 be not straight, and having certain bending in active area 43 inside, the direction at place, two edges is vertical; Injection region 411 guarantees to have thin-oxide between source region 44 and the drain region 45 in the inside of active area 43, has eliminated the path that is made of thick-oxide fully between source region 44 and the drain region 45.Equally, in domain structure 41, in order to realize the thin-oxide district, the minimum overlay length value 47 of 43 pairs of injection regions 411 of active area satisfies L1 ' 〉=L1
0The minimum length value 48 that grid 46 exceed active area 43 satisfies L2 ' 〉=L2
0The channel length of the MOS transistor that domain structure 41 constitutes is by 49 decisions of the distance between source region 44 and the drain region 45, its channel width is by length 410 decisions of source region 44 with the intersecting lens of grid 46, notice that the value of channel width is obtained by several sections line segment length additions when grid 46 are curved shape.
The implementation of structure of the present invention has a lot, except Fig. 4 and structure shown in Figure 7, can also be other all modes that satisfy described requirement.
Unaccomplished matter of the present invention belongs to techniques well known.
Claims (5)
1, a kind of double-edge anti-integral dose radiation reinforced layout structure, it is characterized in that: described domain structure (41) comprises substrate (42), active area (43), injection region (411), grid (46), on substrate (42), be formed with source region (43) and injection region (411), the overlapping region of active area (43) and injection region (411) forms source region (44) and drain region (45), described grid (46) adopt both sides to exceed the dual edge structure of active area (43), and source region (44) and drain region (45) separated, injection region (411) is in the inside of active area (43), guarantee to have thin-oxide between source region (44) and drain region (45), eliminate the path that constitutes by thick-oxide fully between source region (44) and drain region (45).
2, a kind of double-edge anti-integral dose radiation reinforced layout structure according to claim 1 is characterized in that: described active area (43) satisfies L1 〉=L1 to the minimum overlay length value L1 (47) of injection region (411)
0, wherein, L1
0Be the minimum overlay length value of injection region in the standard technology design rule to active area.
3, a kind of double-edge anti-integral dose radiation reinforced layout structure according to claim 1 is characterized in that: the minimum length value L2 (48) that described grid (46) exceed active area (43) satisfies L2 〉=L2
0, wherein, L2
0The minimum length value that exceeds active area for grid in the standard technology design rule.
4, according to claim 1 or 2 or 3 described a kind of double-edge anti-integral dose radiation reinforced layout structures, it is characterized in that: the channel length L of the MOS transistor that described domain structure (41) constitutes is by the decision of the distance (49) between source region (44) and drain region (45), and its channel width W is by source region (44) length (410) decision with the intersecting lens of grid (46).
5, a kind of double-edge anti-integral dose radiation reinforced layout structure according to claim 1 is characterized in that: described source region (44) and drain region (45) can exchange.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101930982A (en) * | 2010-07-07 | 2010-12-29 | 中国电子科技集团公司第五十八研究所 | FLOTOX structure-based radioresistant EEPROM storage unit structure |
| CN101752420B (en) * | 2009-12-15 | 2012-03-07 | 北京时代民芯科技有限公司 | Total dose radiation hardening I-shaped gate layout structure |
| CN102412304A (en) * | 2011-11-03 | 2012-04-11 | 中国电子科技集团公司第五十八研究所 | Inverse ratio or small ratio NMOS (N-channel Metal Oxide Semiconductor) tube layout structure resistant to total dose irradiation effect |
| CN104752513A (en) * | 2015-03-12 | 2015-07-01 | 西安电子科技大学 | Redundant doping radiation-proof MOS (Metal Oxide Semiconductor) field-effect tube based on 65nm process |
| CN109935626A (en) * | 2017-12-17 | 2019-06-25 | 微龛（北京）半导体科技有限公司 | Silicon total dose effect domain reinforcement technique on a kind of insulating layer |
-
2008
- 2008-12-05 CN CN2008102389536A patent/CN101431104B/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101752420B (en) * | 2009-12-15 | 2012-03-07 | 北京时代民芯科技有限公司 | Total dose radiation hardening I-shaped gate layout structure |
| CN101930982A (en) * | 2010-07-07 | 2010-12-29 | 中国电子科技集团公司第五十八研究所 | FLOTOX structure-based radioresistant EEPROM storage unit structure |
| CN101930982B (en) * | 2010-07-07 | 2012-04-18 | 中国电子科技集团公司第五十八研究所 | FLOTOX structure-based radioresistant EEPROM storage unit structure |
| CN102412304A (en) * | 2011-11-03 | 2012-04-11 | 中国电子科技集团公司第五十八研究所 | Inverse ratio or small ratio NMOS (N-channel Metal Oxide Semiconductor) tube layout structure resistant to total dose irradiation effect |
| CN104752513A (en) * | 2015-03-12 | 2015-07-01 | 西安电子科技大学 | Redundant doping radiation-proof MOS (Metal Oxide Semiconductor) field-effect tube based on 65nm process |
| CN104752513B (en) * | 2015-03-12 | 2017-11-21 | 西安电子科技大学 | A kind of method of the redundancy doping Flouride-resistani acid phesphatase metal-oxide-semiconductor field effect transistor prepared based on 65nm techniques |
| CN109935626A (en) * | 2017-12-17 | 2019-06-25 | 微龛（北京）半导体科技有限公司 | Silicon total dose effect domain reinforcement technique on a kind of insulating layer |
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| CN101431104B (en) | 2010-07-14 |
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