CN102074580B - Transistor structure with reinforced total dose radiation resistance - Google Patents
Transistor structure with reinforced total dose radiation resistance Download PDFInfo
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- CN102074580B CN102074580B CN 201010548221 CN201010548221A CN102074580B CN 102074580 B CN102074580 B CN 102074580B CN 201010548221 CN201010548221 CN 201010548221 CN 201010548221 A CN201010548221 A CN 201010548221A CN 102074580 B CN102074580 B CN 102074580B
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Abstract
The invention discloses a transistor structure with reinforced total dose radiation resistance. An active area is divided by a grid area into a drain area, a source area and a flotation area, the grid area surrounds the drain area completely, a closed parasitic circuit from a source area to a drain area is eliminated, and a total dose radiation resistance reinforcement function is realized. The structure disclosed by the invention solves the problem of parasitic current leakage, which is caused by a total ionizing dose effect, between the source and drain areas, realizes small-size transistor and effectively reduces grid capacitance, thereby better meeting requirements of the high-speed, low-power consumption and reinforced-radiation resistance integrated circuits.
Description
Technical field
The present invention relates to a kind of transistor arrangement, relate in particular to a kind of transistor structure with reinforced total dose radiation resistance.
Background technology
Figure 1 shows that the plane graph of a standard normal mos field effect transistor (MOS transistor).MOS transistor comprises grid region 11, drain region 12 and source region 13, and grid region 11 is divided into drain region 12 and source region 13 with active area 10, and drain region 12 and source region 13 do not have intersecting area.An important parameter that determines transistor characteristic is effective breadth length ratio of transistor channel region, and this parameter is determined by transistorized effective channel width 14 and the ratio of length of effective channel 15.Usually, in the situation that other condition is identical, transistorized effective breadth length ratio is larger, and its dynamic power consumption is larger.
The ionising radiation total dose effect refers to that electronic devices and components or system are under the radiation environment for a long time, forms the phenomenon of oxide trap electric charge and heterointerface state charge in insulating barrier (mainly being oxide layer) accumulation.Performance of semiconductor device that this cumulative effect can cause is degenerated, and comprises that the drift of device threshold voltage, mobility descend, the increase of leakage current etc.Along with the progress of technique, gate oxide is more and more thinner, the threshold voltage shift of device, and the leakage current of the decline of mobility and intrinsic device is gradually little of negligible degree, and the problem that highlights is the electric leakage of sneak path.Parasitic leakage mainly refers to the electric leakage relevant with the N-type MOS transistor.The radiation relevant with present technique causes electric leakage and is the edge current leakage in MOS transistor source region and drain region.Be that the ionising radiation total dose effect will cause the go out head part of grid 11 outside active area 10 between transistorized drain region 12 shown in Figure 1 and the source region 13 to form the parasitic leakage passage.
Omit and give birth to electric leakage in order to overcome source that the ionising radiation accumulated dose causes, a kind of transistor arrangement of closed grid occurred.As shown in Figure 2, the grid 21 of this transistor arrangement are closed, do not have the grid of lifting one's head between source region 23 and the drain region 22, thereby the parasitic leakage path that does not exist radiation to cause.The shortcoming of structure shown in Figure 2 is to realize small size, the transistor of especially little breadth length ratio, thus can't reduce the power consumption of the circuit that uses this kind structure.For this reason, transistor arrangement shown in Figure 3 has appearred.The grid of this structure also are closed, but the grid that can form current channel only account for the some of whole grid, so can realize less effective breadth length ratio, thereby reduce circuit power consumption.The shortcoming of structure shown in Figure 3 is that gate area is larger, produces thus larger gate capacitance, and large gate capacitance is with increasing circuit dynamic power consumption, reduction circuit performance, and these shortcomings have also limited the application of this structure.
Summary of the invention
Technology of the present invention is dealt with problems and is: overcome the deficiencies in the prior art, a kind of transistor structure with reinforced total dose radiation resistance is provided, the source transistor that solution is caused by the ionising radiation total dose effect is omitted living electric leakage problem, realizes little breadth length ratio transistor, reduces parasitic gate capacitance.
Technical solution of the present invention is:
A kind of transistor structure with reinforced total dose radiation resistance, comprise grid region, drain region, source region and floating dead zone, described grid region, drain region, source region and floating dead zone are distributed within the same active area and the grid region is separated into source region, drain region and floating dead zone with active area, drain region, source region and floating dead zone do not have intersecting area between any two, the drain region is surrounded fully by the grid region, the source region is surrounded by the grid region part or surrounds fully, and floating dead zone is surrounded by the grid region part; Described floating dead zone refers to have doping type of the same race and same zone doping content and that do not draw by line with source region and drain region.
In a transistor, described drain region has 1, and described source region is no less than 1, and described floating dead zone is no less than 1.
The present invention's advantage compared with prior art is:
(1) structure of the present invention has been eliminated the parasitic leaked current of field oxide path of source region to the drain region, the resistant to total dose ability of Effective Raise device by the drain region is surrounded with the grid region fully; By introducing a floating dead zone at active area, does not draw by line floating dead zone, reduces the source region to effective channel width in drain region, thereby reduce transistorized effective breadth length ratio; Structure of the present invention is when effectively reducing the parasitic leakage that is caused by accumulated dose, compare with traditional ruggedized construction, can realize the MOS transistor of less breadth length ratio, and have lower gate area and electric capacity, therefore more be conducive to the application of high-speed low-power-consumption radiation hardening circuit.
(2) structure of the present invention, a plurality of source regions or a plurality of floating dead zone can be arranged in a transistor, than traditional ruggedized construction of only having a source region and a drain region more implementation is arranged, more be conducive to realize the compromise of device on performance, power consumption and area.
Description of drawings
Fig. 1 is standard normal transistor arrangement schematic diagram;
Fig. 2 is ring-shaped gate transistor arrangement schematic diagram;
Fig. 3 is the anti-integral dose radiation reinforced small-geometry transistor structural representation of a kind of tradition;
Fig. 4 is structural representation of the present invention;
Fig. 5 is the 2nd kind of execution mode schematic diagram of structure of the present invention;
Fig. 6 is the 3rd kind of execution mode schematic diagram of structure of the present invention;
Fig. 7 is the 4th kind of execution mode schematic diagram of structure of the present invention;
Fig. 8 is the 5th kind of execution mode schematic diagram of structure of the present invention.
Embodiment
A kind of transistor structure with reinforced total dose radiation resistance of the present invention, comprise grid region, drain region, source region and floating dead zone, described grid region, drain region, source region and floating dead zone are distributed within the same active area and the grid region is separated into source region, drain region and floating dead zone with active area, drain region, source region and floating dead zone do not have intersecting area between any two, the drain region is surrounded fully by the grid region, the source region is surrounded by the grid region part or surrounds fully, and floating dead zone is surrounded by the grid region part; Floating dead zone refers to have doping type of the same race and same zone doping content and that do not draw by line with source region and drain region.In a transistor, the drain region has 1, and the source region is no less than 1, and floating dead zone is no less than 1.In transistor, source region, drain region and the grid region Three regions that is absolutely necessary, and also active area also is the intrinsic area concept of transistor and definition, in the structure of the present invention, introduced the concept of floating dead zone, and source region, drain region, grid region and floating dead zone are distributed among the same active area.During transistor work, the grid region is as the current channel of source region to the drain region, the conducting situation of this passage is subjected to the control of grid voltage, transistorized current lead-through ability depends on the effective width of raceway groove and the proportionate relationship of effective length, device breadth length ratio namely, usually, the breadth length ratio of device is larger, the On current of device is larger, and power consumption is also higher.In structure of the present invention, owing to introducing floating dead zone, can effectively reduce the channel width of device, realize less device breadth length ratio, and then can realize the characteristic of low-power consumption.According to the requirement of different circuit functions, device architecture of the present invention can obtain different embodiments by different grid shapes, makes device have a plurality of source regions or floating dead zone, is conducive to device and carries out this consideration in many-sides such as performance, power consumption and areas.
Transistor arrangement of the present invention has many kinds of execution modes, and the below is introduced with regard to several typical modes.
As shown in Figure 4, a kind of transistor structure with reinforced total dose radiation resistance, comprise grid region 41, drain region 42, source region 43 and floating dead zone 44, grid region 41 is separated into source region 43, drain region 42 and floating dead zone 44 with active area 40, drain region 42, source region 43 and floating dead zone 44 do not have intersecting area between any two, drain region 42 is surrounded fully by grid region 41, and source region 43 is surrounded or surrounds fully by grid region 41 parts, and floating dead zone 44 is surrounded by grid region 41 parts.In this structure, there is not direct parasitic leakage passage between drain region 42 and the source region 43, namely the passage between source region 43 and the drain region 42 must through grid region 41, leak electricity thereby effectively reduce the parasitic OFF state that is caused by the ionising radiation accumulated dose.And, because a part of only having the grid region is as the effective current path between drain region 42 and the source region 43 and the effective raceway groove of device, thereby effectively reduce transistorized effective breadth length ratio, and then reduced circuit power consumption.In addition, owing to do not have contributive gate region can design to such an extent that minimize to the effective channel width of transistor, thus reduce the grid region area, further reduce the dynamic power consumption of circuit, and can effectively promote circuit performance.
According to a kind of transistor structure with reinforced total dose radiation resistance of the present invention, in a transistor, described drain region has 1, and described source region can be 1, also can be more than 1, and described floating dead zone can be 1, also can be more than 1.In the schematic diagram as shown in Figure 4, only have a drain region 42, a source region 43 and a floating dead zone 44 in the transistor.Fig. 5 has provided another execution mode.In this structure, grid region 51 with all the other region separation be 1 drain region 52,1 source region 53 and 2 floating dead zones 54 and 54 '.Wherein, drain region 52 and source region 53 are all surrounded by grid region 51 fully, and 2 floating dead zones 54 and 54 ' are all surrounded by grid region 51 parts.The advantage of this execution mode is to have good source and leaks symmetry, and namely source region and drain region are based on centrosymmetricly, and the design that symmetry is conducive to analog circuit and switching circuit is more leaked in the source.
In the execution mode shown in Figure 6, grid region 61 with active area 60 be divided into 1 drain region 62,2 source regions 63 and 63 ', 2 floating dead zones 64 and 64 ', wherein, source region 62 is surrounded by grid region 61 fully, and 2 source regions 63 and 63 ' and 2 floating dead zones 64 and 64 ' all surrounded by the grid region part.Compare with execution mode shown in Figure 4, the device that this execution mode is realized is in the situation that the integral device area change is little, and effectively channel width has increased one times, is applicable to the transistor of realizing that breadth length ratio is moderate.
Fig. 7 has provided the moderate transistor implementation of another breadth length ratio.Different from execution mode shown in Figure 6 is, in this structure, grid region 71 is separated into 1 drain region 72,1 source region 73 and 1 floating dead zone 74, totally 3 parts with active area 70.In addition, different from top several execution modes is, the effective channel region 75 between source region and the drain region is curved, and effectively channel region is not the rectangle of a standard.
Because some process rules do not allow to occur the grid shape with the right angle, therefore in light of the circumstances, the shape of grid will be carried out suitable adjustment.As shown in Figure 8, in this embodiment, there is not the right angle in the shape in grid region 81 in active area, and only has 135 degree angles.This execution mode can satisfy the rule request of advanced technologies, is conducive to improve transistorized reliability.
Above several embodiment just adopts several examples of structure of the present invention, and structure of the present invention also has many other execution modes.
Claims (2)
1. transistor structure with reinforced total dose radiation resistance, it is characterized in that: comprise grid region, drain region, source region and floating dead zone, described grid region, drain region, source region and floating dead zone are distributed within the same active area and the grid region is separated into source region, drain region and floating dead zone with active area, drain region, source region and floating dead zone do not have intersecting area between any two, the drain region is surrounded fully by the grid region, the source region is surrounded by the grid region part or surrounds fully, and floating dead zone is surrounded by the grid region part; Described floating dead zone refers to have doping type of the same race and same zone doping content and that do not draw by line with source region and drain region.
2. a kind of transistor structure with reinforced total dose radiation resistance according to claim 1, it is characterized in that: in a transistor, described drain region has 1, and described source region is no less than 1, and described floating dead zone is no less than 1.
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| CN 201010548221 CN102074580B (en) | 2010-11-17 | 2010-11-17 | Transistor structure with reinforced total dose radiation resistance |
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| CN102412304B (en) * | 2011-11-03 | 2013-11-13 | 中国电子科技集团公司第五十八研究所 | Inverse ratio or small ratio NMOS (N-channel Metal Oxide Semiconductor) tube layout structure resistant to total dose irradiation effect |
| CN113161422B (en) * | 2021-05-19 | 2022-11-04 | 电子科技大学 | Low-radiation electric leakage high-voltage LDMOS device structure |
| CN113410306B (en) * | 2021-06-15 | 2023-06-30 | 西安微电子技术研究所 | Total dose radiation resistant reinforced LDMOS device structure and preparation method |
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