CN105977196A - Anti-single-event transient reinforcement SOI member and manufacture method for the same - Google Patents
Anti-single-event transient reinforcement SOI member and manufacture method for the same Download PDFInfo
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- CN105977196A CN105977196A CN201610391993.9A CN201610391993A CN105977196A CN 105977196 A CN105977196 A CN 105977196A CN 201610391993 A CN201610391993 A CN 201610391993A CN 105977196 A CN105977196 A CN 105977196A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
Abstract
The invention relates to the microelectronic technology field. The invention discloses an anti-single-event transient reinforcement SOI member, comprising a substrate, a buried oxide layer, a semiconductor body region, a drain region, a source region, a grid region, gridside walls, LDD regions and a heavily doped source extending region; the buried oxide layer is arranged above the substrate; the semiconductor body region, the source region and the drain region are arranged above the buried oxide layer; the semiconductor body region is positioned between the source region and the drain region; the LDD regions are positioned on two side ends of the semiconductor body region and in contact with the source region and the drain region; the grid region is positioned above the semiconductor body region; the two side gridside walls are arranged on two sides of the grid region and above the LDD regions; the source extending region is arranged among the source region, the semiconductor body region and the buried oxide layer; and the doping types of the source extending region and the source region are opposite. The invention also discloses a manufacture method for the anti-single-event transient reinforcement SOI member. The anti-single-event transient reinforcement SOI member and the manufacture method for the same can effectively inhibit SOI member single-event overturning and the single-event transient effect which are caused by single-event radiation, and the technology is simple and compatible with the current technology.
Description
Technical field
The invention belongs to microelectronics technology, reinforce SOI device and preparation method thereof more particularly to a kind of anti-single particle transient state.
Background technology
SOI (Silicon-on-Insulator) technology refers to form the material preparation technology with certain thickness single crystal semiconductor silicon membrane layer and the Technology manufacturing semiconductor device on thin layer on the insulating layer.SOI technology can realize the Fully dielectric isolation of device, compared with the bulk silicon technology isolated with PN junction, have without breech lock, at high speed, low-power consumption, high integration, the advantage that high temperature resistant, Radiation hardness is strong, be widely applied in high speed, low-power consumption, Flouride-resistani acid phesphatase circuit.
According to SOI silicon film thickness and the doping content of device and running voltage SOI device can be divided into two big classes: part depletion type and complete depletion type device.For the SOI device that silicon fiml is thicker, the thickness of silicon fiml is maximally depleted slice width degree more than twice, is referred to as part depletion SOI device；For the SOI device that silicon fiml is relatively thin, the thickness of silicon fiml, less than being maximally depleted slice width degree, is referred to as fully-depleted SOI device.The preparation technology of part depletion device is easy to migrate from bulk silicon technological, and the complexity of technique is relatively low, and substrate price is relatively cheap；And the preparation technology of fully-depleted device needs again to develop, technique is complex, and substrate price is relatively costly.Although fully-depleted device has more excellent subthreshold swing, OFF state electric leakage and floater effect, but is restricted by Costco Wholesale, technology difficulty, therefore part depletion SOI technology is more widely applied.
Owing to SOI technology MOS device is formed above oxygen buried layer, compared with body silicon, reduce formation single-ion transient state and the sensitive volume of Single event upset effecf, enhance the ability of anti-single particle effect.But, the neutral body district of part depletion SOI device not ground connection the same with body silicon device, therefore its current potential is uncertain, is easily subject to the impact of the effects such as gate tunneling current, impact ionization, irradiation.Source-body-leakage simultaneously also form the bipolar transistor of parasitism, when high energy particle incidence, parasitic bipolar transistor is in amplification mode, the quantity of electric charge that this quantity of electric charge that drain region is collected introduces much larger than high energy particle, part depletion SOI device is easier to single-ion transient state and Single event upset effecf.
Single particle effect to part depletion SOI device is reinforced and is mainly used two ways the most both at home and abroad: 1, use technique to reinforce means, in body district, such as inject the impurity element such as nitrogen, fluorine, these impurity elements form complex centre, reduce the life-span of minority carrier in body district, thus reduce the amplification of parasitic bipolar transistor.This mode needs to introduce nitrogen, fluorine element, brings contamination for standard silicon process；2, special SOI device structure is used.In source region SiGe formed below territory, the minority carrier in proper district is made to tie more easily by the SiGe that energy gap is narrower by energy band engineering.This mode is also required to introduce extra Ge element, and the junction depth of SiGe knot is difficult to control.
Summary of the invention
It is an object of the invention to provide one can effectively suppress single-particle radiation-induced SOI device single-particle inversion and single-ion transient state effect for solving the problems referred to above, technological process is simple and compatible with existing Technology, and the anti-single particle transient state not having impurity to introduce reinforces SOI device and preparation method thereof.
For this, the invention discloses a kind of anti-single particle transient state and reinforce SOI device, including substrate, oxygen buried layer, semiconductor body, drain region, source region, grid region, grid side wall, LDD region and extension area, heavily doped source, described oxygen buried layer is positioned at substrate, described semiconductor body, source region and drain region are positioned on oxygen buried layer, and semiconductor body is between source region and drain region, described LDD region be positioned at semiconductor body top, both sides and respectively with source region and drain contact, described grid region is positioned on semiconductor body, two grid side walls lay respectively at the both sides in grid region and on LDD region, extension area, described source contacts source region and semiconductor body simultaneously, and between source region and semiconductor body and oxygen buried layer, the doping type of extension area, described source is contrary with the doping type of source region.
Further, described oxygen buried layer at least part of source region of correspondence and at least part of source region semiconductor body position formed there is the sunk area for being filled with extension area, source, extension area, described source is filled with at this sunk area.
Further, extension area, described source is positioned at lower section and the lower section in part semiconductor body district of whole source region.
Further, the semi-conducting material of extension area, described source is identical with the material of semiconductor body.
Invention additionally discloses a kind of anti-single particle transient state as above and reinforce the preparation method of SOI device, comprise the steps:
A1, prepares SOI Substrate, including substrate, oxygen buried layer and top layer district；
A2, forms shallow trench isolation in top layer district；
A3, prepare extension area, heavily doped source, and preparation grid region, LDD region, grid side wall, semiconductor body, source region and drain region, the source extension area of making contacts source region, semiconductor body simultaneously, and between source region and semiconductor body and oxygen buried layer, the doping type making extension area, source is contrary with the doping type of source region.
Further, described step A3 is prepared extension area, heavily doped source include: the corresponding at least partly source region of oxygen buried layer and at least part of source region semiconductor body position formed there is the sunk area for being filled with extension area, source, extension area, described source is filled with at this sunk area, prepares extension area, heavily doped source at this sunk area.
Further, in described step A3, the semi-conducting material of extension area, source is identical with the semi-conducting material in top layer district.
The Advantageous Effects of the present invention:
Present invention introduces extension area, heavily doped source, its with as be heavy doping but the contrary source region of doping type forms tunnel-through diode, substantial amounts of electron hole pair is produced in single-particle radiation environment lower body district, electronics is collected hole by drain region and is then flowed to source region more easily by tunnel-through diode, reduce the electromotive force in body district, thus inhibit the amplification of source-body-leakage parasitic bipolar transistor, the electron amount that drain region is collected greatly reduces, effectively inhibit single-particle radiation-induced SOI device single-particle inversion and single-ion transient state effect, without introducing other element impurity, silicon standard technology will not be brought and stain, technological process is simple and compatible with existing Technology.
Accompanying drawing explanation
Fig. 1 is the SOI Substrate structural representation of the embodiment of the present invention；
Fig. 2 is that the deposited oxide after groove that formed of the embodiment of the present invention forms the generalized section of shallow-trench isolation；
Fig. 3 is the etching top layer silicon of the embodiment of the present invention and part oxygen buried layer and carries out monocrystal silicon deposit and heavily-doped implant forms the generalized section of extension area, source；
Fig. 4 is deposit gate oxide and the polysilicon of the embodiment of the present invention, etches the structural representation in grid region；
Fig. 5 is that the carrying out of the embodiment of the present invention is lightly doped the structural representation forming LDD region；
Fig. 6 is carrying out side wall deposit and etching and the structural representation of heavy doping formation source and drain areas of the embodiment of the present invention；
Fig. 7 is the deposition of electrode material of the embodiment of the present invention and etches the structural representation of source electrode, grid, drain contact；
Fig. 8 a is that the normal part of the embodiment of the present invention exhausts SOI device section of structure；
Fig. 8 b is the present example radiation-resistant SOI device architecture profile of the embodiment of the present invention；
Fig. 9 is three kinds of part depletion SOI device structure single-ion transient state response results figures of the embodiment of the present invention.
Detailed description of the invention
In conjunction with the drawings and specific embodiments, the present invention is further described.
nullAs shown in Figure 7，A kind of anti-single particle transient state reinforces SOI device，Including substrate 1、Oxygen buried layer 2、Semiconductor body 3、Drain region 9、Source region 10、Grid region、Grid side wall 11、LDD region 7 and extension area, heavily doped source 8，Oxygen buried layer 2 is positioned on substrate 1，The material of oxygen buried layer 2 is silicon dioxide，Described semiconductor body 3、Source region 10 and drain region 9 are positioned on oxygen buried layer 2，And semiconductor body 3 is between source region 10 and drain region 9，Described LDD region 7 is positioned at the top, both sides of semiconductor body 3 and contacts with source region 10 and drain region 9 respectively，Described grid region is positioned on semiconductor body 3，Grid region includes gate dielectric film 6 and gate electrode 5，The material of gate dielectric film 6 is silicon dioxide，The material of gate electrode 5 is polysilicon，Two grid side walls 11 lay respectively at the both sides in grid region and on LDD region 7，Extension area, described source 8 contacts source region 10 and semiconductor body 3 simultaneously，And between source region 10 and semiconductor body 3 and oxygen buried layer 2，The doping type of extension area, described source 8 is contrary with the doping type of source region 10，In this specific embodiment，The semi-conducting material of extension area, source 8 is identical with the material of semiconductor body 3，Oxygen buried layer 2 is formed in the position of at least part of source region of correspondence 10 and at least part of source region semiconductor body 3 has the sunk area for being filled with extension area, source 8，Extension area, described source 8 is filled with at this sunk area，And it is concordant with the upper surface of oxygen buried layer 2，Certainly，In other embodiments，Extension area, source 8 can also be positioned at above oxygen buried layer 2.Extension area, source 8 is positioned at lower section and the lower section in part semiconductor body district 3 of whole source region 10, in other is implemented, extension area, source 8 may be located at lower section and all lower section of semiconductor body 3 or the lower section of fractional source regions 10 and the lower section etc. in part semiconductor body district 3 of whole source region 10.
The present invention is by introducing extension area, heavily doped source 8, it is that heavily doped source region 10 forms tunnel-through diode as with, substantial amounts of electron hole pair is produced in single-particle radiation environment lower semiconductor body district 3, electronics is collected hole by drain region 9 and is then flowed to source region 10 more easily by tunnel-through diode, this is because the conducting voltage of tunnel-through diode is relatively low.For part depletion SOI device, in semiconductor body 3, the hole of accumulation is released in source region 10, reduce the electromotive force of semiconductor body 3, thus inhibit the amplification of source-body-leakage parasitic bipolar transistor, the electron amount that drain region 9 is collected greatly reduces, and effectively inhibits single-particle radiation-induced SOI device single-particle inversion and single-ion transient state effect.Further, since extension area, source 8 is positioned at below semiconductor body 3, adding the delivery pathways of minority carrier, exist only in tunnel-through diode compared with the structure below source electrode, the release time of minority carrier is shorter, and the electromotive force of semiconductor body 3 is more stable.Stable semiconductor body electromotive force makes source-body junction diode be not at forward bias, this also means that the source-body-leakage bipolar transistor of parasitism is not at amplification mode, and therefore the enlarge-effect of parasitic transistor is effectively suppressed.
Below by illustrating that as a example by nmos device the anti-single particle transient state of above-described embodiment reinforces the preparation method of SOI device, comprise the steps:
A1, prepares part depletion SOI Substrate, as it is shown in figure 1, include p-type top silicon surface 31, the oxygen buried layer 2 of earth silicon material and Semiconductor substrate 1.
A2, carry out photoetching for the first time, it is formed with source region 3, it is etched with the top silicon surface 31 beyond source region 3, for etching barrier layer, the top silicon surface 31 beyond active area 3 is etched away completely with oxygen buried layer 2, carry out the deposit of oxide (for silicon dioxide in this specific embodiment), fill the groove that etching is formed, form shallow trench isolation 4, as shown in Figure 2.
A31, carry out second time photoetching, it is etched with the oxygen buried layer 2 of the top silicon surface 31 and 20nm degree of depth of source region 3, the width of etching is 120nm, and the groove that deposit single crystal silicon material filling is etched, as the identical height of top silicon surface 31, utilizes boron ion implanting to carry out heavy doping, control energy and the dosage of ion implanting, the monocrystal silicon in oxygen buried layer 2 groove is made to form heavily doped region, as extension area, source 8, as shown in Figure 3.
A32, after depositing the thin dielectric film of silicon dioxide thick for one layer of 1.2nm and the gate material of the much higher crystal silicon of 130nm, carries out third time photoetching, is formed and include gate medium 6 and the grid region of gate electrode 5, as shown in Figure 4.
A33, utilizes arsenic or phosphorus to use low-energy ion implanting, forms lightly doped LDD region 7, as shown in Figure 5.
A34, after the grid spacer material of deposit layer of silicon dioxide and silicon nitride, utilize the reticle of third time photoetching, after carrying out lithography alignment, carry out photoetching, form grid side wall 11, again carry out after arsenic or phosphonium ion inject the heavily-doped implant carrying out device source district 10 and drain region 9, forming source region 10 and the drain region 9 of device after carrying out rapid thermal annealing activator impurity, as shown in Figure 6, the active area 3 between source region 10 and drain region 9 is semiconductor body.
A35, carries out grid, source, the deposit of drain electrode contact site and etching, forms grid, source, drain electrode contact site, as shown in Figure 7.
For other embodiments structure anti-single particle transient state reinforce SOI device preparation method be referred to above-mentioned preparation method, this no longer describes in detail.
The anti-single particle transient radiation part depletion SOI device structure proposed the present invention underneath with the emulation tool Sentaurus TCAD of synopsis company is verified.Structure and the dopant profiles of the nmos device of part depletion SOI technology is generated first by the actual preparation technology flow process based on device of the process simulation instrument Sprocess in Sentaurus TCAD, as shown in Figure 8, Fig. 8 a is that normal part exhausts SOI device section of structure；Fig. 8 b is the radiation-resistant SOI device architecture profile of the embodiment of the present invention.Sdevice instrument in Sentaurus TCAD instrument is utilized to carry out device simulation, wherein grid, source electrode and drain bias are in zero potential, and the bias drained is VDD (1.2V), the energy value LET of incoming particle is 0.01 pC/ μm, incident direction is perpendicular to device surface from top to bottom, and incident position is positioned at the centre in device drain region.When producing substantial amounts of electron-hole pair on track after particle incidence, electronics is absorbed hole by drain electrode and flows to neutral body district due to diffusion, causes the unlatching of parasitic bipolar transistor.On the left of Fig. 9, vertical coordinate illustrates the drain current variation relation with the time of incidence of three kinds of different components structures, and what right side vertical coordinate was leakage current to the integral representation of time is the quantity of electric charge that absorbs of drain electrode.Wherein structure 1 be the part depletion SOI device that do not has body to contact, structure 2 be utilize sige material to carry out the part depletion SOI device of body contact, structure 3 is the part depletion SOI device of the present invention.From fig. 9, it can be seen that the device architecture of the present invention can significantly suppress the size of leakage current, the particularly peak value of leakage current to be greatly reduced；The electron charge that drain electrode is collected simultaneously the most greatly reduces compared with the device architecture contacted without body contact, SiGe body, and bipolar amplification is only 0.8 times.Therefore it can be concluded that anti-single particle transient state proposed by the invention reinforces the unlatching of the parasitic bipolar transistor that SOI device can effectively suppress, reduce the electric charge that drain terminal is collected, improve its anti-single particle ability.
Although specifically showing in conjunction with preferred embodiment and describing the present invention; but those skilled in the art should be understood that; in the spirit and scope of the present invention limited without departing from appended claims; the present invention can be made a variety of changes in the form and details, be protection scope of the present invention.
Claims (7)
1. an anti-single particle transient state reinforces SOI device, including substrate, oxygen buried layer, semiconductor body, drain region, source region, grid region, grid side wall and LDD region, described oxygen buried layer is positioned at substrate, described semiconductor body, source region and drain region are positioned on oxygen buried layer, and semiconductor body is between source region and drain region, described LDD region be positioned at semiconductor body top, both sides and respectively with source region and drain contact, described grid region is positioned on semiconductor body, two grid side walls lay respectively at the both sides in grid region and on LDD region, it is characterized in that: also include extension area, heavily doped source, extension area, described source contacts source region and semiconductor body simultaneously, and between source region and semiconductor body and oxygen buried layer, the doping type of extension area, described source is contrary with the doping type of source region.
A kind of anti-single particle transient state the most according to claim 1 reinforces SOI device, it is characterized in that: described oxygen buried layer at least part of source region of correspondence and at least part of source region semiconductor body position formed there is the sunk area for being filled with extension area, source, extension area, described source is filled with at this sunk area.
A kind of anti-single particle transient state the most according to claim 1 and 2 reinforces SOI device, it is characterised in that: extension area, described source is positioned at lower section and the lower section in part semiconductor body district of whole source region.
A kind of anti-single particle transient state the most according to claim 1 reinforces SOI device, it is characterised in that: the semi-conducting material of extension area, described source is identical with the material of semiconductor body.
5. the preparation method of the anti-single particle transient state reinforcing SOI device as described in any one of Claims 1-4, it is characterised in that: comprise the steps
A1, prepares SOI Substrate, including substrate, oxygen buried layer and top layer district；
A2, forms shallow trench isolation in top layer district；
A3, prepare extension area, heavily doped source, and preparation grid region, LDD region, grid side wall, semiconductor body, source region and drain region, the source extension area of making contacts source region, semiconductor body simultaneously, and between source region and semiconductor body and oxygen buried layer, the doping type making extension area, source is contrary with the doping type of source region.
Anti-single particle transient state the most according to claim 5 reinforces the preparation method of SOI device, it is characterized in that: described step A3 is prepared extension area, heavily doped source and includes: formed in the position of oxygen buried layer corresponding at least partly source region and at least part of source region semiconductor body and there is the sunk area for being filled with extension area, source, extension area, described source is filled with at this sunk area, prepares extension area, heavily doped source at this sunk area.
Anti-single particle transient state the most according to claim 5 reinforces the preparation method of SOI device, it is characterised in that: in described step A3, the semi-conducting material of extension area, source is identical with the semi-conducting material in top layer district.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101916726A (en) * | 2010-07-06 | 2010-12-15 | 中国科学院上海微系统与信息技术研究所 | Method for manufacturing signal operation instruction (SOI) metal oxide semiconductor (MOS) apparatus structure for restraining floating body effect |
| CN102916047A (en) * | 2012-10-23 | 2013-02-06 | 哈尔滨工程大学 | Contact structure of SOI (silicon-on-insulator) body and forming method of contact structure based on buried oxide corrosion technology |
| US20150349120A1 (en) * | 2014-05-29 | 2015-12-03 | Globalfoundries Inc. | Semiconductor device structure |
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- 2016-06-03 CN CN201610391993.9A patent/CN105977196A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101916726A (en) * | 2010-07-06 | 2010-12-15 | 中国科学院上海微系统与信息技术研究所 | Method for manufacturing signal operation instruction (SOI) metal oxide semiconductor (MOS) apparatus structure for restraining floating body effect |
| CN102916047A (en) * | 2012-10-23 | 2013-02-06 | 哈尔滨工程大学 | Contact structure of SOI (silicon-on-insulator) body and forming method of contact structure based on buried oxide corrosion technology |
| US20150349120A1 (en) * | 2014-05-29 | 2015-12-03 | Globalfoundries Inc. | Semiconductor device structure |
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