CN102412266B

CN102412266B - Power device structure capable of improving safety operation region (SOA) capacity and manufacturing method

Info

Publication number: CN102412266B
Application number: CN201110310516.2A
Authority: CN
Inventors: 王雷
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2011-10-13
Filing date: 2011-10-13
Publication date: 2014-12-10
Anticipated expiration: 2031-10-13
Also published as: CN102412266A

Abstract

The invention discloses a power device structure capable of improving safety operation region (SOA) capacity, and a manufacturing method thereof. The power device is provided with a high-voltage-resistant first semiconductor substrate region, and a second semiconductor body region and a first semiconductor active region on the first semiconductor substrate region; a drain region is led out of a back; the front surface of a silicon wafer is provided with a groove which is embedded into a body and is filled with second semiconductor polycrystalline silicon directly connected with a substrate; a side wall is connected with the active region and a body region; a second semiconductor region which is arranged below the active region is separated from the body region, and the concentration of the second semiconductor region is higher than that of the body region; and the depth of the active region embedded into the groove edge is consistent with the concentration and the depth of other regions in the horizontal direction, and an obvious cylindrical surface distribution structure formed by dispersing does not exist. The power device structure can reduce a cellar area, improve SOA capacity and reduce manufacturing cost.

Description

Improve power unit structure and the manufacture method thereof of SOA ability

Technical field

The present invention relates to power unit structure and manufacture method in microelectronic chip manufacture field

Background technology

For power component, except normal service area, there are two regions of easily losing efficacy, when device opens and shuts off.Now because the response speed of power device is conventionally all slower, therefore intensifying current or minimizing lag behind the variation of voltage, therefore in the situation of opening or shutdown moment can exist large voltage and large electric current to inject, now device itself must have certain resistivity to it, can within the time of opening or turn-off, not burn device, this ability is commonly referred to SOA (ESD protection area, Safety Operation Area).The SOA ability of device has directly restricted the maximum breakdown voltage of device, operating current and switching speed.

As shown in Figure 2, improve the SOA ability of device, essence is exactly how to avoid the component failure that under high pressure, large electric current injection effect causes, by suppressing, hole, drain region is injected and start with in electronic injection two aspects in source region conventionally.Suppress the hole charge in drain region and inject, conventionally adopt and introduce a very dark deep p+body region and be connected with substrate, strengthen the capacity gauge of hole charge, when suppressing to open or turn-offing at the bottom of the MOS inefficacy while injecting of the large electric current in hole; Suppressing the electronic injection in source region is to intercept in the vertical direction n+source and p-body by introduce a shallow p+body below n+ source region, and when when preventing from opening or turn-offing, large electric current injects, channel region exhausts and causes electron charge directly and substrate is ganged up inefficacy to substrate.

In actual production manufacture process, deep p+body needs the extra light shield that uses, and in order to prevent the impact of deep p+body on n+source, need to reserve certain safety zone.And deep p+body, n+source can be horizontal wealthy in thermal process, especially deep p+body requires very dark, that just mean horizontal wealthy also can be very large, therefore while design, need to reserve very large space, prevent that deep p+body is diffused into n+source, greatly affect device area, also can have a certain impact to device performance simultaneously.

The simultaneously introducing of p+ buried regions neither very easily, especially, in the situation that using deep p+body, be difficult to control the degree of depth and the horizontal direction of p+ buried regions, once that p+ buried regions is crossed is deeply excessively shallow, or does not encase n+ source region, its effect will significantly decline.

Summary of the invention

Technical problem to be solved by this invention is to provide a kind of power unit structure and manufacture method thereof of the SOA of raising ability, and it can dwindle cell density, improves SOA ability, reduces manufacturing cost.

In order to solve above technical problem, the invention provides a kind of power unit structure of the SOA of raising ability, there is a high voltage bearing first type semiconductor substrate region, the Second-Type semiconductor body on it and the first type semiconductor source region, draw from the back side in drain region; At front side of silicon wafer, there is a groove of imbedding in body, be Second-Type polycrystalline silicon semiconductor, be directly connected with substrate, sidewall is connected with tagma with source region; There are a Second-Type semiconductor regions and tagma isolation in below, source region, and its concentration ratio tagma is high; Source region its degree of depth of the slot wedge of imbedding in the horizontal direction with other regional concentrations, the degree of depth is consistent, and does not have the cylindrical distributed architecture significantly diffuseing to form.

Beneficial effect of the present invention is: dwindle cell density, improve SOA ability, reduce manufacturing cost.

Trench area sidewall can, by growth dielectric film, prevent the impact of p+ district on n+ source region.

Heavy doping injection can be carried out in bottom, trench area, and raising contacts with substrate.

Trench area can utilize side wall layer to carry out self aligned p+ to imbed the formation in district.

Spacer material can be SiO2, or SiN.

The 1 layer of hard mask layer of can growing up above polysilicon, its material has the ratio of selection in dry method or wet etching with side wall layer.

The present invention also provides a kind of manufacture method of power unit structure of the SOA of raising ability, comprises the following steps:

On substrate, produce gate oxide and polysilicon gate layer;

Polysilicon gate layer photoetching etching;

Utilize oblique angle to inject and produce tagma, and anneal and expand calculation;

Utilize oblique angle to inject the vertical exclusion region and the source region that produce source region and tagma, and anneal and spread;

Growth hard mask layer, chemical wet etching produces trench area;

Fill p+ polysilicon, and return quarter.

Brief description of the drawings

Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.

Fig. 1 is the power unit structure schematic diagram of this patent;

Fig. 2 is traditional power unit structure schematic diagram;

Fig. 3 a-Fig. 3 f is the schematic flow sheet of the method for the invention.

Description of reference numerals in figure:

1n-drift region, 2p+ polysilicon is imbedded district, 3p+ buried regions, 4n+ source region, 5p tagma, 6 grid oxygen, 7 grid, 9 side walls

Embodiment

As shown in Figure 1, Figure 3, this patent is taking the first type semiconductor as n, and Second-Type semiconductor is that p gives an example

1) choose N-shaped substrate, growth SIO2 and polysilicon gate, SiO2 thickness 10A～2000A, polysilicon gate thickness 500A～2um, according to the Vt of device MOS device, Ion, resistances etc. require and determine.The hard mask layer of growing above polysilicon gate, is SiN in this example, and side wall is SiO2, ensures both material differences, has etching selection ratio.Hard mask layer thickness is 200A～5um.

2) chemical wet etching produces gate patterns.

3) utilize oblique angle rotation to inject and carry out p body injection, its doping can be B or BF, and bulk concentration is 1e12～1e20atom/em3, after completing, anneal, and temperature 650C～1300C, time 1H～100H, visual organ part performance requirement and determining.

4) utilize equally oblique angle rotation to inject and carry out the injection of p+ buried regions, its doping type can be identical with p body, and concentration ratio body is high 2 more than the order of magnitude.But depth ratio body wants shallow 500A～2um, thinner thickness, 500A～2um.Then proceed the injection of n+source, its doping can be P, As etc., bulk concentration 1e14～1e24atom/cm3, and more shallow than buried regions, need to be above body, occur overlapping, but can not be too thick, crossover region thickness is for suitable between 100A～5000A.The activation of annealing afterwards, taking rta technique as good, temperature 650C～1000C, time 10s～30min.

5) deposition side wall layer material, in this example taking SiO2 as example, thickness 1000A～5um, its lateral thickness need be greater than the design rule in minimum source region.The comprehensive etching of dry method is exposed silicon substrate.

6) taking the hard mask layer of remaining side wall layer and polysilicon top as barrier layer, etch silicon substrate produces trench area, and its degree of depth is greater than tagma.

7) fill p-type polysilicon, it is doped to B or BF, and bulk concentration 1e18～1e24atom/cm3 returns and carves comprehensively

When source region, design rule minimum value is excessive, and such as 2um is when above, side wall is blocked up, now can consider to define trench area with photolithography plate in step 5.

In order to strengthen the capacity gauge of p-type groove to hole, can after completing, step 6 carry out the once injection of bottom, improve the contact resistance of groove and substrate.

In order further to avoid the impact of p-type polycrystalline on n+source, can after completing, step 6 deposit one deck SiO2 as buffer compartment absciss layer, now need to add again once to return to carve that the silicon of channel bottom is exposed, ensure that substrate is connected with groove.

The present invention is not limited to execution mode discussed above.Above the description of embodiment is intended in order to describe and illustrate the technical scheme the present invention relates to.Apparent conversion based on the present invention enlightenment or substitute and also should be considered to fall into protection scope of the present invention.Above embodiment is used for disclosing best implementation method of the present invention, to make those of ordinary skill in the art can apply numerous embodiments of the present invention and multiple alternative reaches object of the present invention.

Claims

1. a power unit structure that improves SOA ability, is characterized in that,

There is a high voltage bearing first type semiconductor substrate region, the Second-Type semiconductor body on it and the first type semiconductor source region, draw from the back side in drain region;

At front side of silicon wafer, there is a groove of imbedding in body, be Second-Type polycrystalline silicon semiconductor, be directly connected with substrate, sidewall is connected with tagma with source region;

There are a Second-Type semiconductor regions and tagma isolation in below, source region, and its concentration ratio tagma is high;

Source region is consistent with other regional concentrations of source region in the horizontal direction in the concentration of the slot wedge of imbedding, and does not have the cylindrical distributed architecture significantly diffuseing to form.

2. the manufacture method of the power unit structure of raising SOA ability as claimed in claim 1, is characterized in that, comprises the following steps:

On substrate, produce gate oxide and polysilicon gate layer, with and on hard mask layer;

Polysilicon gate layer photoetching etching;

Chemical wet etching produces groove;

Fill p+ polysilicon, and return quarter.

3. the power unit structure of raising SOA ability according to claim 1, is characterized in that, trenched side-wall, by growth dielectric film, prevents the impact of Second-Type polycrystalline silicon semiconductor on the first type semiconductor source region.

4. the power unit structure of raising SOA ability according to claim 1, is characterized in that, channel bottom carries out a heavy doping and injects, and raising contacts with substrate.

5. the power unit structure of raising according to claim 1 SOA ability, is characterized in that, groove utilizes side wall layer to carry out self aligned p+ to imbed the formation in district.

6. the power unit structure of raising SOA ability according to claim 5, is characterized in that, spacer material is SiO2, or SiN.

7. the power unit structure of raising SOA ability according to claim 1, is characterized in that, the 1 layer of hard mask layer of growing up above polysilicon, and its material has the ratio of selection in dry method or wet etching with side wall layer.