CN102412208B - Chip-scale package and fabrication method thereof - Google Patents
Chip-scale package and fabrication method thereof Download PDFInfo
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- CN102412208B CN102412208B CN201010292081.9A CN201010292081A CN102412208B CN 102412208 B CN102412208 B CN 102412208B CN 201010292081 A CN201010292081 A CN 201010292081A CN 102412208 B CN102412208 B CN 102412208B
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- packing colloid
- conductive projection
- size package
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention discloses a chip-scale package and a fabrication method thereof. The chip-scale package comprises a packaging colloid, conductive bumps, a chip, a dielectric layer, a circuit layer, conductive blind holes and a soldering-resistant layer, the packaging colloid is provided with a first surface and a second surface which are opposite from each other, the conductive bumps are arranged in the packaging colloid and exposed out of the first and the second surfaces of the packaging colloid, the chip is embedded in the packaging colloid and exposed out of the first surface of the packaging colloid, the dielectric layer is arranged on the first surface of the packaging colloid, the conductive bumps and the chip, the circuit layer is arranged on the dielectric layer, the conductive blind holes are arranged in the dielectric layer and electrically connected with the circuit layer, electrode pads and the conductive bumps, and the soldering-resistant layer is arranged on the dielectric layer and the circuit layer. Consequently, the conductive bumps can be directly connected with other external electronic devices, so that a stack structure can be formed, and the fabrication process is effectively simplified.
Description
Technical field
The present invention relates to a kind of packaging part and method for making thereof, particularly relate to a kind of chip size package and method for making thereof.
Background technology
Along with the evolution of semiconductor technology, semiconductor product has been developed different encapsulating products kenels, and be pursue semiconductor package part compact, thereby develop a kind of chip size package (chip scale package, CSP), it is characterized in that this kind of chip size package only has equates with chip size or bigger size.
United States Patent (USP) the 5th, 892,179,6,103,552,6,287,893,6,350,668 and 6,433, a kind of traditional CSP structure is disclosed for No. 427, be directly on chip, to form to increase layer and without using as the chip bearing member such as substrate or lead frame, and utilize the electronic pads that reroutes on (redistribution layer, RDL) technology reprovision chip extremely to want position.
But the shortcoming of above-mentioned CSP structure is using of the technology of rerouting or the conductive trace that is laid on chip is often limited to the size of chip or the size of its acting surface, especially when in the situation that integrated level promotes and chip size dwindles increasingly of chip, chip even cannot provide enough surfaces to settle the soldered ball of greater number to come to be electrically connected with extraneous.
In view of this, United States Patent (USP) the 6th, discloses the method for making of a kind of crystal wafer chip dimension encapsulation part WLCSP (Wafer Level CSP) for 271, No. 469, be on chip, to form the packaging part that increases layer, can provide comparatively sufficient surf zone to carry more input/output terminal or soldered ball.
As shown in Figure 1A, prepare a glued membrane 11, and multiple chips 12 are pasted on this glued membrane 11 with acting surface 121, this glued membrane 11 is for example thermoinduction glued membrane; As shown in Figure 1B, carry out Encapsulation Moulds compression technology, utilize just like the packing colloid 13 of epoxy resin and envelope non-acting surface 122 and the side of chip 12, then heating removes this glued membrane 11, to expose outside this chip acting surface 121; As shown in Figure 1 C, then utilize (RDL) technology that reroutes, lay a dielectric layer 14 on the acting surface 121 of chip 12 and the surface of packing colloid 13, and offer multiple openings that run through dielectric layer 14 with the electronic pads 120 on exposed chip, then on this dielectric layer 14, form line layer 15, and make line layer 15 be electrically connected to electronic pads 120, then on line layer 15, lay and refuse layer 16 and line layer 15 precalculated positions plant soldered ball 17, carry out afterwards cutting operation.
By aforementioned technique, because the surperficial of packing colloid 13 of coated this chip 12 must can settle more soldered ball 17 effectively to reach and extraneous electric connection for the surf zone large compared with these chip 12 acting surfaces 121.
But, the shortcoming of above-mentioned manufacturing process is this chip 12 to be pasted on this glued membrane 11 and fixing mode with its acting surface 121, often because being heated in manufacturing process, this glued membrane 11 there is flexible problem, cause sticky chip 12 positions that are placed on this glued membrane 11 to be offset, even in the time of encapsulation mold pressing, because being subject to thermal softening, this glued membrane 11 causes this chip 12 displacements, so cause follow-up in the time rerouting technique, this line layer 15 cannot be connected on these chip 12 electronic padses 120, thereby causes electrically bad.
Refer to Fig. 2, in another encapsulation mold pressing, because glued membrane 11 ' heat is softened, easily there is the acting surface 121 of glue 130 to this chip 12 that overflow in this packing colloid 13, even pollute this electronic pads 120, cause line layer and the loose contact of chip electrode pad of the follow-up technique that reroutes, and cause waste product problem.
Refer to Fig. 3 A, aforementioned Encapsulation Moulds compression technology only supports multiple chips 12 by this glued membrane 11, easily there are serious warpage (warpage) 110 problems in this glued membrane 11 and packing colloid 13, especially in the time of the very thin thickness of this packing colloid 13, warpage issues is by even more serious, thereby cause follow-up rerouting when technique, be coated with this dielectric layer 14 on this chip 12 time, have uneven thickness problem; So, need additionally to provide again a hard carrier 18 (as shown in Figure 3 B), so that being fixed on to this hard carrier 18 by a viscose glue 19, this packing colloid 13 flattens, but when completing when rerouting technique and removing this carrier 18, easily residual viscose glue 190 (as shown in Figure 3 C) on this packing colloid 13.Disclosing as United States Patent (USP) the 6th, 498,387,6,586,822,7,019,406 and 7,238, No. 602 of other related art.
Moreover, as shown in Figure 3 D, if this packaging part is wanted to carry out when stacking, need first run through this packing colloid 13, carry out thereafter packing colloid 13 perforation technique (TMV, Through Mold Via), to form multiple through holes that run through, be coated with into filled conductive material 100 in this through hole to electroplate or to change again afterwards, thereby form multiple conductive through holes 10, on this conductive through hole 10, form soldered ball 17 ' again, for connecing the electronic installation 1 of putting as another packaging part.But, run through the manufacturing process difficulty of this packing colloid 13, and need fill this electric conducting material 100 while forming this conductive through hole 10, so that manufacturing time increases, and cost improves.
Therefore, how to provide a kind of chip size package and method for making, can avoid the defect of aforementioned prior art, and then guarantee the electric connection quality between line layer and electronic pads, and the reliability of improving product, reduce manufacturing cost, be an important topic in fact.
Summary of the invention
The object of the invention is to guarantee the electric connection quality between line layer and electronic pads, and the reliability of improving product, manufacturing cost reduced.
For achieving the above object, the invention provides a kind of chip size package, comprising: packing colloid, has relative first surface and second surface; Conductive projection, is located in this packing colloid and exposes on the first surface and second surface of this packing colloid; Chip, is embedded in this packing colloid, and this chip has relative acting surface and non-acting surface, has multiple electronic padses on this acting surface, and makes this acting surface expose to the first surface of this packing colloid; Dielectric layer, is located on the acting surface of first surface, this conductive projection and this chip of this packing colloid; Line layer, is located on this dielectric layer; Conductive blind hole, is located in this dielectric layer, to make this line layer be electrically connected this electronic pads and this conductive projection by this conductive blind hole; And refuse layer, be located on this dielectric layer and this line layer, and this refuses layer and has the first perforate, to make this line layer of part expose in this first perforate.
In aforesaid packaging part, the material that forms this conductive projection is copper.
In aforesaid packaging part, on this conductive projection, there is metal level, to make this metal level expose to the second surface of this packing colloid, thereby be located on this metal level exposing for conducting element.
In aforesaid packaging part, the non-acting surface of this chip exposes to the second surface of this packing colloid.
In aforesaid packaging part, this conductive projection flush with the second surface of this packing colloid or the second surface of this packing colloid on there is corresponding the second perforate that exposes this conductive projection, be located on this conductive projection exposing for conducting element.
Aforesaid packaging part also can comprise conducting element, is located on the line layer in this first perforate.
Aforesaid packaging part also can comprise layer reinforced structure, be located on this dielectric layer and this line layer, and this is refused layer and is located on the outermost layer of this layer reinforced structure.
The present invention also provides a kind of method for making of chip size package, comprising: a loading plate is provided, and has adjacent conductive projection and crystalline setting area on this loading plate; Chip is set on the crystalline setting area of this loading plate, this chip has relative acting surface and non-acting surface, and on this acting surface, has multiple electronic padses, and connects and be placed on this loading plate with this acting surface; Form packing colloid on this loading plate, conductive projection and chip, to be coated this chip, and this packing colloid has the second surface that is bonded to the first surface on this loading plate and exposes; Remove this loading plate, to expose the acting surface of first surface, this conductive projection and this chip of this packing colloid; Form dielectric layer on the acting surface of first surface, this conductive projection and this chip of this packing colloid; Form line layer on this dielectric layer, and form conductive blind hole in this dielectric layer, to make this line layer be electrically connected this electronic pads and this conductive projection by this conductive blind hole; Formation is refused layer on this dielectric layer and this line layer, and this refuses layer and have the first perforate, to make this line layer of part expose to this first perforate; And make this conductive projection expose to the second surface of this packing colloid.
In aforesaid method for making, the material that forms this loading plate is copper.
In aforesaid method for making, the manufacturing process that forms this loading plate comprises: a substrate is provided; On this substrate, form resistance layer, and this resistance layer has multiple openings surface of this substrate of exposed portions serve in addition; Remove the part baseplate material in this opening, to make this resistance layer below form this conductive projection; And remove this resistance layer, make remaining baseplate material as this loading plate.
In aforesaid method for making, form metal level on this conductive projection, to make this metal level expose to the second surface of this packing colloid.
According to above-mentioned manufacturing process, the manufacturing process that forms this loading plate comprises: a substrate is provided; Form resistance layer on this substrate, and this resistance layer has multiple openings surface of this substrate of exposed portions serve in addition; Form on the substrate of this metal level in this opening; And remove the part baseplate material of this resistance layer and below thereof, to make this metal level below form this conductive projection, and remaining baseplate material is as this loading plate.
Aforesaid method for making is also included on the acting surface of this chip and is coated with adhesion coating, to make this chip positioning on the crystalline setting area of this loading plate, and when removing after this loading plate, also removes this adhesion coating
In aforesaid method for making, the non-acting surface of this chip exposes to this packing colloid.
Aforesaid method for making also comprises the packing colloid removing on this conductive projection, makes this conductive projection and the second surface of this packing colloid flush or be included in and on the second surface of this packing colloid, forms corresponding the second perforate that exposes this conductive projection.
Aforesaid method for making also can comprise formation layer reinforced structure, and on this dielectric layer and this line layer, and this is refused layer and is located on the outermost layer of this layer reinforced structure.
As from the foregoing, chip size package of the present invention and method for making are mainly first located at chip on the loading plate with conductive projection, again by coated packing colloid this chip and conductive projection, then remove this loading plate with the technique that reroutes, use avoid prior art by chip directly sticky being placed on glued membrane, there is glued membrane and be subject to thermal softening, packing colloid overflow glue and chip offset and pollution problem, even cause line layer and the electronic pads loose contact of the follow-up technique that reroutes, cause the problem of waste product.
Moreover, increasing support force by conductive projection, thus can avoid taking glued membrane as strutting piece, warpage issues occurring in existing manufacturing process, and can avoid the problem of residual viscose glue on packing colloid.
Again, by the design of conductive projection, with wanting to carry out when stacking, directly external other electronic installations, do not need to form conductive through hole as the packing colloid that runs through of prior art, thus the effective simplified manufacturing technique of the present invention, and because of without filled conductive material, and effectively reduce manufacturing time, and reduce costs.
Brief description of the drawings
Figure 1A to Fig. 1 C is US Patent No. 6,271, the method for making schematic diagram of 469 disclosed crystal wafer chip dimension encapsulation parts;
Fig. 2 is US Patent No. 6,271, and the schematic diagram of excessive glue problem occurs 469 disclosed crystal wafer chip dimension encapsulation parts;
Fig. 3 A to Fig. 3 D is US Patent No. 6,271,469 disclosed crystal wafer chip dimension encapsulation part generation packing colloid warpages, sets up carrier, packing colloid surface cull and is difficult for the schematic diagram of the problem such as stacking;
Fig. 4 A to Fig. 4 H is the schematic diagram of chip size package of the present invention and method for making thereof, wherein, Fig. 4 A ' is another execution mode of Fig. 4 A, Fig. 4 F ' is for forming the method for making schematic diagram of layer reinforced structure, Fig. 4 G ' and Fig. 4 G " be respectively the different execution modes of Fig. 4 G, Fig. 4 H ' and Fig. 4 H " be respectively the different execution modes of Fig. 4 H;
The schematic diagram of the manufacturing process of the conductive projection that Fig. 5 A to Fig. 5 C is chip size package of the present invention, wherein, Fig. 5 A ' is another execution mode of Fig. 5 A to Fig. 5 C to Fig. 5 C '.
Main element symbol description:
1,29 electronic installations
10 conductive through holes
100 electric conducting materials
11,11 ' glued membrane
110 warpages
12,22 chips
120,220 electronic padses
121,22a acting surface
122, the non-acting surface of 22b
13 packing colloids
130 excessive glue
14,24 dielectric layers
15,25 line layers
16,26 refuse layer
17,17 ' soldered ball
18 carriers
19 viscose glues
190 residual viscose glues
20 loading plates
20a metal level
200,200 ' conductive projection
21 adhesion coatings
23,23 ' packing colloid
23a first surface
23b, 23b ' second surface
230 second perforates
240 blind holes
25 ' layer reinforced structure
250 conductive blind holes
260 first perforates
27,28 conducting elements
30 substrates
31 resistance layers
310 openings
A crystalline setting area
H distance
Embodiment
By particular specific embodiment, embodiments of the present invention are described below, those skilled in the art can understand other advantages of the present invention and effect easily by content disclosed in the present specification.
Notice, appended graphic the illustrated structure of this specification, ratio, size etc., all contents in order to coordinate specification to disclose only, for those skilled in the art's understanding and reading, not in order to limit the enforceable qualifications of the present invention, therefore the not technical essential meaning of tool, the adjustment of the modification of any structure, the change of proportionate relationship or size, not affecting under effect that the present invention can produce and the object that can reach, all should still drop on disclosed technology contents and obtain in the scope that can contain.Simultaneously, in this specification, quote as " on ", the term such as " end face " and " ", also only for ease of understanding of narrating, but not in order to limit the enforceable scope of the present invention, the change of its relativeness or adjustment, changing under technology contents, when being also considered as the enforceable category of the present invention without essence.
Referring to Fig. 4 A to Fig. 4 H, is the method for making of a kind of chip size package provided by the invention.
As shown in Figure 4 A, provide a loading plate 20, and on this loading plate 20, have adjacent multiple conductive projections 200 and a crystalline setting area A, forming again this loading plate 20 is the materials that can be copper.
As shown in Fig. 4 A ', also can form metal level 20a on the end face of this conductive projection 200, and form the material of this metal level 20a for one or the laminated construction of nickel, palladium, golden institute cohort group.
As shown in Figure 4 B, a chip 22 is set upper in the crystalline setting area of this loading plate 20 A, this chip 22 has relative acting surface 22a and non-acting surface 22b, and on this acting surface 22a, has multiple electronic padses 220, and connects and be placed on this loading plate 20 with this acting surface 22a.In the present embodiment, be to be coated with adhesion coating 21 on this acting surface 22a, to reach this chip 22 in conjunction with being fixed on the object on this loading plate 20, but be not limited in this way.
As shown in Figure 4 C, form packing colloid 23 on this loading plate 20, this conductive projection 200 and this chip 22, to be coated this chip 22, and this packing colloid 23 has the second surface 23b that is bonded to the first surface 23a on this loading plate 20 and exposes.In the present embodiment, the non-acting surface 22b of this packing colloid 23 coated these chips 22, and distance h between this conductive projection 200 and the second surface 20b of this packing colloid 23 is 10 to 50 μ m, but be not limited to this scope.
As shown in Figure 4 D, etching removes this loading plate 20, to expose first surface 23a and this conductive projection 200 of this packing colloid 23, then removes this adhesion coating 21 with chemical liquid, to expose the acting surface 22a of this chip 22.
The present invention in the time removing this loading plate 20, can be on the first surface 23a of this packing colloid 23 kish material or viscose glue.
As shown in Figure 4 E, (RDL) technique that reroutes, first forms at least one dielectric layer 24 on the acting surface 22a of first surface 23a, this conductive projection 200 and this chip 22 of this packing colloid 23.Then, form multiple blind holes 240 in this dielectric layer 24, to expose outside this conductive projection 200 and electronic pads 220.Carry out again patterning step, to form conductive blind hole 250 in this blind hole 240, and form line layer 25 on this conductive blind hole 250 and on dielectric layer 24, to make this line layer 25 be electrically connected this electronic pads 220 and this conductive projection 200 by this conductive blind hole 250.
As shown in Fig. 4 F, form one and refuse layer 26 on this dielectric layer 24 and line layer 25, and this is refused layer 26 and has multiple the first perforates 260, expose to this first perforate 260 with this line layer 25 of order part, thereby in subsequent technique, form as on the line layer 25 of the conducting element 27 of soldered ball in this first perforate 260, for example, with external other electronic installations: circuit board, semiconductor chip.
As shown in Fig. 4 F ', also can first form layer reinforced structure 25 ' on this dielectric layer 24 and line layer 25, this being refused to layer 26 is located on the outermost layer of this layer reinforced structure 25 ' again, outermost layer circuit with this layer reinforced structure 25 ' of order part exposes to this first perforate 260, thereby for forming on the circuit of conducting element 27 in this first perforate 260.This layer reinforced structure 25 ' has at least one dielectric layer, is located at the circuit on this dielectric layer and is located in this dielectric layer and is electrically connected the conductive blind hole of this line layer 25 and circuit again.
As shown in Figure 4 G, use the mode of laser drill, on the second surface 23b of this packing colloid 23, form the second perforate 230, to make this conductive projection 200 expose on the second surface 23b of this packing colloid 23.In other embodiments, also can form another layer reinforced structure in the upper (not shown) of the second surface 23b of this packing colloid 23.
As shown in Fig. 4 H, form as on the conductive projection 200 of the conducting element 28 of soldered ball in this second perforate 230, for example, for external other electronic installations 29: circuit board or another packaging part.
The present invention is by the design of this conductive projection 200, when wanting to carry out when stacking, can be by directly external other electronic installations 29 of soldered ball, do not need as prior art run through this packing colloid with form conductive through hole, therefore the present invention can simplified manufacturing technique, and without filled conductive material, effectively reduce manufacturing time, and reduce costs.
An embodiment therein, as shown in Fig. 4 G ' and Fig. 4 H ', if with sequentially above-mentioned manufacturing process of the structure shown in Fig. 4 A ', this metal level of military order 20a exposes on the second surface 23b of this packing colloid 23, upper to form the metal level 20a of this conducting element 28 in this second perforate 230, thereby for external this electronic installation 29.
In another embodiment, as Fig. 4 G " and Fig. 4 H " as shown in, remove the packing colloid 23 on the non-acting surface 22b of this conductive projection 200 ' and this chip 22, to make remaining packing colloid 23 ' form new second surface 23b ', make the non-acting surface 22b of this conductive projection 200 ' and this chip 22 expose to the new second surface 23b ' of this packing colloid 23 ', can be provided as the use of heat radiation with the non-acting surface 22b that makes this chip 22, and make conductive projection 200 ' flush with the new second surface 23b ' of this packing colloid 23 '.Therefore, about how the non-acting surface of this conductive projection or this chip exposes to the mode of this packing colloid, can adjust on demand, there is no particular restriction.
The present invention is by being first located at this chip 22 on this loading plate 20, again with coated this chip 22 of this packing colloid 23, then remove this loading plate 20, because of without using as existing glued membrane, and avoided the problems such as the excessive glue of packing colloid that prior art occurs and chip pollution.
Moreover, the present invention is located at this chip 22 on this loading plate 20 with this acting surface 22a, can be as there is not flexible problem because glued membrane is heated in prior art, therefore this chip 22 can not be offset, and in the time of encapsulation mold pressing, this loading plate 20 is because not being subject to thermal softening, therefore this chip 22 also can not produce displacement.Therefore,, in the time rerouting technique, the electronic pads 220 of this line layer 25 and chip 22 can loose contact, effectively avoids waste product problem.
Again, the present invention, by form this conductive projection 200 on this loading plate 20, to increase support force, and makes overall structure that warpage can not occur, effectively avoid the problem as there is warpage in existing manufacturing process taking glued membrane as support portion, therefore this chip 22 can not be offset.Therefore,, in the time rerouting technique, this line layer 25 and electronic pads 220 can loose contacts, effectively avoid waste product problem.
The present invention also provides a kind of chip size package, comprise: there is relative first surface 23a and the packing colloid 23 of second surface 23b, be located in this packing colloid 23 and expose to first and second surperficial 23a of this packing colloid 23, the conductive projection 200 of 23b, be located in this packing colloid 23 and expose to the chip 22 of the first surface 23a of this packing colloid 23a, be located at the first surface 23a of this packing colloid 23, dielectric layer 24 on this conductive projection 200 and this chip 22, be located at the line layer 25 on this dielectric layer 24, be located at the conductive blind hole 250 in this dielectric layer 24, and be located at and refuse layer 26 on this dielectric layer 24 and this line layer 25.
The material of described conductive projection 200 is copper, and has the second perforate 230 on the second surface 23b of this packing colloid 23, to make this conductive projection 200 expose to the second surface 23b of this packing colloid 23.Also or, this conductive projection 200 ' flushes with the second surface 23b ' of this packing colloid 23 ', to make this conductive projection 200 ' expose to the second surface 23b ' of this packing colloid 23 '.
Described chip 22 has relative acting surface 22a and non-acting surface 22b, on this acting surface 22a, has electronic pads 220, and makes this acting surface 22a in conjunction with this dielectric layer 24.The non-acting surface 22b of this chip 22 can expose to the second surface 23b ' of this packing colloid 23 ' on demand again.
Described line layer 25 is electrically connected this electronic pads 220 and this conductive projection 200 by this conductive blind hole 250.
The described layer 26 of refusing has the first perforate 260, to make this line layer 25 of part expose in this first perforate 260, thereby for being located on the line layer 25 in this first perforate 260 as the conducting element 27 of soldered ball.
In one embodiment, on this conductive projection 200, there is metal level 20a, to make this metal level 20a expose to the second surface 23b of this packing colloid 23.
Described packaging part also comprises conducting element 28 again, is located on conductive projection that this exposes 200,200 ' maybe on this metal level 20a exposing.
In addition, described packaging part also comprises layer reinforced structure 25 ', be located on this dielectric layer 24 and this line layer 25, and this is refused layer 26 and is located on the outermost layer of this layer reinforced structure 25 '.
Refer to Fig. 5 A to Fig. 5 C, the manufacturing process of formation loading plate 20 is as shown in Figure 4 A provided.
As shown in Figure 5A, first provide a substrate 30, then form resistance layer 31 on this substrate 30, and this resistance layer 31 has multiple openings 310, the surface of this substrate 30 of exposed portions serve in addition.
As shown in Figure 5 B, etching removes part substrate 30 materials in this opening 310, to make these resistance layer 31 belows form this conductive projection 200.
As shown in Figure 5 C, remove this resistance layer 31, make remaining substrate 30 materials as this loading plate 20.
Refer to Fig. 5 A ' to Fig. 5 C ', the manufacturing process that forms the loading plate 20 as shown in Fig. 4 A ' is provided.
As shown in Fig. 5 A ', a substrate 30 is provided, then forms resistance layer 31 on this substrate 30, and this resistance layer 31 has multiple openings 310 surface of this substrate 30 of exposed portions serve in addition.
As shown in Fig. 5 B ', form on the substrate 30 of this metal level 20a in this opening 310.
As shown in Fig. 5 C ', remove part substrate 30 materials of this resistance layer 31 and below thereof, to make this metal level 20a below form this conductive projection 200, and remaining substrate 30 materials are as this loading plate 20.
In sum, chip size package of the present invention and method for making thereof, be the design by conductive projection, when wanting to carry out when stacking, can be by directly external other electronic installations of soldered ball, and effectively simplified manufacturing technique, to reduce manufacturing time and to reduce costs.Moreover the present invention uses loading plate to replace existing glued membrane, effectively avoid the problems such as the excessive glue of packing colloid and chip pollution.
Again, by loading plate, chip is set, and increases integrally-built support force to avoid structure generation warpage by conductive projection, therefore this chip can not be offset, thereby in the time rerouting technique, the electronic pads of this line layer and chip can loose contact, effectively avoids waste product problem.In addition, while removing this loading plate, can be on packing colloid kish material or viscose glue.
Above-described embodiment is in order to illustrative principle of the present invention and effect thereof, but not for limiting the present invention.Any those skilled in the art all can, under spirit of the present invention and category, modify to above-described embodiment.Therefore the scope of the present invention, should be taking the scope of claims as foundation.
Claims (20)
1. a chip size package, is characterized in that, comprising:
Packing colloid, has relative first surface and second surface;
Conductive projection, is located in this packing colloid and exposes on the first surface and second surface of this packing colloid;
Chip, is embedded in this packing colloid, and this chip has relative acting surface and non-acting surface, has multiple electronic padses on this acting surface, and makes this acting surface expose to the first surface of this packing colloid, and this non-acting surface and second surface are positioned at the same side;
Dielectric layer, is located on the acting surface of first surface, this conductive projection and this chip of this packing colloid;
Line layer, is located on this dielectric layer;
Conductive blind hole, is located in this dielectric layer, to make this line layer be electrically connected this electronic pads and this conductive projection by this conductive blind hole; And
Refuse layer, be located on this dielectric layer and this line layer, and this refuses layer and have the first perforate, to make this line layer of part expose in this first perforate.
2. chip size package according to claim 1, is characterized in that, the material that forms this conductive projection is copper.
3. chip size package according to claim 1, is characterized in that, on this conductive projection, has metal level, to make this metal level expose to the second surface of this packing colloid.
4. chip size package according to claim 3, is characterized in that, also comprises conducting element, is located on this metal level exposing.
5. chip size package according to claim 1, is characterized in that, the non-acting surface of this chip exposes to the second surface of this packing colloid.
6. chip size package according to claim 1, is characterized in that, this conductive projection flushes with the second surface of this packing colloid.
7. chip size package according to claim 1, is characterized in that, has correspondence and expose the second perforate of this conductive projection on the second surface of this packing colloid.
8. according to the chip size package described in claim 6 or 7, it is characterized in that, also comprise conducting element, be located on this conductive projection exposing.
9. chip size package according to claim 1, is characterized in that, also comprises conducting element, is located on the line layer in this first perforate.
10. chip size package according to claim 1, is characterized in that, also comprises layer reinforced structure, be located on this dielectric layer and this line layer, and this is refused layer and is located on the outermost layer of this layer reinforced structure.
The method for making of 11. 1 kinds of chip size package, is characterized in that, comprising:
One loading plate is provided, and there is adjacent conductive projection and crystalline setting area on this loading plate;
Chip is set on the crystalline setting area of this loading plate, this chip has relative acting surface and non-acting surface, and on this acting surface, has multiple electronic padses, and connects and be placed on this loading plate with this acting surface;
Form packing colloid on this loading plate, conductive projection and chip, to be coated this chip, and this packing colloid has the second surface that is bonded to the first surface on this loading plate and exposes, and this non-acting surface and second surface are positioned at the same side;
Remove this loading plate, to expose the acting surface of first surface, this conductive projection and this chip of this packing colloid;
Form dielectric layer on the acting surface of first surface, this conductive projection and this chip of this packing colloid;
Form line layer on this dielectric layer, and form conductive blind hole in this dielectric layer, to make this line layer be electrically connected this electronic pads and this conductive projection by this conductive blind hole;
Formation is refused layer on this dielectric layer and this line layer, and this refuses layer and have the first perforate, to make this line layer of part expose to this first perforate; And
Make this conductive projection expose to the second surface of this packing colloid.
The method for making of 12. chip size package according to claim 11, is characterized in that, the material that forms this loading plate is copper.
The method for making of 13. chip size package according to claim 11, is characterized in that, the technique that forms this loading plate comprises:
One substrate is provided;
On this substrate, form resistance layer, and this resistance layer has multiple openings surface of this substrate of exposed portions serve in addition;
Remove the part baseplate material in this opening, to make this resistance layer below form this conductive projection; And
Remove this resistance layer, make remaining baseplate material as this loading plate.
The method for making of 14. chip size package according to claim 11, is characterized in that, forms metal level on this conductive projection, to make this metal level expose to the second surface of this packing colloid.
The method for making of 15. chip size package according to claim 14, is characterized in that, the technique that forms this loading plate comprises:
One substrate is provided;
Form resistance layer on this substrate, and this resistance layer has multiple openings surface of this substrate of exposed portions serve in addition;
Form on the substrate of this metal level in this opening; And
Remove the part baseplate material of this resistance layer and below thereof, to make this metal level below form this conductive projection, and remaining baseplate material is as this loading plate.
The method for making of 16. chip size package according to claim 11, is characterized in that, the non-acting surface of this chip exposes to this packing colloid.
The method for making of 17. chip size package according to claim 11, it is characterized in that, be also included on the acting surface of this chip and be coated with adhesion coating, to make this chip positioning on the crystalline setting area of this loading plate, and when removing after this loading plate, also remove this adhesion coating.
The method for making of 18. chip size package according to claim 11, is characterized in that, also comprises the packing colloid removing on this conductive projection, and this conductive projection is flushed with the second surface of this packing colloid.
The method for making of 19. chip size package according to claim 11, is characterized in that, is also included in and on the second surface of this packing colloid, forms corresponding the second perforate that exposes this conductive projection.
The method for making of 20. chip size package according to claim 11, is characterized in that, also comprises formation layer reinforced structure, and on this dielectric layer and this line layer, and this is refused layer and is located on the outermost layer of this layer reinforced structure.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| EP3537476A4 (en) * | 2016-11-18 | 2020-01-22 | Huawei Technologies Co., Ltd. | Chip packaging structure and method |
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| TWI517269B (en) * | 2013-09-27 | 2016-01-11 | 矽品精密工業股份有限公司 | Package on package structure and manufacturing method thereof |
| KR20150092881A (en) * | 2014-02-06 | 2015-08-17 | 엘지이노텍 주식회사 | Pcb, package substrate and a manufacturing method thereof |
| TWI582861B (en) * | 2014-09-12 | 2017-05-11 | 矽品精密工業股份有限公司 | Structure of embedded component and manufacturing method thereof |
| DE102014224033A1 (en) * | 2014-11-25 | 2016-05-25 | Robert Bosch Gmbh | Electronic module, in particular for vehicle transmission control unit, with press-contact sandwich module technology |
| CN107170731A (en) * | 2017-05-05 | 2017-09-15 | 华为技术有限公司 | Embedded substrate and its manufacture method |
| TW201926485A (en) * | 2017-11-30 | 2019-07-01 | 南茂科技股份有限公司 | Chip package structure and manufacturing method thereof |
| WO2021142599A1 (en) * | 2020-01-14 | 2021-07-22 | 深圳市大疆创新科技有限公司 | Chip packaging structure and packaging method |
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