CN102412208A - Chip-scale package and fabrication method thereof - Google Patents
Chip-scale package and fabrication method thereof Download PDFInfo
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- CN102412208A CN102412208A CN2010102920819A CN201010292081A CN102412208A CN 102412208 A CN102412208 A CN 102412208A CN 2010102920819 A CN2010102920819 A CN 2010102920819A CN 201010292081 A CN201010292081 A CN 201010292081A CN 102412208 A CN102412208 A CN 102412208A
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- chip
- packing colloid
- conductive projection
- size package
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention discloses a chip-scale package and a fabrication method thereof. The chip-scale package comprises a packaging colloid, conductive bumps, a chip, a dielectric layer, a circuit layer, conductive blind holes and a soldering-resistant layer, the packaging colloid is provided with a first surface and a second surface which are opposite from each other, the conductive bumps are arranged in the packaging colloid and exposed out of the first and the second surfaces of the packaging colloid, the chip is embedded in the packaging colloid and exposed out of the first surface of the packaging colloid, the dielectric layer is arranged on the first surface of the packaging colloid, the conductive bumps and the chip, the circuit layer is arranged on the dielectric layer, the conductive blind holes are arranged in the dielectric layer and electrically connected with the circuit layer, electrode pads and the conductive bumps, and the soldering-resistant layer is arranged on the dielectric layer and the circuit layer. Consequently, the conductive bumps can be directly connected with other external electronic devices, so that a stack structure can be formed, and the fabrication process is effectively simplified.
Description
Technical field
The present invention relates to a kind of packaging part and method for making thereof, particularly relate to a kind of chip size package and method for making thereof.
Background technology
Evolution along with semiconductor technology; Semiconductor product has been developed different encapsulating products kenels; And be pursue semiconductor package part compact; Thereby develop a kind of chip size package (chip scale package CSP), is characterized in that this kind chip size package only has with chip size to equate or bigger size.
United States Patent (USP) the 5th, 892,179,6,103; 552,6,287,893,6,350; 668 and 6,433, No. 427 a kind of traditional CSP structure is promptly disclosed; Be directly on chip, to form to increase layer and need not to use, and utilize and reroute that (redistribution layer, RDL) electronic pads on the technological reprovision chip is extremely desired the position like chip bearing members such as substrate or lead frames.
Yet the shortcoming of above-mentioned CSP structure is the conductive trace of using or being laid on the chip of the technology of rerouting and often is subject to the size of chip or the area size of its acting surface; Especially under the situation that the integrated level of chip promotes and chip size dwindles day by day, chip even can't provide enough surfaces to come to electrically connect with extraneous with the soldered ball of settling greater number.
Reflect this; United States Patent (USP) the 6th, 271 discloses the method for making of a kind of crystal wafer chip dimension packaging part WLCSP (Wafer Level CSP) No. 469; Be on chip, to form the packaging part increase layer, can provide comparatively sufficient surf zone to carry more I/O end or soldered ball.
Shown in Figure 1A, to prepare a glued membrane 11, and a plurality of chips 12 are pasted on this glued membrane 11 with acting surface 121, this glued membrane 11 for example is the thermoinduction glued membrane; Shown in Figure 1B, carry out the Encapsulation Moulds compression technology, utilize the non-acting surface 122 and the side that envelope chip 12 just like the packing colloid 13 of epoxy resin, heating removes this glued membrane 11 again, to expose outside this chip acting surface 121; Shown in Fig. 1 C; Utilize (RDL) technology that reroutes then, lay a dielectric layer 14 on the surface of the acting surface 121 of chip 12 and packing colloid 13, and offer a plurality of openings that run through dielectric layer 14 with the electronic pads on the exposed chip 120; Then on this dielectric layer 14, form line layer 15; And make line layer 15 be electrically connected to electronic pads 120, and on line layer 15, lay again and refuse layer 16 and line layer 15 precalculated positions plant soldered ball 17, carry out cutting operation afterwards.
Through aforementioned technology, because of the packing colloid 13 that coats this chip 12 surperficial can supply can settle more soldered ball 17 effectively to reach and the electric connection in the external world than this chip 12 acting surfaces 121 big surf zones.
But; The shortcoming of above-mentioned manufacturing process is this chip 12 is pasted on this glued membrane 11 and fixing mode with its acting surface 121; Because of this glued membrane 11 is heated flexible problem takes place often in manufacturing process; Cause to glue to place chip 12 positions on this glued membrane 11 to squint, even when the encapsulation mold pressing, cause this chip 12 displacements, so cause follow-up when rerouting technology because of this glued membrane 11 receives thermal softening; This line layer 15 can't be connected on these chip 12 electronic padses 120, thereby causes electrically bad.
See also Fig. 2, in another encapsulation mold pressing, because of glued membrane 11 ' is met thermal softening; This packing colloid 13 is prone to take place the acting surface 121 of excessive glue 130 to this chip 12; Even pollute this electronic pads 120, cause the line layer and the loose contact of chip electrode pad of the follow-up technology that reroutes, and cause the waste product problem.
See also Fig. 3 A; Aforementioned Encapsulation Moulds compression technology only supports a plurality of chips 12 through this glued membrane 11; This glued membrane 11 and packing colloid 13 is prone to take place serious warpage (warpage) 110 problems, and especially when the very thin thickness of this packing colloid 13, warpage issues is with even more serious; Thereby cause follow-up rerouting during technology, on this chip 12, have the uneven thickness problem during this dielectric layer 14 of coating; So promptly need the extra hard carrier 18 (shown in Fig. 3 B) that provides again; So that being fixed on this hard carrier 18 through a viscose glue 19, this packing colloid 13 flattens; But reroute technology and when removing this carrier 18, be prone to residual viscose glue 190 (shown in Fig. 3 C) on this packing colloid 13 when accomplishing.Disclosing of other related art like United States Patent (USP) the 6th, 498,387,6,586,822,7,019,406 and 7,238, No. 602.
Moreover, shown in Fig. 3 D, when desiring to pile up as if this packaging part; Need run through this packing colloid 13 earlier, carry out packing colloid 13 perforation technologies (TMV, Through Mold Via) thereafter; To form a plurality of through holes that run through, be coated with filled conductive material 100 in this through hole to electroplate or to change again afterwards, thereby form a plurality of conductive through holes 10; On this conductive through hole 10, form soldered ball 17 ' again, for connecing the electronic installation of putting like another packaging part 1.But, run through the manufacturing process difficulty of this packing colloid 13, and need fill this electric conducting material 100 when forming this conductive through hole 10, so that manufacturing time increases, and cost improves.
Therefore, how a kind of chip size package and method for making being provided, can avoiding the defective of aforementioned prior art, and then guarantee the electric connection quality between line layer and electronic pads, and promote the reliability of product, reduce manufacturing cost, is an important topic in fact.
Summary of the invention
The objective of the invention is to guarantee the electric connection quality between line layer and electronic pads, and promote the reliability of product, reduce manufacturing cost.
For achieving the above object, the present invention provides a kind of chip size package, comprising: packing colloid has opposite first and second surface; Conductive projection is located in this packing colloid and is exposed on the first surface and second surface of this packing colloid; Chip is embedded in this packing colloid, and this chip has relative acting surface and non-acting surface, has a plurality of electronic padses on this acting surface, and makes this acting surface expose to the first surface of this packing colloid; Dielectric layer is located on the acting surface of first surface, this conductive projection and this chip of this packing colloid; Line layer is located on this dielectric layer; Conductive blind hole is located in this dielectric layer, electrically connects this electronic pads and this conductive projection to make this line layer through this conductive blind hole; And refuse layer, and be located on this dielectric layer and this line layer, and this refuses layer and has first perforate, expose in this first perforate with this line layer of order part.
In the aforesaid packaging part, the material that forms this conductive projection is a copper.
In the aforesaid packaging part, have metal level on this conductive projection, expose to the second surface of this packing colloid to make this metal level, thereby supply conducting element to be located on this metal level that exposes.
In the aforesaid packaging part, the non-acting surface of this chip exposes to the second surface of this packing colloid.
In the aforesaid packaging part, this conductive projection flush with the second surface of this packing colloid or the second surface of this packing colloid on have corresponding second perforate that exposes this conductive projection, be located on this conductive projection that exposes for conducting element.
Aforesaid packaging part also can comprise conducting element, is located on the line layer in this first perforate.
Aforesaid packaging part also can comprise layer reinforced structure, be located on this dielectric layer and this line layer, and this is refused layer and is located on the outermost layer of this layer reinforced structure.
The present invention also provides a kind of method for making of chip size package, comprising: a loading plate is provided, and on this loading plate, has adjacent conductive projection and crystalline setting area; Chip is set on the crystalline setting area of this loading plate, this chip has relative acting surface and non-acting surface, and has a plurality of electronic padses on this acting surface, and connects with this acting surface and to place on this loading plate; Form packing colloid on this loading plate, conductive projection and chip, coating this chip, and this packing colloid has the second surface that is bonded to the first surface on this loading plate and exposes; Remove this loading plate, with the acting surface of the first surface, this conductive projection and this chip that expose this packing colloid; Form dielectric layer on the acting surface of first surface, this conductive projection and this chip of this packing colloid; Form line layer on this dielectric layer, and in this dielectric layer, form conductive blind hole, electrically connect this electronic pads and this conductive projection through this conductive blind hole to make this line layer; Formation is refused layer on this dielectric layer and this line layer, and this refuses layer and have first perforate, exposes to this first perforate with this line layer of order part; And make this conductive projection expose to the second surface of this packing colloid.
In the aforesaid method for making, the material that forms this loading plate is a copper.
In the aforesaid method for making, the manufacturing process that forms this loading plate comprises: a substrate is provided; On this substrate, form the resistance layer, and this resistance layer has the surface of this substrate of exposed portions serve beyond a plurality of openings; Remove the part baseplate material in this opening, should form this conductive projection in resistance layer below with order; And remove this resistance layer, make remaining baseplate material as this loading plate.
In the aforesaid method for making, form metal level on this conductive projection, expose to the second surface of this packing colloid to make this metal level.
According to above-mentioned manufacturing process, the manufacturing process that forms this loading plate comprises: a substrate is provided; Form the resistance layer on this substrate, and this resistance layer has the surface of this substrate of exposed portions serve beyond a plurality of openings; Form on the substrate of this metal level in this opening; And the part baseplate material that removes this resistance layer and below thereof, form this conductive projection to make this metal level below, and remaining baseplate material is as this loading plate.
Aforesaid method for making also is included on the acting surface of this chip and is coated with adhesion coating, is positioned on the crystalline setting area of this loading plate to make this chip, and after removing this loading plate, also removes this adhesion coating
In the aforesaid method for making, the non-acting surface of this chip exposes to this packing colloid.
Aforesaid method for making also comprises the packing colloid that removes on this conductive projection, makes this conductive projection and the second surface of this packing colloid flush or be included in and forms corresponding second perforate that exposes this conductive projection on the second surface of this packing colloid.
Aforesaid method for making also can comprise the formation layer reinforced structure, and on this dielectric layer and this line layer, and this is refused layer and is located on the outermost layer of this layer reinforced structure.
By on can know; Chip size package of the present invention and method for making are main to be located at chip on the loading plate with conductive projection earlier; Again packing colloid is coated this chip and conductive projection, then remove this loading plate, use and avoid prior art that directly sticking the placing of chip glued membrane is taken place on the glued membrane received thermal softening, packing colloid overflow glue and chip offset and pollution problem with the technology that reroutes; Even cause the line layer and the electronic pads loose contact of the follow-up technology that reroutes, cause the problem of waste product.
Moreover, increase support force through conductive projection, be that warpage issues takes place strutting piece so can avoid having now in the manufacturing process, and can avoid the problem of residual viscose glue on packing colloid with the glued membrane.
Again, through the design of conductive projection, with when desiring to pile up; Can directly external other electronic installations; Do not need to form conductive through hole like the packing colloid that runs through of prior art, thus the effective simplified manufacturing technique of the present invention, and because of need not the filled conductive material; And effectively reduce manufacturing time, and reduce cost.
Description of drawings
Figure 1A to Fig. 1 C is a U.S. Pat 6,271, the method for making sketch map of 469 disclosed crystal wafer chip dimension packaging parts;
Fig. 2 is a U.S. Pat 6,271, and the sketch map of excessive glue problem takes place 469 disclosed crystal wafer chip dimension packaging parts;
Fig. 3 A to Fig. 3 D is a U.S. Pat 6,271,469 disclosed crystal wafer chip dimension packaging part generation packing colloid warpages, sets up carrier, packing colloid surface cull and is difficult for the sketch map of problems such as piling up;
Fig. 4 A to Fig. 4 H is the sketch map of chip size package of the present invention and method for making thereof; Wherein, Fig. 4 A ' is another execution mode of Fig. 4 A; Fig. 4 F ' is for forming the method for making sketch map of layer reinforced structure, Fig. 4 G ' and Fig. 4 G " be respectively the different execution modes of Fig. 4 G, Fig. 4 H ' and Fig. 4 H " be respectively the different execution modes of Fig. 4 H;
Fig. 5 A to Fig. 5 C is the sketch map of manufacturing process of the conductive projection of chip size package of the present invention, and wherein, Fig. 5 A ' is another execution mode of Fig. 5 A to Fig. 5 C to Fig. 5 C '.
The main element symbol description:
1,29 electronic installations
10 conductive through holes
100 electric conducting materials
11,11 ' glued membrane
110 warpages
12,22 chips
120,220 electronic padses
121,22a acting surface
122, the non-acting surface of 22b
13 packing colloids
130 excessive glue
14,24 dielectric layers
15,25 line layers
16,26 refuse layer
17,17 ' soldered ball
18 carriers
19 viscose glues
190 residual viscose glues
20 loading plates
The 20a metal level
200,200 ' conductive projection
21 adhesion coatings
23,23 ' packing colloid
The 23a first surface
23b, 23b ' second surface
230 second perforates
240 blind holes
25 ' layer reinforced structure
250 conductive blind holes
260 first perforates
27,28 conducting elements
30 substrates
31 resistance layers
310 openings
The A crystalline setting area
The h distance
Embodiment
Below through particular specific embodiment execution mode of the present invention is described, those skilled in the art can understand other advantages of the present invention and effect easily by the content that this specification disclosed.
Notice; The appended graphic structure that illustrates of this specification, ratio, size etc.;,, be not all in order to limit the enforceable qualifications of the present invention for those skilled in the art's understanding and reading only in order to cooperate the content that specification disclosed; Event is the technical essential meaning of tool not; The adjustment of the modification of any structure, the change of proportionate relationship or size not influencing under effect that the present invention can produce and the purpose that can reach, all should still drop on disclosed technology contents and get in the scope that can contain.Simultaneously; Quoted in this specification as " on ", " end face " reach terms such as " one "; Also be merely be convenient to narrate clear, but not in order to limit the enforceable scope of the present invention, the change of its relativeness or adjustment; Under no essence change technology contents, when also being regarded as the enforceable category of the present invention.
See also Fig. 4 A to Fig. 4 H, be the method for making of a kind of chip size package provided by the invention.
Shown in Fig. 4 A, a loading plate 20 is provided, and on this loading plate 20, has adjacent a plurality of conductive projections 200 and a crystalline setting area A, forming this loading plate 20 again is the materials that can be copper.
Shown in Fig. 4 A ', also can form metal level 20a on the end face of this conductive projection 200, and the material that forms this metal level 20a is one or laminated construction of nickel, palladium, golden institute cohort group.
Shown in Fig. 4 B, a chip 22 is set on the A of the crystalline setting area of this loading plate 20, this chip 22 has relative acting surface 22a and non-acting surface 22b, and has a plurality of electronic padses 220 on this acting surface 22a, and connects with this acting surface 22a and to place on this loading plate 20.In the present embodiment, be coating adhesion coating 21 on this acting surface 22a, combine to be fixed in the purpose on this loading plate 20 to reach this chip 22, but do not exceed in this way.
Shown in Fig. 4 C, form packing colloid 23 on this loading plate 20, this conductive projection 200 and this chip 22, coating this chip 22, and this packing colloid 23 has the second surface 23b that is bonded to the first surface 23a on this loading plate 20 and exposes.In the present embodiment, this packing colloid 23 coats the non-acting surface 22b of these chips 22, and the distance h between the second surface 20b of this conductive projection 200 and this packing colloid 23 is 10 to 50 μ m, but is not limited to this scope.
Shown in Fig. 4 D, etching removes this loading plate 20, and first surface 23a and this conductive projection 200 to expose this packing colloid 23 remove this adhesion coating 21 with chemical liquid again, to expose the acting surface 22a of this chip 22.
The present invention when removing this loading plate 20, can be on the first surface 23a of this packing colloid 23 kish material or viscose glue.
Shown in Fig. 4 E, (RDL) technology that reroutes forms at least one dielectric layer 24 earlier on the acting surface 22a of first surface 23a, this conductive projection 200 and this chip 22 of this packing colloid 23.Then, form a plurality of blind holes 240 in this dielectric layer 24, to expose outside this conductive projection 200 and electronic pads 220.Carry out patterning step again, forming conductive blind hole 250 in this blind hole 240, and form line layer 25, electrically connect this electronic pads 220 and this conductive projections 200 through this conductive blind hole 250 to make this line layer 25 on this conductive blind hole 250 and on the dielectric layer 24.
Shown in Fig. 4 F; Form one and refuse layer 26 on this dielectric layer 24 and line layer 25, and this refuses layer 26 and have a plurality of first perforates 260, expose to this first perforate 260 with this line layer 25 of order part; Thereby supply in subsequent technique; Form on the line layer 25 of conducting element 27 in this first perforate 260 like soldered ball, with external other electronic installations, for example: circuit board, semiconductor chip.
Shown in Fig. 4 F '; Also can form layer reinforced structure 25 ' earlier on this dielectric layer 24 and line layer 25; Again this being refused layer 26 is located on the outermost layer of this layer reinforced structure 25 '; Outermost layer circuit with this layer reinforced structure 25 ' of order part exposes to this first perforate 260, thereby supplies to form on the circuit of conducting element 27 in this first perforate 260.This layer reinforced structure 25 ' has at least one dielectric layer, is located at the circuit on this dielectric layer and is located in this dielectric layer and electrically connects the conductive blind hole of this line layer 25 and circuit again.
Shown in Fig. 4 G, use the mode of laser drill, on the second surface 23b of this packing colloid 23, form second perforate 230, expose on the second surface 23b of this packing colloid 23 to make this conductive projection 200.In other embodiments, also can form another layer reinforced structure and go up (figure does not show) in the second surface 23b of this packing colloid 23.
Shown in Fig. 4 H, form on the conductive projection 200 of conducting element 28 in this second perforate 230 like soldered ball, for external other electronic installations 29, for example: circuit board or another packaging part.
The present invention is through the design of this conductive projection 200; When desiring to pile up, can be through direct external other electronic installations 29 of soldered ball, do not need to run through this packing colloid to form conductive through hole like prior art; But so the present invention's simplified manufacturing technique; And need not the filled conductive material, effectively reduce manufacturing time, and reduce cost.
An embodiment therein; Shown in Fig. 4 G ' and Fig. 4 H '; If with the above-mentioned in regular turn manufacturing process of structure shown in Fig. 4 A '; This metal level of military order 20a exposes on the second surface 23b of this packing colloid 23, forming on the metal level 20a of this conducting element 28 in this second perforate 230, thereby supplies external this electronic installation 29.
In another embodiment; Like Fig. 4 G " and Fig. 4 H " shown in; Remove the packing colloid 23 on the non-acting surface 22b of this conductive projection 200 ' and this chip 22; To make remaining packing colloid 23 ' form new second surface 23b '; Make the non-acting surface 22b of this conductive projection 200 ' and this chip 22 expose to the new second surface 23b ' of this packing colloid 23 ', can be made for usefulness with the non-acting surface 22b that makes this chip 22, and make conductive projection 200 ' flush with the new second surface 23b ' of this packing colloid 23 ' into heat radiation.Therefore, how the non-acting surface of relevant this conductive projection or this chip exposes to the mode of this packing colloid, can adjust on demand, does not have special restriction.
The present invention is through being located at this chip 22 on this loading plate 20 earlier; Coat this chip 22 with this packing colloid 23 again; Then remove this loading plate 20, because of need not to use as existing glued membrane, and be able to avoid problems such as excessive glue of packing colloid that prior art takes place and chip pollution.
Moreover; The present invention is located at this chip 22 on this loading plate 20 with this acting surface 22a; Can be as because of glued membrane is heated flexible problem taking place in the prior art, thus this chip 22 can not squint, and when encapsulating mold pressing; This loading plate 20 is not because of receiving thermal softening, so this chip 22 also can not produce displacement.Therefore, when rerouting technology, the electronic pads 220 of this line layer 25 and chip 22 can loose contact, effectively avoids the waste product problem.
Again; The present invention with the increase support force, and makes overall structure that warpage can not take place through on this loading plate 20, forming this conductive projection 200; Effectively avoid as being the problem that warpage takes place in the support portion with the glued membrane in the existing manufacturing process, so this chip 22 can not squint.Therefore, when rerouting technology, this line layer 25 and electronic pads 220 can loose contacts, effectively avoid the waste product problem.
The present invention also provides a kind of chip size package; Comprise: have opposite first 23a and second surface 23b packing colloid 23, be located in this packing colloid 23 and expose to first and second surperficial 23a of this packing colloid 23, the conductive projection 200 of 23b, be located in this packing colloid 23 and expose to dielectric layer 24 on the chip 22 of the first surface 23a of this packing colloid 23a, the first surface 23a that is located at this packing colloid 23, this conductive projection 200 and this chip 22, be located at line layer 25 on this dielectric layer 24, be located at the conductive blind hole 250 in this dielectric layer 24 and be located at and refuse layer 26 on this dielectric layer 24 and this line layer 25.
The material of described conductive projection 200 is a copper, and has second perforate 230 on the second surface 23b of this packing colloid 23, exposes to the second surface 23b of this packing colloid 23 to make this conductive projection 200.Also or, this conductive projection 200 ' flushes with the second surface 23b ' of this packing colloid 23 ', exposes to the second surface 23b ' of this packing colloid 23 ' to make this conductive projection 200 '.
Described chip 22 has relative acting surface 22a and non-acting surface 22b, has electronic pads 220 on this acting surface 22a, and makes this acting surface 22a combine this dielectric layer 24.The non-acting surface 22b of this chip 22 can expose to the second surface 23b ' of this packing colloid 23 ' on demand again.
Described line layer 25 electrically connects this electronic pads 220 and this conductive projection 200 through this conductive blind hole 250.
The described layer 26 of refusing has first perforate 260, exposes in this first perforate 260 with this line layer 25 of order part, thereby supplies to be located on the line layer 25 in this first perforate 260 like the conducting element 27 of soldered ball.
In one embodiment, have metal level 20a on this conductive projection 200, expose to the second surface 23b of this packing colloid 23 to make this metal level 20a.
Described again packaging part also comprises conducting element 28, is located on this conductive projection that exposes 200,200 ' maybe on this metal level 20a that exposes.
In addition, described packaging part also comprises layer reinforced structure 25 ', be located on this dielectric layer 24 and this line layer 25, and this is refused layer 26 and is located on the outermost layer of this layer reinforced structure 25 '.
See also Fig. 5 A to Fig. 5 C, the manufacturing process of the loading plate 20 of formation shown in Fig. 4 A is provided.
Shown in Fig. 5 A, a substrate 30 is provided earlier, formation resistance layer 31 on this substrate 30, and this resistance layer 31 again has a plurality of openings 310, in addition the surface of this substrate 30 of exposed portions serve.
Shown in Fig. 5 B, etching removes part substrate 30 materials in this opening 310, should form this conductive projection 200 in resistance layer 31 below with order.
Shown in Fig. 5 C, remove this resistance layer 31, make remaining substrate 30 materials as this loading plate 20.
See also Fig. 5 A ' to Fig. 5 C ', the manufacturing process that forms the loading plate 20 shown in Fig. 4 A ' is provided.
Shown in Fig. 5 A ', a substrate 30 is provided, form resistance layer 31 again on this substrate 30, and this resistance layer 31 has the surface of this substrate 30 of exposed portions serve beyond a plurality of openings 310.
Shown in Fig. 5 B ', form on the substrate 30 of this metal level 20a in this opening 310.
Shown in Fig. 5 C ', remove part substrate 30 materials of this resistance layer 31 and below thereof, below making this metal level 20a, form this conductive projection 200, and remaining substrate 30 materials are as this loading plate 20.
In sum, chip size package of the present invention and method for making thereof are the designs through conductive projection, when desiring to pile up, can be through direct external other electronic installations of soldered ball, and effective simplified manufacturing technique is to reduce manufacturing time and to reduce cost.Moreover the present invention uses loading plate to replace existing glued membrane, effectively avoids problems such as excessive glue of packing colloid and chip pollution.
Again, chip is set, and increases integrally-built support force to avoid structure generation warpage through conductive projection through loading plate; So this chip can not squint; Thereby when rerouting technology, the electronic pads of this line layer and chip can loose contact, effectively avoids the waste product problem.In addition, when removing this loading plate, can be on packing colloid kish material or viscose glue.
The foregoing description is in order to illustrative principle of the present invention and effect thereof, but not is used to limit the present invention.Any those skilled in the art all can make amendment to the foregoing description under spirit of the present invention and category.Therefore rights protection scope of the present invention should be foundation with the scope of claims.
Claims (20)
1. a chip size package is characterized in that, comprising:
Packing colloid has opposite first and second surface;
Conductive projection is located in this packing colloid and is exposed on the first surface and second surface of this packing colloid;
Chip is embedded in this packing colloid, and this chip has relative acting surface and non-acting surface, has a plurality of electronic padses on this acting surface, and makes this acting surface expose to the first surface of this packing colloid;
Dielectric layer is located on the acting surface of first surface, this conductive projection and this chip of this packing colloid;
Line layer is located on this dielectric layer;
Conductive blind hole is located in this dielectric layer, electrically connects this electronic pads and this conductive projection to make this line layer through this conductive blind hole; And
Refuse layer, be located on this dielectric layer and this line layer, and this refuses layer and have first perforate, expose in this first perforate with this line layer of order part.
2. chip size package according to claim 1 is characterized in that, the material that forms this conductive projection is a copper.
3. chip size package according to claim 1 is characterized in that, has metal level on this conductive projection, exposes to the second surface of this packing colloid to make this metal level.
4. chip size package according to claim 3 is characterized in that, also comprises conducting element, is located on this metal level that exposes.
5. chip size package according to claim 1 is characterized in that the non-acting surface of this chip exposes to the second surface of this packing colloid.
6. chip size package according to claim 1 is characterized in that, this conductive projection flushes with the second surface of this packing colloid.
7. chip size package according to claim 1 is characterized in that, has second perforate that correspondence exposes this conductive projection on the second surface of this packing colloid.
8. according to claim 6 or 7 described chip size package, it is characterized in that, also comprise conducting element, be located on this conductive projection that exposes.
9. chip size package according to claim 1 is characterized in that, also comprises conducting element, is located on the line layer in this first perforate.
10. chip size package according to claim 1 is characterized in that, also comprises layer reinforced structure, be located on this dielectric layer and this line layer, and this is refused layer and is located on the outermost layer of this layer reinforced structure.
11. the method for making of a chip size package is characterized in that, comprising:
One loading plate is provided, and on this loading plate, has adjacent conductive projection and crystalline setting area;
Chip is set on the crystalline setting area of this loading plate, this chip has relative acting surface and non-acting surface, and has a plurality of electronic padses on this acting surface, and connects with this acting surface and to place on this loading plate;
Form packing colloid on this loading plate, conductive projection and chip, coating this chip, and this packing colloid has the second surface that is bonded to the first surface on this loading plate and exposes;
Remove this loading plate, with the acting surface of the first surface, this conductive projection and this chip that expose this packing colloid;
Form dielectric layer on the acting surface of first surface, this conductive projection and this chip of this packing colloid;
Form line layer on this dielectric layer, and in this dielectric layer, form conductive blind hole, electrically connect this electronic pads and this conductive projection through this conductive blind hole to make this line layer;
Formation is refused layer on this dielectric layer and this line layer, and this refuses layer and have first perforate, exposes to this first perforate with this line layer of order part; And
Make this conductive projection expose to the second surface of this packing colloid.
12. the method for making of chip size package according to claim 11 is characterized in that, the material that forms this loading plate is a copper.
13. the method for making of chip size package according to claim 11 is characterized in that, the technology that forms this loading plate comprises:
One substrate is provided;
On this substrate, form the resistance layer, and this resistance layer has the surface of this substrate of exposed portions serve beyond a plurality of openings;
Remove the part baseplate material in this opening, should form this conductive projection in resistance layer below with order; And
Remove this resistance layer, make remaining baseplate material as this loading plate.
14. the method for making of chip size package according to claim 11 is characterized in that, forms metal level on this conductive projection, exposes to the second surface of this packing colloid to make this metal level.
15. the method for making of chip size package according to claim 14 is characterized in that, the technology that forms this loading plate comprises:
One substrate is provided;
Form the resistance layer on this substrate, and this resistance layer has the surface of this substrate of exposed portions serve beyond a plurality of openings;
Form on the substrate of this metal level in this opening; And
Remove the part baseplate material of this resistance layer and below thereof, form this conductive projection to make this metal level below, and remaining baseplate material is as this loading plate.
16. the method for making of chip size package according to claim 11 is characterized in that, the non-acting surface of this chip exposes to this packing colloid.
17. the method for making of chip size package according to claim 11; It is characterized in that, also be included on the acting surface of this chip and be coated with adhesion coating, be positioned on the crystalline setting area of this loading plate to make this chip; And after removing this loading plate, also remove this adhesion coating.
18. the method for making of chip size package according to claim 11 is characterized in that, also comprises the packing colloid that removes on this conductive projection, and this conductive projection is flushed with the second surface of this packing colloid.
19. the method for making of chip size package according to claim 11 is characterized in that, also is included in and forms corresponding second perforate that exposes this conductive projection on the second surface of this packing colloid.
20. the method for making of chip size package according to claim 11 is characterized in that, also comprises the formation layer reinforced structure, on this dielectric layer and this line layer, and this is refused layer and is located on the outermost layer of this layer reinforced structure.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201010292081.9A CN102412208B (en) | 2010-09-21 | 2010-09-21 | Chip-scale package and fabrication method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201010292081.9A CN102412208B (en) | 2010-09-21 | 2010-09-21 | Chip-scale package and fabrication method thereof |
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| CN102412208A true CN102412208A (en) | 2012-04-11 |
| CN102412208B CN102412208B (en) | 2014-08-13 |
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