CN102403456B - Method for making phase change memory component - Google Patents
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- CN102403456B CN102403456B CN201010288123.1A CN201010288123A CN102403456B CN 102403456 B CN102403456 B CN 102403456B CN 201010288123 A CN201010288123 A CN 201010288123A CN 102403456 B CN102403456 B CN 102403456B
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Abstract
The invention relates to a method for making phase change memory component, which comprises the following steps of: providing a front-end device structure which includes a first dielectric layer and a bottom electrode; etching back to remove the upper part of the bottom electrode, and forming a first opening on the surface of the front-end device structure; forming a filling plug in the first opening; etching back to remove the upper part of the first dielectric layer, and making the upper surface of the filling plug higher than that of the first dielectric layer; isotropically etching the filling plug to reduce line width of the filling plug; forming an insulation layer in a region uncovered with the etched filling plug on the surface of the front-end device structure, and making the upper surface of the insulation layer lower than that of the etched filling plug, or flush with the same; removing the etched filling plug to form a second opening; forming a second dielectric layer and a phase change layer on the insulation layer; and forming a third dielectric layer and a top electrode on the second dielectric layer and the phase change layer.
Description
Technical field
The present invention relates to semiconductor fabrication process, particularly a kind of method of making phase change memory component.
Background technology
The local pyrexia that phase-change material (for example Ge-Sb-Te phase-change material) causes by electric pulse and change its phase into crystalline state and amorphous state, phase change memory component is exactly the semiconductor device that utilizes this characteristic storage binary message.Phase change memory component is the memory based on resistance, and the conversion by phase-change material between crystalline state and amorphous state and the corresponding resistance characteristic that presents low-resistance and high resistant reach the object of storage binary message.In phase change memory component, the memory component of storage binary message comprises phase change layer and electrode.
Fig. 1 is the sectional view of the phase change memory component of prior art.As shown in Figure 1, phase change memory component 100 comprises bottom electrode 101, phase change layer 102 and top electrodes 103.The electric current of the varying strength phase change layer 102 of flowing through, flow through by electric current the thermal effect that phase change layer 102 produces and change phase-change material into amorphous state (RESET state) by crystalline state (SET state), (RESET) operation can reset to phase-change material.And phase-change material is changed into by amorphous state, the operation of crystalline state is corresponding is called set (SET).In the time carrying out SET operation, need to apply voltage or a current impulse long and intensity is medium, make the temperature of phase-change material be elevated to crystallization temperature above, below fusion temperature, and keep the regular hour (being generally greater than 50ns), make phase-change material be converted into crystalline state by amorphous state, become low-resistance from high resistant.In the time carrying out RESET operation, need to apply a short and strong current impulse, electric energy is transformed into heat energy, make more than the temperature of phase-change material is elevated to fusion temperature, through fast cooling just can realize phase-change material by crystalline state to amorphous conversion, become high resistant from low-resistance, thereby realize the memory function based on resistance.
In phase change memory component, phase change layer needs higher temperature from crystalline state to amorphous transition process.Generally, by bottom electrode, phase change layer is heated, top electrodes only plays the effect of interconnection, and therefore, the quality of the heating effect of bottom electrode to phase change layer directly has influence on the read-write speed of phase change memory component.In order to obtain good heating effect, the larger drive current of the general employing of phase change memory component, its write-operation current will reach 1mA left and right, but drive current can not unrestrictedly rise, and large-drive-current can cause the small-sized difficulty of peripheral drive circuit and logical device.Also have a kind of method that improves heating effect to be, dwindle the contact area of bottom electrode and phase change layer, improve contact resistance.But in existing technique, the forming process of bottom electrode is mainly first in interlayer dielectric layer, to form hole, then fills metal.Conventionally the top width in etching formation hole is all greater than bottom width, causes formed bottom electrode to be horn-like, is therefore difficult to further dwindle the contact area between bottom electrode and phase change layer.In addition, due to the restriction of the photo-etching machine exposal limit, only cannot define by photoetching the bottom electrode that meets technological requirement.
Therefore, need a kind of method, by reducing the contact area between bottom electrode and phase change layer, improve the efficiency of heating surface of bottom electrode to phase change layer, thereby improve the read or write speed of phase change memory component.
Summary of the invention
In summary of the invention part, introduced the concept of a series of reduced forms, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
The invention provides a kind of method of making phase change memory component, comprise: front end device architecture a) is provided, described front end device architecture comprises the first dielectric layer and bottom electrode, wherein, described the first dielectric layer surrounds the surrounding of described bottom electrode, and described bottom electrode is exposed to the surface of described front end device architecture; B) eat-back the top of removing described bottom electrode, form the first opening in the surface of described front end device architecture; C) in described the first opening, form and fill connector; D) eat-back the top of removing described the first dielectric layer, make the upper surface of described filling connector higher than the upper surface of remaining the first dielectric layer; E) described in isotropic etching, fill connector, to dwindle the live width of described filling connector; F) region that the filling connector after not being etched on the surface of described front end device architecture covers forms insulating barrier, the upper surface of the filling connector of the upper surface of described insulating barrier after lower than described etching, or with described etching after the upper surface flush of filling connector; G) remove the filling connector after described etching, to form the second opening; H) on described insulating barrier, form the second dielectric layer and phase change layer, wherein, described the second dielectric layer surrounds the surrounding of described phase change layer, described phase change layer be positioned at described bottom electrode directly over, and fill described the second opening; I) on described the second dielectric layer and described phase change layer, form the 3rd dielectric layer and top electrodes, wherein, the surrounding that described the 3rd dielectric layer surrounds described top electrodes, described top electrodes is positioned at the position of aiming at described bottom electrode on described phase change layer.
Preferably, d) step obtain the upper surface of described remaining the first dielectric layer and the lower surface of described filling connector between be less than or equal to ± 200 dusts of difference in height.
Preferably, the degree of depth of described the first opening is 50-150nm.
Preferably, c) step comprises: in described the first opening He on described front end device architecture surface, form packed layer; The packed layer of removing the upper surface that exceeds described front end device architecture through flatening process, forms described filling connector.
Preferably, the material of described packed layer is photoresist, antireflection material or amorphous carbon.
Preferably, described flatening process is cmp or eat-backs.
Preferably, the live width of the filling connector after described etching is 5-40nm.
Preferably, the gas passing in described isotropic etching process comprises O
2or Cl
2, and substrate bias power is 0-50W.
Preferably, in described isotropic etching process, also pass into HBr and CH
2f
2.
Preferably, described insulating barrier forms by selectivity sedimentation.
Preferably, described selectivity sedimentation is chemical liquid deposition.
Preferably, the material of described insulating barrier is silica.
Preferably, the filling connector after described etching adopts the mode of ashing to remove.
Preferably, in g) step and h) between step, also comprise the step that the front end device architecture to being formed with described insulating barrier cleans.
According to the method for invention, can reduce the contact area between bottom electrode and phase change layer, improve the efficiency of heating surface of bottom electrode to phase change layer, thereby effectively improve the read or write speed of phase change memory component.
Accompanying drawing explanation
Following accompanying drawing of the present invention is used for understanding the present invention in this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.In the accompanying drawings,
Fig. 1 is the sectional view of the phase change memory component of prior art;
Fig. 2 A-2H is according to the sectional view of each step in the method flow of embodiment of the present invention making phase change memory component;
Fig. 3 is the process chart of making phase change memory component according to embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details have been provided to more thorough understanding of the invention is provided.But, it will be apparent to one skilled in the art that the present invention can be implemented without one or more these details.In other example, for fear of obscuring with the present invention, be not described for technical characterictics more well known in the art.
In order thoroughly to understand the present invention, will detailed step be proposed in following description, so that how explanation the present invention makes phase change memory component.Obviously, execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Fig. 2 A-2H is according to the sectional view of each step in the method flow of one embodiment of the present invention making phase change memory component.
As shown in Figure 2 A, provide front end device architecture 200.First, provide and be formed with the isostructural substrate 201 of grid, source electrode, drain electrode and interlayer dielectric layer, for simplicity, described structure is all not shown in the drawings.Wherein, the material of interlayer dielectric layer can be chosen as low k (dielectric constant) material.In interlayer dielectric layer, there is the conductive plug of being made by electric conducting material that at least one exposes upper surface, for example tungsten latch.Then, form the first dielectric layer 202 and bottom electrode 202a on the surface of substrate 201, bottom electrode 202a aims at conductive plug.Wherein, the surrounding that the first dielectric layer 202 surrounds bottom electrode 202a, and bottom electrode 202a is exposed to the surface of front end device architecture 200.The material of the first dielectric layer 202 can be oxide, for example silica, and generation type can be chemical vapour deposition technique (CVD).The material of bottom electrode 202a can be doped polycrystalline silicon, W, TiN or TiAlN, it can be other silicide material, this silicide material can be at least one the silicide comprising in Ag, Au, Al, Cu, Cr, Co, Ni, Ti, Sb, V, Mo, Ta, Nb, Ru, W, Pt, Pd, Zn and Mg, is preferably WSi.The method that forms bottom electrode 202a can, for first define the opening of bottom electrode pattern in the first dielectric layer 202, then be filled into bottom electrode material in opening.Substrate 201, bottom electrode 202a and the common formation front end of the first dielectric layer 202 device architecture 200.
As shown in Figure 2 B, eat-back the top of removing bottom electrode 202a, form the first opening 203 in the surface of front end device architecture 200.The width (D) of the first opening 203 is 50-100nm, and the degree of depth (H) of the first opening 203 is 50-150nm.Described etch-back technics can adopt isotropic dry etching, for example, and low substrate bias power (0-50W) etching or remote plasma etching.The reacting gas passing in etching process comprises fluorine-based compound, for example SF
6, CF
4, C
2f
6and NF
3deng in one or more.In addition, etching gas can also comprise protective gas, for example, in nitrogen, helium and argon gas one or more.
As shown in Figure 2 C, fill connector 204 in the interior formation of the first opening 203.Concrete formation method can be the first opening 203 in and front end device architecture 200 surfaces on, adopt traditional handicraft, for example, the modes such as coating or deposition, formation packed layer.The upper surface of described packed layer is higher than the upper surface of front end device architecture 200, and the material of described packed layer can be photoresist, antireflection material or amorphous carbon etc.Then, through flatening process, for example, cmp (CMP) or the mode such as eat-back, removes the packed layer of the upper surface that exceeds front end device architecture 200, forms and fills connector 204.Fill connector 204 and there is the width (D) identical with the first opening 203.
As shown in Figure 2 D, eat-back and remove the top of the first dielectric layer 202, make to fill the upper surface of connector 204 higher than the upper surface of remaining the first dielectric layer 202.Preferably, make be less than or equal to ± 200 dusts of difference in height between the upper surface of remaining the first dielectric layer 202 and the lower surface of filling connector 204.Eat-back the upper surface of rear filling connector 204 higher than the upper surface of remaining the first dielectric layer 202., adopting self aligned mode to make to fill between connector 204 and bottom electrode 202a aims at completely.Described etch-back technics can adopt dry etching or wet etching.The reacting gas passing in dry etching process comprises fluorocarbon, for example CHF
3, CH
2f
2, CF
4, C
4f
8deng in one or more.In addition, etching gas can also comprise protective gas, for example, in nitrogen, helium and argon gas one or more.Substrate bias power is 100-1000W.Wet etching can adopt the solution that comprises HF.
As shown in Figure 2 E, isotropic etching is filled connector 204, to dwindle the live width of filling connector 204.The reacting gas passing into comprises oxygen or chlorine, and reacting gas can also comprise HBr and CH
2f
2.Substrate bias power is 0-50W, is preferably 0W.According to one embodiment of the present invention, the gas of isotropic etching comprises O
2, CH
2f
2and HBr, O
2flow velocity be 10-100sccm, the flow velocity of HBr is 0-80sccm, CH
2f
2flow velocity be 10-20sccm.Wherein, sccm is under standard state, namely 1 cubic centimetre of (1cm per minute under 1 atmospheric pressure, 25 degrees Celsius
3/ min) flow.In addition, in reacting gas, can also comprise inert gas, to play the effects such as protection and dilution.After isotropic etching, fill connector 204 and there is less live width (d), can be 5-40nm.
As shown in Figure 2 F, the region that filling connector 204 after not being etched on front end device architecture 200 surfaces covers forms insulating barrier 205, and the upper surface of the insulating barrier 205 forming need be lower than the upper surface of the filling connector 204 after etching, or with etching after the upper surface flush of filling connector 204.The method that forms insulating barrier 205 is selectivity sedimentation, and for front end device architecture 200, the region that only the filling connector 204 after not being etched covers forms insulating barrier 205, and on the surface of the filling connector 204 after etching, does not form insulating barrier.Described selectivity sedimentation is for example chemical liquid deposition.The material of insulating barrier 205 is silica.
As shown in Figure 2 G, remove the filling connector 204 after etching, form the second opening 210, the filling connector 204 after described etching adopts the mode of ashing to remove.Then, alternatively, the front end device architecture 200 that is formed with insulating barrier 205 is cleaned, to remove in the second opening 210 and the lip-deep residue of insulating barrier 205.
As shown in Fig. 2 H, on the surface of insulating barrier 205, form the second dielectric layer 206 and phase change layer 206a, wherein, the surrounding that the second dielectric layer 206 surrounds phase change layer 206a.Phase change layer 206a be positioned at bottom electrode 202a directly over, and phase change layer 206a fills the second opening 210.Then, on the second dielectric layer 206 and phase change layer 206a, form the 3rd dielectric layer 207 and top electrodes 207a, wherein, the surrounding that the 3rd dielectric layer 207 surrounds top electrodes 207a.Top electrodes 207a is positioned at the upper position of aiming at bottom electrode 202a of phase change layer 206a, thereby completes the making of phase change memory component.
Make the method for phase change memory component according to embodiment of the present invention, adopt in the insulating barrier of self-aligned manner between phase change layer and bottom electrode and form opening, dwindled the contact area of phase change layer and bottom electrode, and opening be positioned at exactly bottom electrode directly over.Therefore, the method according to this invention, has improved the contact resistance of phase change layer and bottom electrode effectively.In the time phase change layer being heated by bottom electrode, obtain good heating effect, thereby improved the read or write speed of phase change memory component.In addition, the contact area of phase change layer and bottom electrode can be adjusted by technique, simple and convenient, is easy to manufacture.
As shown in Figure 3, for make the process chart of phase change memory component according to embodiment of the present invention.In step 301, front end device architecture is provided, described front end device architecture comprises the first dielectric layer and bottom electrode, wherein the first dielectric layer surrounds the surrounding of bottom electrode, and bottom electrode is exposed to the surface of front end device architecture.In step 302, eat-back the top of removing bottom electrode, form the first opening in the surface of front end device architecture.In step 303, in the first opening, form and fill connector.In step 304, eat-back and remove the top of the first dielectric layer, make to fill the upper surface of connector higher than the upper surface of remaining the first dielectric layer.In step 305, isotropic etching is filled connector, to dwindle the live width of filling connector.In step 306, the region that filling connector after not being etched on front end device architecture surface covers forms insulating barrier, and the upper surface of the insulating barrier forming need be lower than the upper surface of the filling connector after etching, or with etching after the upper surface flush of filling connector.In step 307, adopt the modes such as ashing to remove the filling connector after etching, to form the second opening.In step 308, on insulating barrier, form the second dielectric layer and phase change layer, wherein, the second dielectric layer surrounds the surrounding of phase change layer, phase change layer be positioned at bottom electrode directly over, and phase change layer is filled the second opening.On the second dielectric layer and phase change layer, form the 3rd dielectric layer and top electrodes, wherein, the 3rd dielectric layer surrounds the surrounding of top electrodes, top electrodes be positioned at phase change layer directly over.Complete the making of phase change memory component.
Can be applicable in multiple integrated circuit (IC) according to the phase change memory component of embodiment manufacture as above.For example memory circuitry according to IC of the present invention, as random access memory (RAM), dynamic ram (DRAM), synchronous dram (SDRAM), static RAM (SRAM) (SRAM) or read-only memory (ROM) etc.Can also be logical device according to IC of the present invention, as programmable logic array (PLA), application-specific integrated circuit (ASIC) (ASIC), combination type DRAM logical integrated circuit (buried type dynamic random access memory), radio-frequency devices or other circuit devcies arbitrarily.IC chip according to the present invention can be used for for example consumer electronic products, in the various electronic products such as personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera, digital camera, mobile phone, especially in radio frequency products.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment is the object for giving an example and illustrating just, but not is intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (14)
1. a method of making phase change memory component, comprising:
A) provide front end device architecture, described front end device architecture comprises the first dielectric layer and bottom electrode, and wherein, described the first dielectric layer surrounds the surrounding of described bottom electrode, and described bottom electrode is exposed to the surface of described front end device architecture;
B) eat-back the top of removing described bottom electrode, form the first opening in the surface of described front end device architecture;
C) in described the first opening, form and fill connector;
D) eat-back the top of removing described the first dielectric layer, make the upper surface of described filling connector higher than the upper surface of remaining the first dielectric layer;
E) described in isotropic etching, fill connector, to dwindle the live width of described filling connector;
F) region that the filling connector after not being etched on the surface of described front end device architecture covers forms insulating barrier, the upper surface of the filling connector of the upper surface of described insulating barrier after lower than described etching, or with described etching after the upper surface flush of filling connector;
G) remove the filling connector after described etching, to form the second opening;
H) on described insulating barrier, form the second dielectric layer and phase change layer, wherein, described the second dielectric layer surrounds the surrounding of described phase change layer, described phase change layer be positioned at described bottom electrode directly over, and fill described the second opening;
I) on described the second dielectric layer and described phase change layer, form the 3rd dielectric layer and top electrodes, wherein, the surrounding that described the 3rd dielectric layer surrounds described top electrodes, described top electrodes is positioned at the position of aiming at described bottom electrode on described phase change layer.
2. the method for claim 1, is characterized in that, be less than or equal to ± 200 dusts of difference in height between the upper surface of described remaining the first dielectric layer and the lower surface of described filling connector that d) step obtains.
3. the method for claim 1, is characterized in that, the degree of depth of described the first opening is 50-150nm.
4. the method for claim 1, is characterized in that, c) step comprises:
In described the first opening He on described front end device architecture surface, form packed layer;
The packed layer of removing the upper surface that exceeds described front end device architecture through flatening process, forms described filling connector.
5. method as claimed in claim 4, is characterized in that, the material of described packed layer is photoresist, antireflection material or amorphous carbon.
6. method as claimed in claim 4, is characterized in that, described flatening process is cmp or eat-backs.
7. the method for claim 1, is characterized in that, the live width of the filling connector after described etching is 5-40nm.
8. the method for claim 1, is characterized in that, the gas passing in described isotropic etching process comprises O
2or Cl
2, and substrate bias power is 0-50W.
9. method as claimed in claim 8, is characterized in that, in described isotropic etching process, also passes into HBr and CH
2f
2.
10. the method for claim 1, is characterized in that, described insulating barrier forms by selectivity sedimentation.
11. methods as claimed in claim 10, is characterized in that, described selectivity sedimentation is chemical liquid deposition.
12. the method for claim 1, is characterized in that, the material of described insulating barrier is silica.
13. the method for claim 1, is characterized in that, the filling connector after described etching adopts the mode of ashing to remove.
14. the method for claim 1, is characterized in that, in g) step and h) between step, also comprise the step that the front end device architecture to being formed with described insulating barrier cleans.
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