CN104716258B - Semiconductor devices and preparation method thereof - Google Patents
Semiconductor devices and preparation method thereof Download PDFInfo
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- CN104716258B CN104716258B CN201310681667.8A CN201310681667A CN104716258B CN 104716258 B CN104716258 B CN 104716258B CN 201310681667 A CN201310681667 A CN 201310681667A CN 104716258 B CN104716258 B CN 104716258B
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Abstract
The invention discloses a kind of semiconductor devices and preparation method thereof.Methods described includes：Semiconductor substrate is provided；Dielectric layer is formed on the semiconductor substrate, is formed in the dielectric layer fluted；In the groove and phase-change material layers are formed on the dielectric layer, the phase-change material layers fill up the groove；Protective layer is formed on the phase-change material layers；And CMP process is performed, remove the phase-change material layers beyond the protective layer and the groove.According to the method for the making semiconductor devices of the present invention, protective layer is formed above phase-change material layers.The protective layer covers phase-change material layers in CMP process, can protect phase-change material layers, avoids extracting phase-change material layers completely in polishing process.
Description
Technical field
The present invention relates to semiconductor fabrication process, more particularly to a kind of semiconductor devices and preparation method thereof.
Background technology
Phase transition storage (PCM) is a kind of non-volatile semiconductor memory of rising in recent years.With traditional memory
Compare, it have small memory cell size, high read or write speed, low-power consumption, have extended cycle life it is excellent with excellent anti-radiation performance etc.
Point.There is advantage based on above-mentioned, phase transition storage can not only substitute existing memory, but also not reach in normal memory
Some fields (field such as space, space technology and military affairs) produce new application.
Fig. 1 is the sectional view of the phase-changing memory unit of prior art.As shown in figure 1, phase-changing memory unit 100 includes
Bottom electrode 101, phase transformation connector 102 and top electrodes 103.Bottom electrode 101, phase transformation connector 102 and top electrodes 103 are by being situated between
Electric layer 104 is surrounded isolates with peripheral devices.Phase transformation connector 102 is formed by phase-change material (such as Ge-Sb-Te phase-change materials).No
Electric current with intensity flows through phase transformation connector 102, by electric current flow through fuel factor caused by phase transformation connector 102 by phase-change material by
Crystalline state (SET states) is changed into amorphous state (RESET state), you can be resetted (RESET) operation to phase-change material.
Its phase is changed into crystalline state and amorphous state, phase change memory by phase-change material by local pyrexia caused by electric pulse
Device is exactly the semiconductor devices using characteristic storage binary message.Phase transition storage is the memory based on resistance, is passed through
Conversion of the phase-change material between crystalline state and amorphous state and the resistance characteristic of low-resistance and high resistant is accordingly presented to reach storage binary system
The purpose of information.
The generation type of phase transformation connector 102 comprises the following steps：As shown in Figure 2 A, formation and bottom in dielectric layer 104
The opening 105 that electrode 101 is aligned；As shown in Figure 2 B, phase-change material layers 106 are formed in opening 105 and on dielectric layer 104；Such as
Shown in Fig. 2 C, execution CMP process removes phase-change material layers except the opening, to form phase transformation connector 106.But
The adhesion of phase-change material layers 106 and dielectric layer 104 below is poor, and due to the characteristic of itself of phase-change material layers 106 without
Method forms glue-line between phase-change material layers 106 and dielectric layer 104.This causes to be easy to open in CMP process
Phase-change material layers 106 in mouth 105 pull out, as shown in Figure 2 C.And as critical size reduces, in order to expand sediment phase change material
The process window of the bed of material 106 (for example with physical vapour deposition (PVD) or chemical vapor deposition), it will usually form shallow phase transformation connector
102.The phase-change material layers 106 that so can further increase in opening 105 are drawn out in CMP process.
Therefore, it is necessary to a kind of semiconductor devices and preparation method thereof, at least to solve to a certain extent in the prior art
The problem of existing.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will enter in specific embodiment part
One step describes in detail.The Summary of the present invention is not meant to attempt to limit technical scheme claimed
Key feature and essential features, the protection domain for attempting to determine technical scheme claimed is not meant that more.
The present invention provides a kind of preparation method of semiconductor devices, and methods described includes：Semiconductor substrate is provided；Described
Dielectric layer is formed in Semiconductor substrate, is formed in the dielectric layer fluted；Shape in the groove and on the dielectric layer
Into phase-change material layers, the phase-change material layers fill up the groove；Protective layer is formed on the phase-change material layers；And perform
CMP process, remove the phase-change material layers beyond the protective layer and the groove.
Preferably, the polishing speed of the protective layer is less than the polishing speed of the phase-change material layers.
Preferably, the adhesion of the protective layer is more than the adhesion of the phase-change material layers.
Preferably, the protective layer includes the one or more in TiN, TaN, Ti, Ta.
Preferably, the thickness of the protective layer is
Preferably, methods described is used to form the phase transformation connector for phase transition storage.
Preferably, bottom electrode is also formed with the dielectric layer, the bottom electrode is located under the phase transformation connector
Electrically connect just and with the phase transformation connector.
Preferably, methods described is additionally included in the surface of the phase transformation connector and is formed and electrically connect with the phase transformation connector
Top electrodes.
The present invention also provides a kind of semiconductor devices, and the semiconductor devices is using any method shape as described above
Into.
According to the method for the making semiconductor devices of the present invention, protective layer is formed above phase-change material layers.The protection
Layer covers phase-change material layers in CMP process, can protect phase-change material layers, avoid phase in polishing process
Change material layer is extracted completely.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, for explaining the principle of the present invention.In the accompanying drawings,
Fig. 1 is the sectional view of the phase-changing memory unit of prior art；
Fig. 2A -2C are the sectional views that prior art shape makees the device that each step obtains during phase transformation connector；
Fig. 3 is the process chart that semiconductor devices is made according to one embodiment of the invention；And
Fig. 4 A-4F are to make the device that each step during semiconductor devices obtains according to one embodiment of the invention
Sectional view.
Embodiment
Next, the present invention will be more fully described by with reference to accompanying drawing, shown in the drawings of embodiments of the invention.But
It is that the present invention can be implemented in different forms, and should not be construed as being limited to embodiments presented herein.On the contrary, provide
These embodiments will make disclosure thoroughly and complete, and will fully convey the scope of the invention to those skilled in the art.
In accompanying drawing, for clarity, the size and relative size in Ceng He areas may be exaggerated.Same reference numerals represent phase from beginning to end
Same element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " other
When element or layer, its can directly in other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
Person may have element or layer between two parties.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or when " being directly coupled to " other elements or layer, then element or layer between two parties is not present.
According to an aspect of the present invention, there is provided a kind of preparation method of semiconductor devices.Fig. 3 is shown according to the present invention
The flow chart of the preparation method of the semiconductor devices of one embodiment, Fig. 4 A-4F show using the flow chart shown in Fig. 3 come
The sectional view for the device that each step obtains during making semiconductor devices.Below in conjunction with the flow chart and figure shown in Fig. 3
The preparation method of the semiconductor devices of the semiconductor devices sectional view description present invention shown in 4A-4F.
Perform step 301：Semiconductor substrate is provided.
As shown in Figure 4 A, there is provided Semiconductor substrate 400.The Semiconductor substrate 400 can be silicon, silicon-on-insulator (SOI),
Be laminated on insulator silicon (SSOI), be laminated on insulator SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and
At least one of germanium on insulator (GeOI).The shallow trench for isolating active area is could be formed with Semiconductor substrate 400
Isolate (STI) etc., shallow trench isolation can be by silica, silicon nitride, silicon oxynitride, Fluorin doped glass and/or other are existing
Dielectric materials are formed.Certainly, can also be formed with other devices, such as transistor etc. in Semiconductor substrate 400.In order to scheme
Show succinctly, only represent Semiconductor substrate 400 with square frame herein.
Perform step 302：Dielectric layer is formed on a semiconductor substrate, is formed in the dielectric layer fluted.
As shown in Figure 4 B, dielectric layer 410 is formed in Semiconductor substrate 400.Dielectric layer 410 can be silicon oxide layer, including
Have using what thermal chemical vapor deposition (thermal CVD) manufacturing process or high-density plasma (HDP) manufacturing process were formed
The material layer of doped or undoped silica, such as undoped silica glass (USG), phosphorosilicate glass (PSG) or boron phosphorus silicon
Glass (BPSG).In addition, dielectric layer 410 can also be the spin cloth of coating-type glass (spin-on- for adulterating boron or adulterating phosphorus
Glass, SOG), doping phosphorus tetraethoxysilane (PTEOS) or adulterate boron tetraethoxysilane (BTEOS).
In addition, the material of dielectric layer 410 can also include such as fluorocarbon (CF), carbon doped silicon oxide (SiOC) or
Carbonitride of silicium (SiCN) etc..Or film that SiCN films are formd on fluorocarbon (CF) etc. can also be used.Carbon is fluorinated
Compound is with fluorine (F) and carbon (C) for main component.Fluorocarbon can also use the thing constructed with noncrystal (amorphism)
Matter.Dielectric layer 410 can also use the Porous such as carbon doped silicon oxide (SiOC) to construct.
With continued reference to Fig. 4 B, fluted 402 are formed in dielectric layer 410, the groove 402 is used to fill phase-change material layers.It is recessed
Groove 402 is, for example, to be formed using photoetching process commonly used in the art.In one embodiment, it is filled in groove 402
Phase-change material layers can be as the phase transformation connector of phase-changing memory unit.The embodiment will be described hereinafter.
In addition, in the embodiment for forming phase-changing memory unit, bottom electrode 401 can be formed in dielectric layer 410.And
And the exposed bottom electrode 401 of groove 402.Groove 402 is preferably aligned with bottom electrode 401.Bottom electrode 401 is by dielectric layer
410 surround in order to which peripheral devices are kept apart.In fact, it is also possible in Semiconductor substrate 400 formed with conductive plug, such as tungsten
Latch, the conductive plug are used to electrically connect with bottom electrode 401.As an example, the material of bottom electrode 401 can be Si or mix
Miscellaneous polysilicon.Forming the method for the structure described in Fig. 4 B can include：Go out bottom electrode figure defined in dielectric layer 410 first
Bottom electrode material, is then filled into opening by the opening of case, to form bottom electrode 401；Then, in the He of dielectric layer 410
Go out groove 402 defined in bottom electrode 401, the top of bottom electrode 401 is eliminated when defining groove 402, groove 402 is located at bottom
The surface of portion's electrode 401.
Perform step 303：In groove and phase-change material layers are formed on dielectric layer, phase-change material layers fill up groove.
As shown in Figure 4 C, the phase-change material layers 403 can be formed using existing process.By germanium (Ge)-antimony (Sb)-tellurium (Te)
The chalcogenide compound Ge of composition2Sb2Te5(GST) reversible transition between crystalline state and amorphous state, can be realized rapidly, turn into current
The most frequently used phase-change material in phase transition storage.
Perform step 304：Protective layer is formed on phase-change material layers.
As shown in Figure 4 D, protective layer 404 is formed on phase-change material layers 403.Protective layer 404 covers phase-change material layers 403,
In subsequent CMP process, protective layer 404 can avoid the phase-change material layers 403 in groove from being pulled out.As
Example, the thickness of protective layer 404 can beThe thickness of protective layer 404 can play well within the range
Protective effect, and can enough avoid extend the process time.
Preferably, the polishing speed of protective layer 404 is less than the polishing speed of phase-change material layers 403.Chemically-mechanicapolish polishing
Initial time section in, specifically, before the face A-A shown in Fig. 4 D is polished to, due to the protective layer 404 of formation itself
There can be small fluctuating (not shown) on surface, on the one hand the small fluctuating is due to the deposition work of protective layer 404
Caused by skill, the roughness on the surface of phase-change material layers 403 is on the other hand also inherited.Signified microrelief does not wrap herein
Include the larger depression 405 on the surface of protective layer 404 caused by groove 402.Main pin is polished in the initial time section
To the tip of the microrelief on the surface of protective layer 404.Based on tip place material layer relative to flat place material layer with compared with
This characteristic of big polishing speed, and can chemically-mechanicapolish polished as protective layer 404 from the less material of polishing speed
Initial time section in when Fig. 4 D shown in device surface fast flat.
Moreover it is preferred that the adhesion of protective layer 404 is preferably more than the adhesion of phase-change material layers 403.The adhesion
Refer in crystal existing interaction force between particle.During below face A-A and not up to face B-B is polished to, depression
Protective layer in 405 can play constraint effect to the crystal grain in phase-change material layers 403.Also, due to what is now polished
Surface relatively flat, therefore the risk that the phase-change material layers 403 in groove 402 are pulled out can be reduced.
Preferably, protective layer 404 can be the one or more in TiN, TaN, Ti, Ta.Above-mentioned material not only have compared with
Low polishing speed, but also there is larger adhesion.
Perform step 305：CMP process is performed, removes the phase-change material layers beyond protective layer and groove.
As shown in Figure 4 E, chemically-mechanicapolish polished, remove the phase-change material layers beyond protective layer 404 and groove 402
403.It is used to be formed in the embodiment of phase transformation connector of phase-changing memory unit in this method, phase transformation is completed after the completion of the step
The making of connector 406.Wherein, the lower section of phase transformation connector 406 is also formed with bottom electrode 401, and the bottom electrode 401 is inserted with phase transformation
The electrical connection of plug 406.
Further, this method also includes the step of forming top electrodes, as illustrated in figure 4f, phase transformation connector 406 just on
It is square to be electrically connected into top electrodes 407, top electrodes 407 with phase transformation connector 406.As an example, the making side of top electrodes 407
Method can include：First, dielectric layer 420 is formed on the device shown in Fig. 4 E (referring to Fig. 4 F)；Then, in dielectric layer 420
Definition is directly over phase transformation connector 406 and exposure phase transformation connector 406 is open；Finally, top electrode material is filled in opening,
To form top electrodes 407.As an example, the material of top electrodes 407 can be Si or DOPOS doped polycrystalline silicon.
In summary, according to the method for the making semiconductor devices of the present invention, formed and protected above phase-change material layers 403
Sheath 404.The protective layer 404 covers phase-change material layers 403 in CMP process, can protect phase-change material layers
403, avoid extracting phase-change material layers 403 completely in polishing process.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in described scope of embodiments.In addition people in the art
Member can also make more kinds of it is understood that the invention is not limited in above-described embodiment according to the teachings of the present invention
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (8)
1. a kind of preparation method of semiconductor devices, it is characterised in that methods described includes：
Semiconductor substrate is provided；
Dielectric layer is formed on the semiconductor substrate, is formed in the dielectric layer fluted；
In the groove and phase-change material layers are formed on the dielectric layer, the phase-change material layers fill up the groove；
Protective layer is formed on the phase-change material layers, the adhesion of the protective layer is more than the combination of the phase-change material layers
Power, the adhesion refer in crystal existing interaction force between particle；And
CMP process is performed, removes the phase-change material layers beyond the protective layer and the groove.
2. the method as described in claim 1, it is characterised in that the polishing speed of the protective layer is less than the phase-change material layers
Polishing speed.
3. the method as described in claim 1, it is characterised in that the protective layer include TiN, TaN, Ti, Ta in one kind or
It is a variety of.
4. the method as described in claim 1, it is characterised in that the thickness of the protective layer is
5. the method as described in claim 1, it is characterised in that methods described is used for the phase transformation connector for forming phase transition storage.
6. method as claimed in claim 5, it is characterised in that bottom electrode, the bottom are also formed with the dielectric layer
Electrode is located at the lower section of the phase transformation connector and electrically connected with the phase transformation connector.
7. method as claimed in claim 5, it is characterised in that methods described is additionally included in the surface shape of the phase transformation connector
Into the top electrodes electrically connected with the phase transformation connector.
8. a kind of semiconductor devices, the semiconductor devices is formed using the method any one of claim 1-7.
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| CN101770954A (en) * | 2008-12-29 | 2010-07-07 | 中芯国际集成电路制造(上海)有限公司 | Forming method of flash memory |
| CN102468430A (en) * | 2010-11-05 | 2012-05-23 | 中芯国际集成电路制造(上海)有限公司 | Implementation method for improving adhesiveness of phase change material |
| CN102569646A (en) * | 2010-12-22 | 2012-07-11 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of phase change memory |
| CN102956821A (en) * | 2011-08-24 | 2013-03-06 | 台湾积体电路制造股份有限公司 | Phase change memory and method of fabricating same |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100546406B1 (en) * | 2004-04-10 | 2006-01-26 | 삼성전자주식회사 | Method for manufacturing phase-change memory element |
| TW200903777A (en) * | 2007-07-05 | 2009-01-16 | Ind Tech Res Inst | Phase-change memory element and method for fabricating the same |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101770954A (en) * | 2008-12-29 | 2010-07-07 | 中芯国际集成电路制造(上海)有限公司 | Forming method of flash memory |
| CN102468430A (en) * | 2010-11-05 | 2012-05-23 | 中芯国际集成电路制造(上海)有限公司 | Implementation method for improving adhesiveness of phase change material |
| CN102569646A (en) * | 2010-12-22 | 2012-07-11 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of phase change memory |
| CN102956821A (en) * | 2011-08-24 | 2013-03-06 | 台湾积体电路制造股份有限公司 | Phase change memory and method of fabricating same |
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