CN102402709A - 记忆卡封装结构及其制造方法 - Google Patents

记忆卡封装结构及其制造方法 Download PDF

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CN102402709A
CN102402709A CN2011102060446A CN201110206044A CN102402709A CN 102402709 A CN102402709 A CN 102402709A CN 2011102060446 A CN2011102060446 A CN 2011102060446A CN 201110206044 A CN201110206044 A CN 201110206044A CN 102402709 A CN102402709 A CN 102402709A
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magnetic
substrate
ducting layer
memory card
packaging structure
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CN102402709B (zh
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蓝文相
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Aptos Technology Inc
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Abstract

一种记忆卡封装结构，包括：一基板，含有一天线模块；一第一与第二磁性导波，分别设置于基板的相对一上表面与一下表面；一芯片，设置于第一磁性导波层上并与基板电性连接；以及一封胶体，包覆芯片、第一磁性导波层与基板的上表面。一种记忆卡封装结构的制造方法也于此处提出。藉由在封装结构内直接设置磁性导波材料，可在不增加记忆卡封装结构厚度的前提下，将信号从记忆卡的水平方向导出，以延长信号传输距离。

Description

记忆卡封装结构及其制造方法
技术领域
本发明涉及一种记忆卡封装技术，特别是一种记忆卡封装结构及其制造方法。
背景技术
随着数字相机、移动电话、个人数字助理器、影音播放器等数字产品的不断推陈出新，功能加强、体积缩小，已渐渐成为消费者生活中不可缺少的物品，而用以储存数据的记忆卡也是使得此类产品发挥最大功效的功臣之一。
伴随着计算机与网络通信等产品功能急速提升，必需具备多元化、可移植性与轻薄微小化的需求，因此，提高容量、缩小尺寸及多元化是记忆卡结构设计不变的开发方向。
发明内容
为了解决上述问题，本发明目的之一是提供一种记忆卡封装结构及其制造方法，藉由在封装体内直接设置磁性导波材料，可在不增加记忆卡封装结构厚度的前提下，将信号从记忆卡的水平方向导出，以延长信号传输距离。
本发明目的之一是提供一种记忆卡封装结构，包括：一基板，包括一天线模块；一第一磁性导波层，设置于基板的上表面，且至少覆盖天线模块；一芯片，设置于第二磁性导波层上并与基板电性连接；一封胶体，用以包覆基板的芯片、第一磁性导波层与上表面；以及一第二磁性导波层，设置于基板的下表面，其中第一磁性导波层与第二磁性导波层所设置的位置至少需涵盖天线模块的位置范围。
本发明目的之一是提供一种记忆卡封装结构的制造方法，包括下列步骤：提供一基板，其中基板含有一天线模块；设置一第一磁性导波层于基板的上表面上，且至少覆盖天线模块；设置一芯片于第一磁性导波层上，并使芯片与基板电性连接；形成一封胶体以包覆基板的芯片、第一磁性导波层与上表面；以及设置一第二磁性导波层于基板的下表面上，其中第一磁性导波层与第二磁性导波层所设置的位置至少需涵盖天线模块的位置范围。
以下藉由具体实施例配合附图详加说明，将更容易了解本发明的目的、技术内容、特点及其所达成的功效。
附图说明
图1为本发明一实施例的芯片封装结构的制造方法的流程图。
图2为本发明一实施例的芯片封装结构的结构剖视图。
图3为本发明又一实施例的芯片封装结构的结构剖视图。
图4A、4B为本发明又一实施例的芯片封装结构的结构剖视图。
图5A、5B为本发明又一实施例的芯片封装结构的结构剖视图及其下视示意图。
主要组件符号说明
10        基板
11，13    表面
12                      天线模块
20，22                  磁性导波层
21                      孔洞
30                      芯片
40                      金线
42                      凸块
50                      封胶体
60                      信号输出单元
62                      金手指
S10，S20，S30，S40，S50 步骤
具体实施方式
其详细说明如下，所述优选实施例仅做一说明而并非用以限定本发明。
请参考图1，图1为本发明一实施例的记忆卡封装结构的制造方法的流程图。如图所示，首先，提供一基板(步骤S10)，其中基板具有一天线模块，天线模块可设置于基板的上表面或者内置于基板中。接着，设置一第一磁性导波层于基板的上表面上(步骤S20)。然后，设置一芯片于第一磁性导波层上，并使芯片与基板电性连接(步骤S30)。接着，形成一封胶体以包覆芯片、第一磁性导波层与基板的上表面(步骤S40)。最后，设置一第二磁性导波层于基板的下表面上，其中第一磁性导波层与第二磁性导波层所设置的位置至少需涵盖天线模块的位置范围(步骤S50)。在一实施例中，第一磁性导波层与第二磁性导波层具有胶层，故第一磁性导波层与第二磁性导波层可利用黏贴的方式而设置于基板上。
接续上述，在又一实施例中，第一磁性导波层与第二磁性导波层也可同时形成在基板上，以缩短工艺步骤。本发明的工艺，可将一磁性导波层直接设置于封装结构内，不仅不会增加结构的厚度，两个磁性导波层也可共同作用以限定天线模块的信号的发射方向。
在一实施例中，请参考图2，图2为本发明一实施例的记忆卡封装结构的剖视图。此结构包括但不限于以上述制造方法制造而成，如图所示，一种记忆卡封装结构包括：一基板10，包括一天线模块12，天线模块12可设置于基板10的上表面11或者内置于基板10中，在此实施例中，天线模块12设置于基板10的上表面11。一第一磁性导波层20设置于基板10的上表面11，且至少覆盖天线模块12。一芯片30，例如近场通信芯片(near filed communication chip，NFC chip)或无线射频芯片(RFID chip)，设置于第一磁性导波层20上并与基板10电性连接。在本实施例中，利用多条金线40以打线的方式电性连接芯片30与基板10。一封胶体50包覆芯片30、第一磁性导波层20与基板10的上表面11。以及，一第二磁性导波层22设置于基板10的下表面13，其中第一磁性导波层20与第二磁性导波层22所设置的位置至少需涵盖天线模块12的位置范围，藉以将天线模块12的信号从记忆卡封装结构的水平方向导出，从而延长天线模块12的信号传输距离。
接续上述，在一实施例中，一信号输出单元60，设置于基板10的下表面13上，用以输出或使外界装置输入数据与信号。且在本实施例中，第二磁性导波层22覆盖下表面13并仅露出信号输出单元60所设置的位置，以形成较佳的遮蔽。而可以理解的，将磁性导波层20、22设置于基板10的上下两表面11、13并涵盖天线模块12的位置范围，除可将天线模块12的波或信号从记忆卡封装结构的水平方向导出之外，还不增加记忆卡封装结构的厚度，故可让设计者在记忆卡封胶体上黏贴其它的规范胶布，工艺上相当弹性。
请参考图3，在再一实施例中，记忆卡封装结构也可包括多个孔洞21贯穿第一磁性导波层20，其中芯片30可透过多条金线40穿过孔洞21与基板10电性连接。在此实施例中，磁性导波层大面积覆盖天线模块12可让导波效果更好。在一实施例中，请参考图4A与4B，芯片30也可利用多个凸块42以覆晶方式与基板10电性连接，其它结构与上述实施例相同，此处即不在赘述。
请参考图5A及图5B，5A及图5B为本发明又一实施例的记忆卡封装结构的剖视图与其下视示意图。如图所示，记忆卡封装结构包括一基板10，其中基板包括一天线模块12且多个金手指62设置于基板10的下表面13。如图所示，此实施例中，天线模块12内置于基板10内。一第一磁性导波层20，设置于基板10的上表面11；一第二磁性导波层22，设置于基板10的下表面13，并避开金手指62设置的位置。一芯片30，设置于第一磁性导波层10上并与基板10电性连接；以及一封胶体50，用以包覆芯片30、第一磁性导波层10与基板10的上表面11。在优选实施例中，第一磁性导波层20的面积大于等于天线模块12的面积且第二磁性导波层22的面积也大于等于天线模块12的面积，以提供较优的导波功能。
在上述实施例中，本发明的记忆卡封装结构包括但不限于微型记忆卡，只要记忆卡封装结构中具有天线模块，皆适用本发明的结构与工艺。
综合上述，本发明一实施例的一种记忆卡封装结构及其制造方法，藉由在封装结构内直接设置磁性导波材料，可在不增加记忆卡封装结构的厚度的前提下，将天线的信号从记忆卡封装结构的水平方向导出，以延长信号传输距离。
以上所述的实施例仅为说明本发明的技术思想及特点，其目的在使本领域技术人员能够了解本发明的内容并据以实施，而不能以此限定本发明，即凡是依本发明所公开的精神所作的均等变化或修饰，仍应涵盖在本发明的权利要求所限定的范围内。

Claims (10)

1.一种记忆卡封装结构，其特征在于，包括：
一基板，所述基板包括一天线模块；
一第一磁性导波层，所述第一磁性导波层设置于所述基板的上表面，且至少覆盖所述天线模块；
一芯片，所述芯片设置于所述第一磁性导波层上并与所述基板电性连接；
一封胶体，所述封胶体用以包覆所述芯片、所述第一磁性导波层与所述基板的所述上表面；以及
一第二磁性导波层，所述第二磁性导波层设置于所述基板的下表面，其中所述第一磁性导波层与所述第二磁性导波层所设置的位置至少需涵盖所述天线模块的位置范围。
2.如权利要求1所述的记忆卡封装结构，其特征在于，所述天线模块设置于所述基板的所述上表面上或设置于所述基板中。
3.如权利要求1所述的记忆卡封装结构，其特征在于，一信号输出单元设置于所述基板的所述下表面。
4.如权利要求3所述的记忆卡封装结构，其特征在于，所述信号输出单元包括多个金手指。
5.如权利要求1所述的记忆卡封装结构，其特征在于，所述芯片为近场通信芯片或无线射频芯片。
6.如权利要求1所述的记忆卡封装结构，其特征在于，所述芯片利用多条金线或多个凸块与所述基板电性连接。
7.如权利要求1所述的记忆卡封装结构，其特征在于，还包括多个孔洞贯穿所述第一磁性导波层。
8.一种记忆卡封装结构的制造方法，其特征在于，包括下列步骤：
提供一基板，其中所述基板含有一天线模块；
设置一第一磁性导波层于所述基板的上表面上，且至少覆盖所述天线模块；
设置一芯片于所述第一磁性导波层上，并使所述芯片与所述基板电性连接；
形成一封胶体包覆所述芯片、所述第一磁性导波层与所述基板的所述上表面；以及
设置一第二磁性导波层于所述基板的一下表面，其中所述第一磁性导波层与所述第二磁性导波层所设置的位置至少需涵盖该天线模块的位置范围。
9.如权利要求8所述的记忆卡封装结构的制造方法，其特征在于，所述第一磁性导波层与所述第二磁性导波层同时形成于所述基板上。
10.如权利要求8所述的记忆卡封装结构的制造方法，其特征在于，所述第一磁性导波层与所述第二磁性导波层是利用黏贴的方式而设置于所述基板上。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104022345A (zh) * 2013-03-01 2014-09-03 索尼公司 芯片级封装件
CN108171299A (zh) * 2017-12-19 2018-06-15 中电智能卡有限责任公司 一种智能卡的加工工艺

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102013105575A1 (de) * 2013-05-30 2014-12-04 Infineon Technologies Ag Chipkartenmodul, Chipkarte, und Verfahren zum Herstellen eines Chipkartenmoduls
KR102652721B1 (ko) * 2016-12-30 2024-03-28 인텔 코포레이션 고주파수 통신을 위한 3d 적층된 초박형 패키지 모듈로 설계된 마이크로 전자 디바이스
TWI739150B (zh) * 2019-08-30 2021-09-11 南茂科技股份有限公司 微型記憶體封裝結構以及記憶體封裝結構

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101159037A (zh) * 2006-09-29 2008-04-09 株式会社瑞萨科技 Rfid标贴标签及其制造方法
CN101281615A (zh) * 2007-04-03 2008-10-08 株式会社日立制作所 介质盒和电路图案板

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4737789A (en) * 1986-12-02 1988-04-12 X Cyte, Inc. Inductive antenna coupling for a surface acoustic wave transponder
CA2197283A1 (en) * 1996-02-13 1997-08-14 Mikio Horiuchi Card and information recording card and method of using the same
WO2004063977A2 (en) * 2003-01-03 2004-07-29 American Express Travel Related Services Company, Inc. Metal containing transaction card and method of making the same
JP2004328610A (ja) * 2003-04-28 2004-11-18 Matsushita Electric Ind Co Ltd アンテナ装置
US7404522B2 (en) * 2003-05-26 2008-07-29 Omron Corporation Information carrier, information recording medium, sensor, commodity management method
US8025237B2 (en) * 2006-01-20 2011-09-27 Panasonic Corporation Antenna built-in module, card type information device, and methods for manufacturing them

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101159037A (zh) * 2006-09-29 2008-04-09 株式会社瑞萨科技 Rfid标贴标签及其制造方法
CN101281615A (zh) * 2007-04-03 2008-10-08 株式会社日立制作所 介质盒和电路图案板

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104022345A (zh) * 2013-03-01 2014-09-03 索尼公司 芯片级封装件
CN108171299A (zh) * 2017-12-19 2018-06-15 中电智能卡有限责任公司 一种智能卡的加工工艺

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