CN102394651B - Programmable double integral type 32-bit ADC (analog-to-digital converter) - Google Patents
Programmable double integral type 32-bit ADC (analog-to-digital converter) Download PDFInfo
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- CN102394651B CN102394651B CN201110265067.4A CN201110265067A CN102394651B CN 102394651 B CN102394651 B CN 102394651B CN 201110265067 A CN201110265067 A CN 201110265067A CN 102394651 B CN102394651 B CN 102394651B
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Abstract
The invention relates to a programmable double integral type 32-bit ADC (analog-to-digital converter) which comprises a signal amplifying and processing circuit J0, a reference voltage supplying circuit J1, an operational amplifier J2, a comparator J3, a microprocessor J4 and a data communication module J5. Analog signals are converted into digital signals by processing data by each module. Through the programmable double integral type 32-bit ADC, the resolution of a double integral type ADC can be increased to 32 bits, thereby greatly meeting the requirement for high-precision physical quantity detection, and simultaneously simplifying the circuit structure as well as facilitating the control.
Description
Technical field
The present invention relates to 32 ADC of biproduct somatotype able to programme that a kind of circuit that analog signal is converted to digital signal, especially antijamming capability are strong, conversion accuracy is high.
Background technology
At present, known biproduct somatotype ADC can only convert at most specified analog quantity to 16 bit digital quantity, and resolution can reach 1/ (2
16), only can meet general measure requirement; The ADCShi TI company of 32 ∑-Δ types produces, and includes PGA amplifier, draw up high-frequency noise and fixing low-frequency disturbance ability; The ADC resolution of other types is lower than 24.In the process of exploitation high-resolution pressure-measuring system new product, use the ADC of existing 16 integral forms can not reach system 1/ (10
5) certainty of measurement requirement, use the ADC antijamming capability of 32 ∑-Δ types relatively poor, simultaneously price is too high.If a kind of 32 biproduct somatotype ADC can be provided, analog quantity can be converted to the more digital quantity of long number, meet the demand of the detection of high accuracy physical quantity, sample of high-resolution image and human-body biological input simultaneously.
Summary of the invention
In order to overcome existing ADC, do not meet the deficiency that high-precision signal detects, the invention provides 32 ADC of a kind of biproduct somatotype able to programme, these 32 ADC have solved the low shortcoming of existing biproduct somatotype ADC resolution, for high-precision signal measurement provides convenience.
The technical solution adopted for the present invention to solve the technical problems is: 32 ADC of this biproduct somatotype able to programme comprise that signal amplifies with treatment circuit J0, reference voltage circuit J1, operational amplifier J2, comparator J3, microprocessor J4 and data communication module J5 are provided.
Signal amplifies and treatment circuit J0 positive signal output Ui ' connecting resistance R2, switch triode T collector electrode is connected with one end of resistance R 2, "-" input of other end concatenation operation amplifier J2 of resistance R 2 and the Uc of integrating capacitor C end, "-" input of another termination J3 of C; T grounded emitter, the base stage of T is connected with the P1.0 end of microprocessor J4 by resistance R 1.
One end of the negative signal output H contact resistance R3 of signal amplification and treatment circuit J0, the other end of resistance R 3 connects provides the L of reference voltage circuit J1 end, J1 outputting standard reference voltage Ua and Ub, Ub connects "+" input of J2; Ua connects "+" input of comparator J3, the Q termination "+5V " power supply of J1.
"-" input of operational amplifier J2 is connected with R2, and "+" input of J2 is connected with the Ub of J1 end, and the output U0 of J2 is connected with "-" input of comparator J3.
Comparator circuit J3 has three links, and "+" end of J3 is connected with the Ua of J1, and "-" end of J3 is connected with the output U0 of J2, and the output Um of J3 is connected with the P3.2 pin of microprocessor J4.
The P1.0 pin of microprocessor J4 is connected with T base stage by resistance R 1, the P3.2 pin of J4 connects the output Um of J3, the TxD of J4, RxD pin are connected with 11 pins, 12 pins of data communication module J5, and J5 is the chip MAX232 that Transistor-Transistor Logic level is converted to 232 level.
Switch triode T is operated in cut-off and saturated two kinds of operating states, 1 or 0 control that this two states is sent by J4 pin P1.0, in the positive charge stage, P1.0 sends 0, T by, input signal Ui ' regularly charges by 2 couples of integrating capacitor C of resistance R, the charging interval arrives, charging process finishes, and at this moment U0 value is minimum; In reverse charging (electric discharge) stage, P1.0 sends 1, T is saturated, integrating capacitor C discharges over the ground by resistance R 2, along with increase discharge time, voltage U 0 increases, and when U0=Ua, J3 output voltage U m sports low level, Um is added in the P3.2 pin of J4, J4 produces outside 0 and interrupts, and electric discharge finishes, and J4 internal timing/counter T0/T1 records discharge time, the value of T0/T1 is through software filtering, re-use software and carry out after data processing, the digital quantity of changing as the analog quantity of input, exports from serial ports.
The conversion of positive charge stage to the reverse charging stage realized by timing, and the conversion of reverse charging stage to the positive charge stage realized by U0=Ua.Transfer process is realized jointly by software programming and hardware circuit.
Below Software for Design of the present invention is partly elaborated:
In 201 modules shown in Fig. 2, initialization system, enters endless loop: recursive call 202 modules and 203 modules.The data volume that 204 modules collect completes filtering, conversion by 202 modules; 204 modules complete after data processing, by 203 modules, the data after 204 resume module are sent to TxD by J4 serial and export with the 12 and 11 corresponding pins that serial received RxD pin is connected respectively MAX232.
The first step: when electric discharge finishes, J3 output Um is external interrupt 0 pin that the trailing edge of low level or level is given J4, and J4 response external interrupts 0,204 modules shown in calling graph 2.
In 204 modules shown in Fig. 2: read T0/T1 value as digital quantity characteristic value, initialization T1 is also arranged to counting mode, T0 puts initial value as positive charge timing, the P1.0 of J4 sends low level 0 base stage to T, collector electrode and the base stage of T are disconnected, Ui ', to integrating capacitor C charging, arranges the charge timing time, starts T0 regularly.
Second step: enter the forward timing charging stage, timer evenly rises in value in time-domain, until timing arrives, when positive charge finishes, U0 value is minimum, and the charge timing time arrives, and produces T0 Interruption, 206 modules shown in calling graph 2.
In 206 modules shown in Fig. 2: initialization T0, the P1.0 of J4 sends high level 1 base stage to T, starts counter T1/T0 and starts counting, and the every interruption of T0 once, makes T1+1.
The P1.0 of the 3rd step: J4 sends high level 1 base stage to T, makes collector electrode and the saturated short circuit of emitter of T, and integrating capacitor C discharges over the ground by the collector electrode of T, enters the reverse charging stage.
The 4th step: whenever T0 counts to expire and overflow, just produce T0 interruption, continue 206 modules shown in calling graph 2, in 206 modules, initialization T0, T1+1; The 4th step circulation is carried out, and along with the integrating capacitor C increase of discharge time, U0 constantly raises, when J2 output output voltage is elevated to U0=Ua, be comparator J3 "-" input terminal voltage U0 while equaling "+" input canonical reference voltage U a of J3, electric discharge finishes, and comparator J3 produces upset.
The 5th step: J3 output level Um becomes low level or exports trailing edge to the P3.2 pin of J4, J4 again produces outside 0 and interrupts, and turns back to the first step, 204 modules shown in calling graph 2, in 204 modules, read T0/T1 count value as the feature digital quantity of input analog signal conversion.If T1 overflows to produce and interrupts, data length surpasses 32, processes, if T1 does not produce interruption as invalid data, data are effective, and it is exactly the digital quantity of analog quantity conversion that feature digital quantity is multiplied by a coefficient (obtaining the coefficient of the corresponding digital quantity of feature digital quantity by data fitting).
32 ADC of this biproduct somatotype able to programme are used the T0/T1 of J4 inside, forward timing integration and back discharge integration adopt different scale counting clocks, reverse integral counting clock than the fast 8-12 of forward integration timer clock doubly, owing to having improved the count frequency of integrating capacitor C discharge process, improved analog-to-digital precision; Adopt software approach that 2 16 bit timings/counter chains of microprocessor J4 inside are connected into 32, realized 32 digit counter circuit; Ua, the Ub of the output of J1 module are relative voltage values, lower to supply voltage requirement, do not need special high-accuracy power source special.
The invention has the beneficial effects as follows, 32 ADC of this biproduct somatotype able to programme can bring up to 32 by the resolution of biproduct somatotype ADC, than existing 16 ADC resolution, 65536 times have been improved, met greatly the demand that high accuracy physical quantity detects, simultaneously, saved the necessary some logic switches of general adc circuit, timing circuit, counter circuit, logic control circuit, simplified capacitor charging/discharging controling circuit, simple in structure, it is convenient to control.
Accompanying drawing explanation
Below in conjunction with drawings and Examples, the invention will be further described.
Fig. 1 is 32 biproduct somatotype ADC structure charts of the present invention.
Fig. 2 is 32 biproduct somatotype ADC running software flow charts of the present invention.
Embodiment
In Fig. 1,32 ADC of this biproduct somatotype able to programme comprise that signal amplifies with treatment circuit J0, reference voltage circuit J1, operational amplifier J2, comparator J3, microprocessor J4 and data communication module J5 are provided.
Signal amplifies and treatment circuit J0 positive signal output Ui ' connecting resistance R2, switch triode T collector electrode is connected with one end of resistance R 2, "-" input of other end concatenation operation amplifier J2 of resistance R 2 and the Uc of integrating capacitor C end, "-" input of another termination J3 of C; T grounded emitter, the base stage of T is connected with the P1.0 end of microprocessor J4 by resistance R 1.
One end of the negative signal output H contact resistance R3 of signal amplification and treatment circuit J0, the other end of resistance R 3 connects provides the L of reference voltage circuit J1 end, J1 outputting standard reference voltage Ua and Ub, Ub connects "+" input of J2; Ua connects "+" input of comparator J3, the Q termination "+5V " power supply of J1.
"-" input of operational amplifier J2 is connected with R2, and "+" input of J2 is connected with the Ub of J1 end, and the output U0 of J2 is connected with "-" input of comparator J3.
Comparator circuit J3 has three links, and "+" end of J3 is connected with the Ua of J1, and "-" end of J3 is connected with the output U0 of J2, and the output Um of J3 is connected with the P3.2 pin of microprocessor J4.
The P1.0 pin of microprocessor J4 is connected with T base stage by resistance R 1, the P3.2 pin of J4 connects the output Um of J3, the TxD of J4, RxD pin are connected with 11 pins, 12 pins of data communication module J5, and J5 is the chip MAX232 that Transistor-Transistor Logic level is converted to 232 level.
Switch triode T is operated in cut-off and saturated two kinds of operating states, 1 or 0 control that this two states is sent by J4 pin P1.0, in the positive charge stage, P1.0 sends 0, T by, input signal Ui ' regularly charges by 2 couples of integrating capacitor C of resistance R, the charging interval arrives, charging process finishes, and at this moment U0 value is minimum; In reverse charging (electric discharge) stage, P1.0 sends 1, T is saturated, integrating capacitor C discharges over the ground by resistance R 2, along with increase discharge time, voltage U 0 increases, and when U0=Ua, J3 output voltage U m sports low level, Um is added in the P3.2 pin of J4, J4 produces outside 0 and interrupts, and electric discharge finishes, and J4 internal timing/counter T0/T1 records discharge time, the value of T0/T1 is through software filtering, re-use software and carry out after data processing, the digital quantity of changing as the analog quantity of input, exports from serial ports.
The conversion of positive charge stage to the reverse charging stage realized by timing, and the conversion of reverse charging stage to the positive charge stage realized by U0=Ua.Transfer process is realized jointly by software programming and hardware circuit.
Below Software for Design of the present invention is partly elaborated:
In 201 modules shown in Fig. 2, initialization system, enters endless loop: recursive call 202 modules and 203 modules.The data volume that 204 modules collect completes filtering, conversion by 202 modules; 204 modules complete after data processing, by 203 modules, the data after 204 resume module are sent to TxD by J4 serial and export with the 12 and 11 corresponding pins that serial received RxD pin is connected respectively MAX232.
The first step: when electric discharge finishes, J3 output Um is external interrupt 0 pin that the trailing edge of low level or level is given J4, and J4 response external interrupts 0,204 modules shown in calling graph 2.
In 204 modules shown in Fig. 2: read T0/T1 value as digital quantity characteristic value, initialization T1 is also arranged to counting mode, T0 puts initial value as positive charge timing, the P1.0 of J4 sends low level 0 base stage to T, collector electrode and the base stage of T are disconnected, Ui ', to integrating capacitor C charging, arranges the charge timing time, starts T0 regularly.
Second step: enter the forward timing charging stage, timer evenly rises in value in time-domain, until timing arrives, when positive charge finishes, U0 value is minimum, and the charge timing time arrives, and produces T0 Interruption, 206 modules shown in calling graph 2.
In 206 modules shown in Fig. 2: initialization T0, the P1.0 of J4 sends high level 1 base stage to T, starts counter T1/T0 and starts counting, and the every interruption of T0 once, makes T1+1.
The P1.0 of the 3rd step: J4 sends high level 1 base stage to T, makes collector electrode and the saturated short circuit of emitter of T, and integrating capacitor C discharges over the ground by the collector electrode of T, enters the reverse charging stage.
The 4th step: whenever T0 counts to expire and overflow, just produce T0 interruption, continue 206 modules shown in calling graph 2, in 206 modules, initialization T0, T1+1; The 4th step circulation is carried out, and along with the integrating capacitor C increase of discharge time, U0 constantly raises, when J2 output output voltage is elevated to U0=Ua, be comparator J3 "-" input terminal voltage U0 while equaling "+" input canonical reference voltage U a of J3, electric discharge finishes, and comparator J3 produces upset.
The 5th step: J3 output level Um becomes low level or exports trailing edge to the P3.2 pin of J4, J4 again produces outside 0 and interrupts, and turns back to the first step, 204 modules shown in calling graph 2, in 204 modules, read T0/T1 count value as the feature digital quantity of input analog signal conversion.If T1 overflows to produce and interrupts, data length surpasses 32, processes, if T1 does not produce interruption as invalid data, data are effective, and it is exactly the digital quantity of analog quantity conversion that feature digital quantity is multiplied by a coefficient (obtaining the coefficient of the corresponding digital quantity of feature digital quantity by data fitting).
32 ADC of this biproduct somatotype able to programme are used the T0/T1 of J4 inside, forward timing integration and back discharge integration adopt different scale counting clocks, reverse integral counting clock than the fast 8-12 of forward integration timer clock doubly, owing to having improved the count frequency of integrating capacitor C discharge process, improved analog-to-digital precision; Adopt software approach that 2 16 bit timings/counter chains of microprocessor J4 inside are connected into 32, realized 32 digit counter circuit; Ua, the Ub of the output of J1 module are relative voltage values, lower to supply voltage requirement, do not need special high-accuracy power source special.
Claims (1)
1. 32 ADC of biproduct somatotype able to programme, 32 ADC of this biproduct somatotype able to programme comprise that signal amplifies with treatment circuit J0, reference voltage circuit J1, operational amplifier J2, comparator J3, microprocessor J4 and data communication module J5 are provided, it is characterized in that: signal amplifies and treatment circuit J0 positive signal output Ui ' connecting resistance R2, switch triode T collector electrode is connected with one end of resistance R 2, the "-" input of other end concatenation operation amplifier J2 of resistance R 2 and the Uc of integrating capacitor C end, the "-" input of another termination J3 of C, T grounded emitter, the base stage of T is connected with the P1.0 end of microprocessor J4 by resistance R 1, one end of the negative signal output H contact resistance R3 of signal amplification and treatment circuit J0, the other end of resistance R 3 connects provides the L of reference voltage circuit J1 end, J1 outputting standard reference voltage Ua and Ub, Ub connects "+" input of J2, Ua connects "+" input of comparator J3, the Q termination "+5V " power supply of J1, the "-" input of operational amplifier J2 is connected with R2, and "+" input of J2 is connected with the Ub of J1 end, and the output U0 of J2 is connected with the "-" input of comparator J3, comparator circuit J3 has three links, and "+" end of J3 is connected with the Ua of J1, and the "-" end of J3 is connected with the output U0 of J2, and the output Um of J3 is connected with the P3.2 pin of microprocessor J4, the P1.0 pin of microprocessor J4 is connected with T base stage by resistance R 1, the P3.2 pin of J4 connects the output Um of J3, the TxD of J4, RxD pin are connected with 11 pins, 12 pins of data communication module J5, and J5 is the chip MAX232 that Transistor-Transistor Logic level is converted to 232 level, switch triode T is operated in cut-off and saturated two kinds of operating states, 1 or 0 control that this two states is sent by J4 pin P1.0, in the positive charge stage, P1.0 sends 0, T by, input signal Ui ' regularly charges by 2 couples of integrating capacitor C of resistance R, the charging interval arrives, charging process finishes, and at this moment U0 value is minimum, in reverse charging (electric discharge) stage, P1.0 sends 1, T is saturated, integrating capacitor C discharges over the ground by resistance R 2, along with increase discharge time, voltage U 0 increases, and when U0=Ua, J3 output voltage U m sports low level, Um is added in the P3.2 pin of J4, J4 produces outside 0 and interrupts, and electric discharge finishes, and J4 internal timing/counter T0/T1 records discharge time, T0/T1 value is through software filtering, re-use software and carry out after data processing, the digital quantity of changing as the analog quantity of input, exports from serial ports, the conversion of positive charge stage to the reverse charging stage realized by timing, and the conversion of reverse charging stage to the positive charge stage realized by U0=Ua, transfer process is realized jointly by software programming and hardware circuit, below Software for Design of the present invention is partly elaborated: the first step: when electric discharge finishes, J3 output Um is external interrupt 0 pin that the trailing edge of low level or level is given J4, and J4 response external interrupts 0, calls Int0 interrupt service routine 204 modules, in 204 modules: read T0/T1 value as feature digital quantity, initialization T1 is also arranged to counting mode, T0 puts initial value as positive charge timing, the P1.0 of J4 sends low level 0 base stage to T, collector electrode and the base stage of T are disconnected, Ui ', to integrating capacitor C charging, arranges the charge timing time, starts T0 regularly, second step: enter the forward timing charging stage, internal timing/counter T0/T1 evenly rises in value in time-domain, until timing arrives, when positive charge finishes, U0 value is minimum, the charge timing time arrives, and produces T0 Interruption, calls T0 interrupt service routine 206 modules, in 206 modules: initialization T0, the P1.0 of J4 sends high level 1 base stage to T, starts internal timing/counter T0/T1 and starts counting, and the every interruption of T0 once, makes T1+1, the P1.0 of the 3rd step: J4 sends high level 1 base stage to T, makes collector electrode and the saturated short circuit of emitter of T, and integrating capacitor C discharges over the ground by the collector electrode of T, enters the reverse charging stage, the 4th step: whenever T0 counts to expire and overflow, just produce T0 interruption, continue to call T0 interrupt service routine 206 modules, in 206 modules, initialization T0, T1+1, the 4th step circulation is carried out, and along with the integrating capacitor C increase of discharge time, U0 constantly raises, when J2 output output voltage is elevated to U0=Ua, be comparator J3 "-" input terminal voltage U0 while equaling "+" input canonical reference voltage U a of J3, electric discharge finishes, and comparator J3 produces upset, the 5th step: J3 output level Um becomes low level or exports trailing edge to the P3.2 pin of J4, J4 again produces outside 0 and interrupts, turn back to the first step, call Int0 interrupt service routine 204 modules, in 204 modules, read T0/T1 value as the feature digital quantity of input analog signal conversion, if T1 overflows to produce and interrupts, data length is over 32, as invalid data, process, if T1 does not produce interruption, data are effective, feature digital quantity is multiplied by the digital quantity that a coefficient is exactly analog quantity conversion, this coefficient is by data fitting, to obtain the coefficient of the corresponding digital quantity of feature digital quantity.
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| CN105024699B (en) * | 2014-04-24 | 2018-06-29 | 苏州迈略信息科技有限公司 | Double slope integrating analog to digital converter based on switching capacity feedback digital-to-analogue conversion |
| CN110071724A (en) * | 2019-06-06 | 2019-07-30 | 深圳市兆信电子仪器设备有限公司 | A kind of analog-digital converter |
| CN111696496A (en) * | 2020-06-22 | 2020-09-22 | 王诺 | Original sound shelf drum rotation digitalization and processing system thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3646587A (en) * | 1969-12-16 | 1972-02-29 | Hughes Aircraft Co | Digital-to-analog converter using field effect transistor switch resistors |
| CN101379405A (en) * | 2005-12-19 | 2009-03-04 | 硅谷实验室公司 | Current sensor |
| CN202218219U (en) * | 2011-09-01 | 2012-05-09 | 徐州师范大学 | Programmable double-integral 32-bit ADC |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3646587A (en) * | 1969-12-16 | 1972-02-29 | Hughes Aircraft Co | Digital-to-analog converter using field effect transistor switch resistors |
| CN101379405A (en) * | 2005-12-19 | 2009-03-04 | 硅谷实验室公司 | Current sensor |
| CN202218219U (en) * | 2011-09-01 | 2012-05-09 | 徐州师范大学 | Programmable double-integral 32-bit ADC |
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